DETAILED ACTION
This action is in response to Applicant’s Request for Continued Examination ("Response”) received on February 19, 2025 in response to the Office Action dated December 19, 2024. This action is made Non-Final.
Claims 1-20 are pending.
Claims 1, 12, and 18 are independent claims.
Claims 1-20 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s Response
In Applicant’s Response, Applicant amended claims 1-5, 9, 11, 12, 13, 15, 17, 18, and 20, and submitted arguments against the prior art in the Office Action dated December 19, 2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 12, 13, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatcher et al., US Publication 2019/0080230 (“Hatcher”), in view of Lee, US Publication 2017/0300806 (“Lee”), and further in view of Kaltiokallio, US Publication 2020/0395053 (“Kaltiokallio”).
Claim 1:
Hatcher teaches or suggests a resistance control unit of a neural network, comprising:
a plurality of resistors couped between a first node and a second node of a neural network (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0019 – hardware device 100 may be a hybrid analog-digital circuit; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.);
a plurality of switches coupled to ... and configured for setting a conductance between the first node and the second node based on selectively shorting out, none, a subset, or all of the plurality of resistors (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0019 – hardware device 100 may be a hybrid analog-digital circuit; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.); and
a plurality of memory cells configured for generating a digital output, (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0019 – hardware device 100 may be a hybrid analog-digital circuit; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.).
Hatcher does not explicitly disclose the plurality of resistors being based on one or more gate structures and a plurality of gate vias, each resistor of the plurality of resistors being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias ...; ... wherein the plurality of switches is controlled by the digital output.
Lee teaches or suggests the plurality of resistors being based on one or more gate structures and a plurality of gate vias, each resistor of the plurality of resistors being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias (see Fig. 6A-8B; para. 0007 - synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values, the synapses being programmed with at least one pattern based on the various fixed resistance values; para. 0010 - synapses may include resistor interconnections that include conductive paths having different lengths, the different lengths respectively providing the various fixed resistance values; para. 0055 - resistor interconnection Ir of each synapse may electrically connect the row contact Re and the column contact Cc of the synapse.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include the plurality of resistors being based on one or more gate structures and a plurality of gate vias, each resistor of the plurality of resistors being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Kaltiokallio further teaches or suggests formed on an integrated IC; wherein the plurality of switches is controlled by the digital output (see Fig. 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include formed on an integrated IC wherein the plurality of switches is controlled by the digital output for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Claim 2:
Lee further teaches or suggests each of the one or more gate structures and the plurality of gate vias comprises polysilicon or a metal (see para. 0017 - resistance regions may include one of an intrinsic semiconductor region, a low-concentration doped semiconductor region, a high-concentration doped semiconductor region, a metal silicide region, a metal compound region, a metal alloy region, and a metal region; para. 0018 - Each of the resistor interconnections may be a silicon wiring, a metal silicide interconnection, or a metal interconnection.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include each of the one or more gate structures and the plurality of gate vias comprises polysilicon or a metal for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Claim 3:
Lee further teaches or suggests wherein: each of the plurality of resistors has same resistance; and each of the plurality of resistors is formed by electrically connecting in series multiple portions of the one or more gate structures (see Fig. 6A-8B; para. 0007 - synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values, the synapses being programmed with at least one pattern based on the various fixed resistance values; para. 0010 - synapses may include resistor interconnections that include conductive paths having different lengths, the different lengths respectively providing the various fixed resistance values; para. 0055 - resistor interconnection Ir of each synapse may electrically connect the row contact Re and the column contact Cc of the synapse; para. 0058 – the synapses illustrated in FIG. 6A have substantially the same conductivity and include the resistor interconnections Irll to Ir19 having different lengths; para. 0063 - although resistor interconnections have the same shape, the resistor interconnections can have different fixed resistance values by selectively including a plurality of regions having different doping concentrations; para. 0064 - FIGS. 7A to 7C illustrate longitudinal cross-sectional views of synapses having fixed resistance values in accordance with embodiments; FIGS. 7D to 7F illustrate longitudinal cross-sectional views of synapses having various fixed resistance values in accordance with embodiments.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein: each of the plurality of resistors has same resistance; and each of the plurality of resistors is formed by electrically connecting in series multiple portions of the one or more gate structures for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Claim 4:
Lee further teaches or suggests wherein: the multiple portions of the one or more gate structures of one or the plurality of resistors have a same width and different length (see Fig. 6A-8B; para. 0007 - synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values, the synapses being programmed with at least one pattern based on the various fixed resistance values; para. 0010 - synapses may include resistor interconnections that include conductive paths having different lengths, the different lengths respectively providing the various fixed resistance values; para. 0055 - resistor interconnection Ir of each synapse may electrically connect the row contact Re and the column contact Cc of the synapse. the fixed resistance value of each synapse depends on the geometrical shape of the corresponding resistor interconnection Irll to Ir19, since the resistor interconnections Irll to Ir19 resemble strips having substantially the same width but different lengths; para. 0058 – the synapses illustrated in FIG. 6A have substantially the same conductivity and include the resistor interconnections Irll to Ir19 having different lengths;
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein: the multiple portions of the one or more gate structures of one or the plurality of resistors have a same width and different length for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Claim 5:
Kaltiokallio further teaches or suggests wherein: each of the switches is formed by at least one transistor electrically coupled between two corresponding gate vias of the plurality of gate vias; and each of the at least one transistor is electrically connected, in series of in parallel, to at least one of the plurality of resistors (see Fig. 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein: each of the switches is formed by at least one transistor electrically coupled between two corresponding gate vias of the plurality of gate vias; and each of the at least one transistor is electrically connected, in series of in parallel, to at least one of the plurality of resistors for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Claim 6:
Kaltiokallio further teaches or suggests wherein: the digital output has a plurality of bits; and each of the plurality of memory cells is configured for storing and outputting a respective bit of the digital output (see Fig. 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein: the digital output has a plurality of bits; and each of the plurality of memory cells is configured for storing and outputting a respective bit of the digital output for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Claim 7:
Kaltiokallio further teaches or suggests wherein: each of the at least one transistor is controlled by one of the plurality of bits of the digital output (see Fig. 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein: each of the at least one transistor is controlled by one of the plurality of bits of the digital output for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Claim 8:
Kaltiokallio further teaches or suggests wherein each of the plurality of memory cells is a static random-access memory (SRAM) formed by six transistors (see Fig. 3A; 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0077 - FIG. 3A is a schematic view of a basic computing element 300 implemented using six transistor (6T) SRAM. The basic computing element 300 follows the general configuration of that shown in FIG. 1; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein each of the plurality of memory cells is a static random-access memory (SRAM) formed by six transistors for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Claim 9:
Hatcher further teaches or suggests wherein: the conductance between the first node and the second node is set based on a weight value associated with the neural network (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 may be a hybrid analog-digital circuit; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.).
Claim 12:
Hatcher teaches or suggests an array of resistance control units, wherein: the resistance control units are connected between row lines and column lines of a neural network ... (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.);
at least one switch coupled to ... and configured for setting a conductance between two nodes based on selectively shorting out none, a subset, or all of the at least one resistor (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.); and
at least one memory cell configured for generating a digital output (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.).
Hatcher does not explicitly disclose the at least one resistor being based on one or more gate structures and a plurality of gate vias, each resistor of the at least one resistor being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias ...; ... wherein the plurality of switches is controlled by the digital output.
Lee teaches or suggests the at least one resistor being based on one or more gate structures and a plurality of gate vias, each resistor of the at least one resistor being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias (see Fig. 6A-8B; para. 0007 - synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values, the synapses being programmed with at least one pattern based on the various fixed resistance values; para. 0010 - synapses may include resistor interconnections that include conductive paths having different lengths, the different lengths respectively providing the various fixed resistance values; para. 0055 - resistor interconnection Ir of each synapse may electrically connect the row contact Re and the column contact Cc of the synapse.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include the at least one resistor being based on one or more gate structures and a plurality of gate vias, each resistor of the at least one resistor being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Kaltiokallio further teaches or suggests wherein the at least one switch is controlled by the digital output (see Fig. 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein the at least one switch is controlled by the digital output for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Claim 13:
Hatcher further teaches or suggests wherein: the conductance of each resistance control unit is set based on a corresponding weight value associated with the neural network (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.).
Claim 18:
Hatcher teaches or suggests a method comprising: ... included in a resistance control unit of a neural network, the resistance control unit comprising:
at least one resistor coupled between a first node and a second node of the neural network (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.);
at least one switch coupled to ... and the at least one memory cell (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.);
turning on or off the at least one switch based on the digital output for setting a conductance between the first node and the second node by selectively shorting out none, a subset, or all of the at least one resistor (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.);
applying an input voltage at the first node to enable a current flowing from the first node to the second node, based on a conductance between the first node and the second node set by the at least one switch (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.); and
providing an output voltage based on at least the current from the second node (see Fig. 1, 2 5A, and 5B; para. 0005 - Each of the weight cells has an electrical admittance corresponding to a weight; para. 0013 - The method and system described herein may be used in a variety of fields including but not limited to machine learning, artificial intelligence and neural networks; para. 0019 – hardware device 100 capable of performing an analog complex valued multiply-accumulate (MAC) operation/vector-matrix multiplication; para. 0021 - weight cells 120 may include passive electronic components, such as resistors and capacitors; para. 0024 - resulting current through output line 130 depends on the voltage through each input line and the admittance of the weight cells 120 connecting the input lines 110 with the output line. current may be converted into a voltage or otherwise manipulated by the post processing block; para. 0040 - FIGS. SA, SB and SC depict exemplary embodiments of a weight cell 120', a programmable resistance circuit 200A. weight cell 120' can thus be purely resistive, can be purely capacitive or both resistive and capacitive; para. 0041 - selectively opening or closing the switches 203, 205 and 207, the resistance of the programmable resistance circuit 200A can be set to one of eight evenly distributed values. However, other configurations having other resistance values are possible; para. 0043 - weight cell 120', the programmable resistance circuit 200A and/or the programmable capacitance circuit 210A, the hardware device 100, 100A, 100B, l00C and/or an analogous device may be implemented; para. 0045 - admittances for the weight cells 120 are programmed, via step 302. Thus, the desired resistances, capacitances, inductances and/or other electrical characteristics of the weight cells 120 are set. Step 302 may include opening or closing one or more of the switches 203, 205, 207, 213, 215 and/or 217 to provide the desired resistance and capacitance in each weight cell 120.).
Hatcher does not explicitly disclose reading a digital output from at least one memory cell; the at least one resistor being based on one or more gate structures and a plurality of gate vias, each resistor of the at least one resistor being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias.
Kaltiokallio further teaches or suggests reading a digital output from at least one memory cell (see Fig. 5A, 12A, and 12B; para. 0010 - storing means may comprise one of an SRAM; para. 0011 - routing means may comprise a semiconductor switch comprising first and second transistors, the value of the control bit stored in the storing means determining the state of the semiconductor switch; para. 0065 - basic computing element 100 may also comprise a memory means, such as a memory cell 104 for storing at least one bit of data representative of a control bit. The memory cell 104 may be set or reset via a memory write node 105; para. 0093 - involving metal layers 1200 stacked on top of one another with the resistor contacts 1202 occupying very small areas as they pass through one layer very large and dense neural networks. Where CMOS transistors are present, these can be provided where indicated by reference numeral 1204; para. 0096 - at least one high resistivity contact layer 1404, an optional MRAM memory layer 1406, and one or more layers comprising MOS transistors, e.g. CMOS transistors which may comprise gates, switches, amplifiers etc. and may include analogue domain components.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include reading a digital output from at least one memory cell for the purpose of efficiently implementing gates and switches within an integrated circuit, improving integrated circuit manufacture and nn performance, as taught by Kaltiokallio (0093 and 0096).
Lee further teaches or suggests the at least one resistor being based on one or more gate structures and a plurality of gate vias, each resistor of the at least one resistor being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias (see Fig. 6A-8B; para. 0007 - synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values, the synapses being programmed with at least one pattern based on the various fixed resistance values; para. 0010 - synapses may include resistor interconnections that include conductive paths having different lengths, the different lengths respectively providing the various fixed resistance values; para. 0055 - resistor interconnection Ir of each synapse may electrically connect the row contact Re and the column contact Cc of the synapse.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include the at least one resistor being based on one or more gate structures and a plurality of gate vias, each resistor of the at least one resistor being based on a gate structure segment of the one or more gate structures electrically coupled between two corresponding gate vias of the plurality of gate vias; ... coupled to the plurality of gate vias for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Claim 20:
Lee further teaches or suggests wherein: the neural network is formed on an integrated circuit (IC); each of the at least one transistor is formed by electrically connecting in series multiple portions of the one or more gate structures in the IC; and each of the one or more gate structures and the plurality of gate vias comprises a polysilicon or a metal (see para. 0017 - resistance regions may include one of an intrinsic semiconductor region, a low-concentration doped semiconductor region, a high-concentration doped semiconductor region, a metal silicide region, a metal compound region, a metal alloy region, and a metal region; para. 0018 - Each of the resistor interconnections may be a silicon wiring, a metal silicide interconnection, or a metal interconnection; Fig. 6A-8B; para. 0007 - synapses arranged in intersection regions between the row lines and the column lines. The synapses may include resistor interconnections having various fixed resistance values, the synapses being programmed with at least one pattern based on the various fixed resistance values; para. 0010 - synapses may include resistor interconnections that include conductive paths having different lengths, the different lengths respectively providing the various fixed resistance values; para. 0055 - resistor interconnection Ir of each synapse may electrically connect the row contact Re and the column contact Cc of the synapse; para. 0058 – the synapses illustrated in FIG. 6A have substantially the same conductivity and include the resistor interconnections Irll to Ir19 having different lengths; para. 0063 - although resistor interconnections have the same shape, the resistor interconnections can have different fixed resistance values by selectively including a plurality of regions having different doping concentrations; para. 0064 - FIGS. 7A to 7C illustrate longitudinal cross-sectional views of synapses having fixed resistance values in accordance with embodiments; FIGS. 7D to 7F illustrate longitudinal cross-sectional views of synapses having various fixed resistance values in accordance with embodiments.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Jung, to include wherein: the neural network is formed on an integrated circuit (IC); each of the at least one transistor is formed by electrically connecting in series multiple portions of the one or more gate structures in the IC; and each of the one or more gate structures and the plurality of gate vias comprises a polysilicon or a metal for the purpose of efficiently managing resistance and conductance in circuit region based on structures of particular materials and lengths, improving integrated circuit manufacture and synapse data retention, as taught by Lee (0010, 0091-0096).
Claim(s) 10, 11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatcher, in view of Lee, in view of Kaltiokallio, and further in view of Philip et al., US Publication 2021/0327502 (“Philip”).
Claim 10:
As indicated above, Hatcher, Lee, and Kaltiokallio teach or suggest a switch coupled between the first node and the plurality of resistors.
Philip more specifically teaches or suggests a read enable switch, wherein: the read enable switch is controlled by a read enable signal, and at least one of the first node or the second node is located on a signal line in the plurality of memory cells (see Fig. 2; para. 0018 – described RPU and resulting ANN architecture improve overall ANN performance and enable a broader range of practical ANN applications; para. 0021 - transistor 216 electrically coupled to each of the row write and row read lines 208, 210 and to each of the column write and column read lines 212; para. 0023 - performing a write or modify function to the RPU cell 206, the transistors 216 coupled to each of the row read line 210 and the column read line 214 are set to an "off' or "clamp" position (e.g., V=O) preventing current from passing through these read lines 210, 214. The transistors 216 coupled to the row write line 208 and/or the column write line 212 are set to an "open" state. The voltage sources are set, for example, to apply a bias application of voltage V>V SELECT to the row write line 208 and/or the column write line 212 to deliver a current through the write lines 208, 212 and perform a write function on the respective RPU cell 206. No current flows through the row read and column read lines 210, 214. Similarly, in conjunction with performing a read function, the transistors 216 associated with the row and/or column write lines 208, 212 are set to an "off' state to close off the circuit leading to the row and column write lines 208, 212. The transistors 216 coupled to the row read line 210 and/or the column read line 214 are set to an "on" state. A bias voltage, which in illustrative embodiments is 0.1-0.9 VsELEcr, is applied to the row read and column read lines 210, 214 to deliver a current and perform a read function on the respective RPU cells 206; para. 034 - performing a read function, a positive voltage is supplied from each voltage source "V" to the nMOS transistors 316 to open the nMOS transistors 316. A resulting current, at specified levels controlled through the logic or circuitry associated with the voltage sources "V," is conveyed along the row and column read lines 310, 314 to perform one or more read functions on the respective RPU cell 306.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include, wherein: the read enable switch is controlled by a read enable signal, and at least one of the first node or the second node is located on a signal line in the plurality of memory cells for the purpose of efficiently performing read/write operations in a memory array using switches and signals, improving neural network performance, as taught by Philip (0018).
Claim 11:
Philip more specifically teaches or suggests wherein: the read enable switch is set to an open state by the read enable signal during a write mode of the plurality of memory cells; and the read enable switch is set to a close state by the read enable signal during a computing mode of the neural network (see Fig. 2; para. 0018 – described RPU and resulting ANN architecture improve overall ANN performance and enable a broader range of practical ANN applications; para. 0021 - transistor 216 electrically coupled to each of the row write and row read lines 208, 210 and to each of the column write and column read lines 212; para. 0023 - performing a write or modify function to the RPU cell 206, the transistors 216 coupled to each of the row read line 210 and the column read line 214 are set to an "off' or "clamp" position (e.g., V=O) preventing current from passing through these read lines 210, 214. The transistors 216 coupled to the row write line 208 and/or the column write line 212 are set to an "open" state. The voltage sources are set, for example, to apply a bias application of voltage V>V SELECT to the row write line 208 and/or the column write line 212 to deliver a current through the write lines 208, 212 and perform a write function on the respective RPU cell 206. No current flows through the row read and column read lines 210, 214. Similarly, in conjunction with performing a read function, the transistors 216 associated with the row and/or column write lines 208, 212 are set to an "off' state to close off the circuit leading to the row and column write lines 208, 212. The transistors 216 coupled to the row read line 210 and/or the column read line 214 are set to an "on" state. A bias voltage, which in illustrative embodiments is 0.1-0.9 VsELEcr, is applied to the row read and column read lines 210, 214 to deliver a current and perform a read function on the respective RPU cells 206; para. 034 - performing a read function, a positive voltage is supplied from each voltage source "V" to the nMOS transistors 316 to open the nMOS transistors 316. A resulting current, at specified levels controlled through the logic or circuitry associated with the voltage sources "V," is conveyed along the row and column read lines 310, 314 to perform one or more read functions on the respective RPU cell 306.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include wherein: the read enable switch is set to an open state by the read enable signal during a write mode of the plurality of memory cells; and the read enable switch is set to a close state by the read enable signal during a computing mode of the neural network for the purpose of efficiently performing read/write operations in a memory array using switches and signals, improving neural network performance, as taught by Philip (0018).
Claim 19:
As indicated above, Hatcher, Lee, and Kaltiokallio teach or suggest a switch coupled between the first node and the at least one resistor.
Philip more specifically teaches or suggests turning on, based on a read enable signal during a computing mode of the neural network, a read enable switch, wherein; at least one of the first node or the second node is located on a signal line in the at least one memory cell, and the current is enabled based on turning on the read enable switch; and turning off, based on a read enable signal during a write mode of the at least one memory cell, the read enable switch to disable the current (see Fig. 2; para. 0018 – described RPU and resulting ANN architecture improve overall ANN performance and enable a broader range of practical ANN applications; para. 0021 - transistor 216 electrically coupled to each of the row write and row read lines 208, 210 and to each of the column write and column read lines 212; para. 0023 - performing a write or modify function to the RPU cell 206, the transistors 216 coupled to each of the row read line 210 and the column read line 214 are set to an "off' or "clamp" position (e.g., V=O) preventing current from passing through these read lines 210, 214. The transistors 216 coupled to the row write line 208 and/or the column write line 212 are set to an "open" state. The voltage sources are set, for example, to apply a bias application of voltage V>V SELECT to the row write line 208 and/or the column write line 212 to deliver a current through the write lines 208, 212 and perform a write function on the respective RPU cell 206. No current flows through the row read and column read lines 210, 214. Similarly, in conjunction with performing a read function, the transistors 216 associated with the row and/or column write lines 208, 212 are set to an "off' state to close off the circuit leading to the row and column write lines 208, 212. The transistors 216 coupled to the row read line 210 and/or the column read line 214 are set to an "on" state. A bias voltage, which in illustrative embodiments is 0.1-0.9 VsELEcr, is applied to the row read and column read lines 210, 214 to deliver a current and perform a read function on the respective RPU cells 206; para. 034 - performing a read function, a positive voltage is supplied from each voltage source "V" to the nMOS transistors 316 to open the nMOS transistors 316. A resulting current, at specified levels controlled through the logic or circuitry associated with the voltage sources "V," is conveyed along the row and column read lines 310, 314 to perform one or more read functions on the respective RPU cell 306.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include turning on, based on a read enable signal during a computing mode of the neural network, a read enable switch, wherein; at least one of the first node or the second node is located on a signal line in the at least one memory cell, and the current is enabled based on turning on the read enable switch; and turning off, based on a read enable signal during a write mode of the at least one memory cell, the read enable switch to disable the current for the purpose of efficiently performing read/write operations in a memory array using switches and signals, improving neural network performance, as taught by Philip (0018).
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatcher, in view of Lee, Kaltiokallio, in view of Fujinami, US Publication 2022/0236953 (“Fujinami”), and further in view of Shibata et al, US Publication (“2022/0138441 (“Shibata”).
Claim 14:
Fujinami further teaches or suggests wherein: each of the row lines is associated with an input of a neural network; the column lines include a plurality of pairs of column lines; each pair of column lines is associated with a pair of outputs of the neural network; the resistance control units include a plurality of pairs of resistance control units (see Fig. 9, 12, 16A, 16B, 19-22; para. 0078 - according to a mathematical model such as a neural network; para. 0430 - 16Aand FIG. 16B schematically show circuit diagrams of the positive synapse circuit 9a and the negative synapse circuit 9b; para. 0432 - first resistor 17a is connected between the positive input signal line 7a and the positive charge output line Sa, defines the positive weight value v,+, and outputs the positive weight charge to the positive charge output line Sa; para. 0434 - second resistor 17b is connected between the negative input signal line 7 b and the negative charge output line Sb, defines the negative weight value v,-, and outputs the negative weight charge to the negative charge output line.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include wherein: each of the row lines is associated with an input of a neural network; the column lines include a plurality of pairs of column lines; each pair of column lines is associated with a pair of outputs of the neural network; the resistance control units include a plurality of pairs of resistance control units for the purpose of efficiently carrying out neural network functionality using row and column resistor arrangements, improving network operation accuracy, as taught by Fujinami (0005, 0006, and 0430).
Shibata further teaches or suggests and each pair of resistance control units is between a corresponding row line and a corresponding pair of column lines (see Fig. 2-4; para. 0140 – inputs the input signal to a plurality of variable resistance elements (for example, l0Al-1 to l0Al-n) constituting a variable resistor array unit lOA; para. 0143 – the input signal is input to the variable resistor array unit lOA, the variable resistor array unit l0A outputs the result of the multiply and accumulate calculation, depending on the conductivity G of each of the variable resistance elements (for example, l0Al-1, l0Al-2.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include and each pair of resistance control units is between a corresponding row line and a corresponding pair of column lines for the purpose of efficiently carrying out neural network functionality using row and column resistor arrangements, improving network operation calculations and reducing error, as taught by Shibata (0222).
Claim 15:
Fujinami further teaches or suggests a pair of resistance control units including a first resistance control unit and a second resistance control unit, wherein: the first resistance control unit has a first conductance between the first row line and a first column line of the first pair, whether the first conductance is set based on weight associated with a first input at the first row line and a first output at the first column line, the second resistance unit has a second conductance between the row line and a second column line of the first pair, wherein the second conductance provides a negative weight associated with the first input at the row line and a second output at the second column line, and the first resistance control unit and the second resistance control unit together correspond to a signed weight, based on a summation of the positive weight and the negative weight, associated with the first input and an output pair of the first output and the second output (see Fig 9, 12, 16A, 16B, 19-22; para. 0078 - according to a mathematical model such as a neural network; para. 0430 - 16Aand FIG. 16B schematically show circuit diagrams of the positive synapse circuit 9a and the negative synapse circuit 9b; para. 0432 - first resistor 17a is connected between the positive input signal line 7a and the positive charge output line Sa, defines the positive weight value v,+, and outputs the positive weight charge to the positive charge output line Sa; para. 0434 - second resistor 17b is connected between the negative input signal line 7 b and the negative charge output line Sb, defines the negative weight value v,-, and outputs the negative weight charge to the negative charge output line; para. 0487; para. 0490 - multiply-accumulate result obtained by adding up the product values (v;*y;) in the negative weight column 18b is a sum of the product values of the negative weights provided in the positive weight pair and the negative weight pair; para. 0498 - sum total value W (common sum total value) of the weight values is, as shown below, equal to a value obtained by adding up a sum total of the positive paired weights w/ and a sum total of the negative paired weights.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include a pair of resistance control units including a first resistance control unit and a second resistance control unit, wherein: the first resistance control unit has a first conductance between the first row line and a first column line of the first pair, whether the first conductance is set based on weight associated with a first input at the first row line and a first output at the first column line, the second resistance unit has a second conductance between the row line and a second column line of the first pair, wherein the second conductance provides a negative weight associated with the first input at the row line and a second output at the second column line, and the first resistance control unit and the second resistance control unit together correspond to a signed weight, based on a summation of the positive weight and the negative weight, associated with the first input and an output pair of the first output and the second output for the purpose of efficiently carrying out neural network functionality using row and column resistor arrangements, improving network operation accuracy, as taught by Fujinami (0005, 0006, and 0430).
Shibata further teaches or suggests between the first row line and a first pair of column lines; and that for the second unit has a conductance between the first row line and a second column line of the first pair, wherein the second conductance is set based on a negative weight associated with the first input at the first row line and a second output at the second column line (see Fig. 2-4; para. 0140 – inputs the input signal to a plurality of variable resistance elements (for example, l0Al-1 to l0Al-n) constituting a variable resistor array unit lOA; para. 0143 – the input signal is input to the variable resistor array unit lOA, the variable resistor array unit l0A outputs the result of the multiply and accumulate calculation, depending on the conductivity G of each of the variable resistance elements (for example, l0Al-1, l0Al-2.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include between the first row line and a first pair of column lines; and that for the second unit has a conductance between the first row line and a second column line of the first pair, wherein the second conductance provides a weight associated with the first input at the first row line and a second output at the second column line for the purpose of efficiently carrying out neural network functionality using row and column resistor arrangements, improving network operation calculations and reducing error, as taught by Shibata (0222).
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatcher, in view of Lee, in view of Kaltiokallio, and further in view of Fujinami, US Publication 2022/0236953 (“Fujinami”).
Claim 16:
Fujinami further teaches or suggests wherein: the row lines include a plurality of row lines; each pair of row lines is associated with a pair of inputs of the neural network; the column lines include a plurality of pairs of column lines; each pair of column lines is associated with a pair of outputs of the neural network; the resistance control units include a plurality of pairs of resistance control units; and each pair of resistance control units is between a corresponding pair of row lines and a corresponding pair of column lines (see Fig 12, 16A, 16B, 19-22; para. 0078 - according to a mathematical model such as a neural network; para. 0430 - 16Aand FIG. 16B schematically show circuit diagrams of the positive synapse circuit 9a and the negative synapse circuit 9b; para. 0432 - first resistor 17a is connected between the positive input signal line 7a and the positive charge output line Sa, defines the positive weight value v,+, and outputs the positive weight charge to the positive charge output line Sa; para. 0434 - second resistor 17b is connected between the negative input signal line 7 b and the negative charge output line Sb, defines the negative weight value v,-, and outputs the negative weight charge to the negative charge output line.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include wherein: the row lines include a plurality of row lines; each pair of row lines is associated with a pair of inputs of the neural network; the column lines include a plurality of pairs of column lines; each pair of column lines is associated with a pair of outputs of the neural network; the resistance control units include a plurality of pairs of resistance control units; and each pair of resistance control units is between a corresponding pair of row lines and a corresponding pair of column lines for the purpose of efficiently carrying out neural network functionality using row and column resistor arrangements, improving network operation accuracy, as taught by Fujinami (0005, 0006, and 0430).
Claim 17:
Fujinami further teaches or suggests comprising: a pair of resistance control units including a first resistance control unit and a second resistance control unit between a first pair of row lines and a second pair or column lines, wherein: the first resistance control unit has a first conductance between a first row line of the first pair and a first column line of the second pair, wherein the first conductance is set based on a positive weight associated with a first input at the first row line and a first output at the first column line, the second resistance control unit has a second conductance between a second row line of the first pair and a second column line of the second pair, wherein the second conductance is set based on a negative weight associated with a second input at a second row line and a second output at the second column line, and the first resistance control unit and the second control unit together correspond to a signed weight, based on the summation of the positive and the negative weight, associated with (a) an input pair of the first input and the second input and (b) an output pair of the first output and the second output (see Fig 9, 12, 16A, 16B, 19-22; para. 0078 - according to a mathematical model such as a neural network; para. 0430 - 16Aand FIG. 16B schematically show circuit diagrams of the positive synapse circuit 9a and the negative synapse circuit 9b; para. 0432 - first resistor 17a is connected between the positive input signal line 7a and the positive charge output line Sa, defines the positive weight value v,+, and outputs the positive weight charge to the positive charge output line Sa; para. 0434 - second resistor 17b is connected between the negative input signal line 7 b and the negative charge output line Sb, defines the negative weight value v,-, and outputs the negative weight charge to the negative charge output line; para. 0487; para. 0490 - multiply-accumulate result obtained by adding up the product values (v;*y;) in the negative weight column 18b is a sum of the product values of the negative weights provided in the positive weight pair and the negative weight pair; para. 0498 - sum total value W (common sum total value) of the weight values is, as shown below, equal to a value obtained by adding up a sum total of the positive paired weights w/ and a sum total of the negative paired weights.).
Accordingly, it would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to modify the system and method, taught in Hatcher, to include comprising: a pair of resistance control units including a first resistance control unit and a second resistance control unit between a first pair of row lines and a second pair or column lines, wherein: the first resistance control unit has a first conductance between a first row line of the first pair and a first column line of the second pair, wherein the first conductance is set based on a positive weight associated with a first input at the first row line and a first output at the first column line, the second resistance control unit has a second conductance between a second row line of the first pair and a second column line of the second pair, wherein the second conductance is set based on a negative weight associated with a second input at a second row line and a second output at the second column line, and the first resistance control unit and the second control unit together correspond to a signed weight, based on the summation of the positive and the negative weight, associated with (a) an input pair of the first input and the second input and (b) an output pair of the first output and the second output for the purpose of efficiently carrying out neural network functionality using row and column resistor arrangements, improving network operation accuracy, as taught by Fujinami (0005, 0006, and 0430).
Response to Arguments
Applicant’s further arguments have been considered but are not persuasive because the arguments do not correspond to the rationales as used in the current rejection.
Conclusion
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/ANDREW T MCINTOSH/Primary Examiner, Art Unit 2144