DETAILED ACTION
This office action addresses Applicant’s response filed on 18 February 2026. Claims 1-8, 10-18, 20, and 21 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foreman (US 2017/0161415) in view of Fung (US 7,254,789) and/or Tsai (US 2014/0189634), Han (US 10,643,019), Mottaez (US 2012/0030642), Shrivastava (US 8,701,063), and Sircar (US 8,875,082) and/or Singh (US 2008/0005713).
Regarding claim 1, Foreman discloses a method for performing Static Timing Analysis (STA) in which STA scenarios are compressed using hybrid views that are hybrids of static and live views (¶¶16, 26, 28, 40), the method comprising:
identifying a plurality of operational scenarios, each operational scenario associated with a set of conditions and a particular path through an Integrated Circuit (IC) design (¶¶24, 27);
determining an operational status for at least one operational feature under the set of conditions associated with the plurality of operational scenarios (¶24);
classifying, via a classifier, operational scenarios into (1) live views that are of a type that is updated during a change stage in response to changes made to the IC design to fix timing violations and (2) static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations, timing of signal paths determined for scenarios of static views are captured when the change stage begins and are transferred to the live views (¶¶24, 27, 28);
determining margins associated with operational features within at least one scenario of the static views based on differences between operational features of the static views associated with a particular path through the IC design and the live views through the same particular path through the IC design and transferring information for correcting timing violations from the at least one scenario of the static views to the live view for each particular path through the IC design through application a margin associated with the particular path, the information including timing information of signals traveling through the particular path of the IC design, the live view to which the information was transferred forming a change scenario, therein timing violation and change data from scenarios associated with the particular path through the IC design common to both the static views and the live views are contained in the live views, therein allowing timing violations held in the static views to be fixed (¶¶24, 26-28, 40).
Foreman does not appear to explicitly disclose merging live views to form a merged live view. Fung (col. 15, lines 1-15) and/or Tsai (¶¶52, 53) disclose these limitations. The application of Fung and/or Tsai to Foreman suggests determining worst case corners (as taught by Foreman), merging the worst case corners (as taught by Fung and/or Tsai), and then providing the merged corner for optimization with an applied margin (as taught by Foreman). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Foreman and Fung and/or Tsai, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of consolidating worst case information for optimization. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Foreman discloses determining worst case corners for further optimization and timing analysis. Fung and Tsai each teach that worst case corners should be merged. The teachings of Fung and Tsai are each directly applicable to Foreman in the same way, so that Foreman would similarly merge worst case corners for optimization so that worst case information is consolidated into one corner.
Persons having ordinary skill in the art would understand Foreman’s corners to correspond to views, as evidenced by Han (col. 3, lines 25-26), and would further understand Foreman’s selected worst corners to correspond to the claimed live views, and unselected corners to correspond to the claimed static views, as also evidence by Han (col. 2, lines 28-33). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Foreman, Fung and/or Tsai, and Han, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of reducing runtime of timing optimization. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Foreman teaches determining a subset of corners to perform timing optimization. Persons having ordinary skill in the art would understand Foreman’s corners to correspond to views, and the selected subset of corners to correspond to live views and the other corners to correspond to static views, as taught by Han. The teachings of Han are directly applicable to Foreman in the same way, so that Foreman would determine a subset of live views for timing optimization to reduce runtime.
If Foreman is found to be unclear regarding classifying, via a classifier, operational scenarios into live views updated during a change stage in response to changes and static views that are not, the static views being captured before fixes are implemented to remove the timing violations, Mottaez also discloses that live views are of a type that is updated during a change stage in response to changes made to a design to fix timing violations and static views are of a type that is captured without updating the static view in response to changes made to the design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (¶¶77-80). The combination of Foreman and Mottaez suggests dividing operational scenarios into live and static views, and only further analyzing the live scenarios (as taught by Foreman), so that when a design is modified during optimization, circuit information is updated only in the live scenarios (as taught by Mottaez).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Foreman, Fung and/or Tsai, Han, and Mottaez, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to reduce the amount of information that is updated when a design is modified. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Foreman discloses classifying scenarios into live and static views, such that only live scenarios are analyzed during design optimizations. Mottaez provides explicit disclosure that when a design is modified during optimization, information is updated only for some scenarios. The teachings of Mottaez are directly applicable to Foreman in the same way, so that Foreman would similarly update the live scenarios when a design is modified during optimization.
If Foreman is found to be unclear regarding transferring information for correcting timing violations from the at least one scenario of the static views to the live view for each particular path through the IC design through application a margin associated with the particular path, the information including timing information of signals traveling through the particular path of the IC design, the live view to which the information was transferred forming a change scenario, therein timing violation and change data from scenarios associated with the particular path through the IC design common to both the static views and the live views are contained in the live views, therein allowing timing violations held in the static views to be fixed, Shrivastava discloses the same (Abstract; col. 3, line 64 to col. 4, line 7; col. 6, lines 30-42).
Shrivastava also discloses identifying a plurality of operational scenarios, each operational scenario associated with a set of conditions and a particular path through an Integrated Circuit (IC) design (col. 2, lines 8-11; col. 3, lines 29-34);
determining an operational status for at least one operational feature under the set of conditions associated with the plurality of operational scenarios (col. 3, lines 35-42);
classifying, via a classifier, operational scenarios into (1) live views that are of a type that is updated during a change stage in response to changes made to the IC design to fix timing violations and (2) static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations, timing of signal paths determined for scenarios of static views are captured when the change stage begins and are transferred to the live views (col. 3, line 64 to col. 4, line 7; col. 4, lines 23-27; col. 6, lines 35-40; col. 7, lines 36-50); and
determining margins associated with operational features within at least one scenario of the static views based on differences between operational features of the static views associated with a particular path through the IC design and the live views through the same particular path through the IC design (col. 6, lines 30-42).
Specifically, Foreman already discloses applying a margin to the worst corner(s) to capture other corners around the worst corner, based on the slack differences between the corners, and timing optimization is performed using the worst corner(s) having the applied margin (¶¶26, 28, 40). Thus, Foreman clearly discloses “transferring information from the at least one scenario of a static view to the live view through the application of one of the margins, therein allowing timing violations held in the static views to be fixed”, since Foreman’s worst corner(s) (live views) used for timing optimization have a margin applied to cover other corners (static views) based on their slack differences. Shrivastava provides even more explicit disclosure of these features, in which dominant scenarios are selected for use in subsequent analysis/optimization, skipping the remaining scenarios, and the dominant scenarios have a margin applied to cover non-dominant scenarios, thus allowing optimization to be performed only using the dominant scenarios but still covering the timing violation and ECO data of the non-dominant scenarios.
Furthermore, Fig. 5 of Applicant’s drawings illustrates the “transferring information …” limitations, where the merged live view has a U2/D slack of -1, which doesn’t account for the U2/D slack of -4 in the static view, so a margin of -3 is applied to U2/D of the merged live view, so that the merged live view now covers the static view. Both Foreman and Shrivastava do this; applying the margin in both cases causes the selected worst/dominant view to cover other views, so that analyzing the selected worst/dominant view with the applied margin accounts for data of the unselected views (Foreman ¶¶24, 26, 40; Shrivastava col. 6, lines 30-42).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Foreman, Fung and/or Tsai, Han, Mottaez, and Shrivastava, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of covering non-selected views during timing optimization using a reduced number of views. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Foreman discloses applying margins to selected worst corners to cover other corners, based on slack differences between the corners. Persons having ordinary skill in the art would understand that the margin allows timing optimization using the worst corners to also account for other (non-selected) corners which are not used in timing optimization, as more explicitly taught by Shrivastava. The teachings of Shrivastava are directly applicable to Foreman in the same way, so that Foreman would similarly apply a margin to views selected for timing optimization so that non-selected views are still covered by the optimization.
If Foreman is found to be unclear regarding the change stage being ECO and correspondingly a scenario being an ECO scenario, and data being ECO data, Sircar (Fig. 3; col. 13, lines 24-35) and/or Singh (¶12) disclose the same. As would be recognized by persons having ordinary skill in the art, Sircar and/or Singh each disclose that ECO data includes the timing information such as slack, slew, etc. disclosed by Foreman, Fung, Tsai, Han, Mottaez, and Shrivastava. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Foreman, Fung and/or Tsai, Han, Mottaez, Shrivastava, and Sircar and/or Singh, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of storing timing information for timing optimization during the conventional ECO design stage. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Foreman, Fung, Tsai, Han, Mottaez, and Shrivastava all teach timing information, such as slack, slew, etc. that is used for timing optimization and correction. Sircar and Singh each teach that such timing information is ECO data stored in an ECO database for timing optimization and correction during the conventional ECO design stage where timing correction is performed. The teachings of Sircar and/or Singh are directly applicable to Foreman, Fung, Tsai, Han, Mottaez, and Shrivastava so that their timing information would similarly be ECO data stored in an ECO database to allow access for timing optimization and correction during the conventional ECO stage.
Regarding claim 2, Foreman discloses that the at least one of the set of conditions comprises operational conditions (¶24).
Regarding claim 3, Foreman discloses that the operational conditions comprise at least temperature conditions (¶24).
Regarding claim 4, Foreman discloses that the at least one of the operational conditions comprises process conditions (¶24).
Regarding claim 5, Foreman discloses that the process conditions comprise process variations (¶29).
Regarding claim 6, Foreman discloses that the at least one operational feature comprises timing of signals over the paths of the IC design (¶¶24, 27).
Regarding claim 7, Foreman discloses that the timing of signals over the paths of an integrated circuit comprises timing slack (¶¶24, 27).
Regarding claim 8, Foreman discloses that the classifying of the operational scenarios into the live views and the static views comprises determining which scenarios are updated on the fly and which are not updated as fixes are made (¶28).
If Foreman is found to be unclear regarding live views updated in response to changes and static views that are not, Mottaez also discloses that live views are updated in response to changes made to a design to fix timing violations and static views are captured without updating the static view in response to changes made to the design to fix timing violations (¶80). The combination of Foreman and Mottaez suggests dividing operational scenarios into live and static views, and only further analyzing the live scenarios (as taught by Foreman), so that when a design is modified during optimization, circuit information is updated only in the live scenarios (as taught by Mottaez). Motivation to combine remains consistent with claim 1.
Regarding claim 10, Foreman does not appear to explicitly disclose that a set of live view scenarios are merged to form merged live views by determining worst cases for each operational feature within the set of live views; Tsai discloses these features (¶52). Motivation to combine remains consistent with claim 1.
Regarding claim 11, Foreman discloses a system for performing Static Timing Analysis in which STA scenarios are compressed (¶16) comprising a memory storing instructions and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to (¶¶53, 58):
identify a plurality of operational scenarios, each associated with a unique set of conditions and a particular path through an Integrated Circuit (IC) design (¶¶24, 27);
determine operational status for a plurality of operational features under the unique set of conditions associated with the plurality of operational scenarios (¶24);
divide operational scenarios, based on one or more defined criteria, into live views that are of a type that is updated in response to changes made an IC design to fix timing violations and static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (¶¶24, 27, 28);
determine margins associated with operational features within at least one scenario of the static views based on differences between operation features of the static views and the live views; and transfer information from the at least one scenario of the static views to the merged live view through application of the margin on a path by path basis, the information including timing information of signals traveling through the particular paths of the IC design that are common to the live views and the static views; therein timing violation and ECO data from scenarios associated with the particular path of the static views and the live views are contained in the live views, therein allowing the timing violations in the scenarios held in the static views to be fixed (¶¶24, 26-28, 40).
Foreman does not appear to explicitly disclose merging live views to form a merged live view. Fung (col. 15, lines 1-15) and/or Tsai (¶¶52, 53) disclose these limitations. The application of Fung and/or Tsai to Foreman suggests determining worst case corners (as taught by Foreman), merging the worst case corners (as taught by Fung and/or Tsai), and then providing the merged corner for optimization with an applied margin (as taught by Foreman). Motivation to combine remains consistent with claim 1.
Persons having ordinary skill in the art would understand Foreman’s corners to correspond to views, as evidenced by Han (col. 3, lines 25-26), and would further understand Foreman’s selected worst corners to correspond to the claimed live views, and unselected corners to correspond to the claimed static views, as also evidence by Han (col. 2, lines 28-33). Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear regarding dividing operational scenarios, based on one or more defined criteria, into live views that are of a type that is updated in response to changes and static views that are not, the static views being captured before fixes are implemented to remove the timing violations, Mottaez also discloses dividing operational scenarios, based on one or more defined criteria, into live views that are of a type that is updated in response to changes made to an IC design to fix timing violations and static views that are of a type that is captured without updating the static view in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (¶¶77-80). The combination of Foreman and Mottaez suggests dividing operational scenarios into live and static views, and only further analyzing the live scenarios (as taught by Foreman), so that when a design is modified during optimization, circuit information is updated only in the live scenarios (as taught by Mottaez). Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear regarding transferring information from the at least one scenario of the static views to the merged live view through application of the margin on a path by path basis, the information including timing information of signals traveling through the particular paths of the IC design that are common to the live views and the static views; therein timing violation and ECO data from scenarios associated with the particular path of the static views and the live views are contained in the live views, therein allowing the timing violations in the scenarios held in the static views to be fixed, Shrivastava discloses the same (Abstract; col. 3, line 64 to col. 4, line 7; col. 6, lines 30-42).
Shrivastava also discloses identifying a plurality of operational scenarios, each associated with a unique set of conditions and a particular path through an Integrated Circuit (IC) design (col. 2, lines 8-11; col. 3, lines 29-34);
determine operational status for a plurality of operational features under the unique set of conditions associated with the plurality of operational scenarios (col. 3, lines 35-42);
divide operational scenarios, based on one or more defined criteria, into live views that are of a type that is updated in response to changes made an IC design to fix timing violations and static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (col. 3, line 64 to col. 4, line 7; col. 4, lines 23-27; col. 6, lines 35-40; col. 7, lines 36-50); and
determine margins associated with operational features within at least one scenario of the static views based on differences between operation features of the static views and the live views (col. 6, lines 30-42).
Specifically, Foreman already discloses applying a margin to the worst corner(s) to capture other corners around the worst corner, based on the slack differences between the corners, and timing optimization is performed using the worst corner(s) having the applied margin (¶¶26, 28, 40). Thus, Foreman clearly discloses “transferring information from the at least one scenario of a static view to the live view through the application of one of the margins, therein allowing timing violations held in the static views to be fixed”, since Foreman’s worst corner(s) (live views) used for timing optimization have a margin applied to cover other corners (static views) based on their slack differences. Shrivastava provides even more explicit disclosure of such a feature, in which a dominant scenario has a margin applied to cover non-dominant scenarios, thus allowing optimization to be performed only using the dominant scenarios but still covering the timing violation and ECO data of the non-dominant scenario.
Furthermore, Fig. 5 of Applicant’s drawings illustrates these limitations, where the merged live view has a U2/D slack of -1, which doesn’t account for the U2/D slack of -4 in the static view, so a margin of -3 is applied to U2/D of the merged live view, so that the merged live view now covers the static view. Both Foreman and Shrivastava do this; applying the margin in both cases causes the selected worst/dominant view to cover other views, so that analyzing the selected worst/dominant view with the applied margin accounts for data of the unselected views (Foreman ¶¶24, 26, 40; Shrivastava col. 6, lines 30-42). Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear regarding data being ECO data, Sircar (Fig. 3; col. 13, lines 24-35) and/or Singh (¶12) disclose the same. As would be recognized by persons having ordinary skill in the art, Sircar and/or Singh each disclose that ECO data includes the timing information such as slack, slew, etc. disclosed by Foreman, Fung, Tsai, Han, Mottaez, and Shrivastava. Motivation to combine remains consistent with claim 1.
Claim 12-18 and 20 are directed to systems for performing the methods of claims 2-8 and 10, and are rejected under the same reasoning.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Foreman in view of Fung and/or Tsai, Han, Mottaez, Shrivastava, Sircar and/or Singh, and Oh (US 2016/0085901).
Regarding claim 21, Foreman discloses a non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to (¶53):
identify a plurality of operational scenarios with at least one operational condition (¶24);
determine an operational status for a plurality of operational features under the conditions associated with the plurality of operational scenarios (¶24);
divide, based on one or more defined criteria, operational scenarios into live views that are of a type that is updated in response to changes made to an Integrated Circuit (IC) design to fix timing violations and static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (¶¶24, 27, 28);
determine margins associated with operational features within at least one scenario of the static views based on differences between the operational features of the static views and the live views and transfer timing information, associated with the margins, from the static views to a merged live view so that the timing violations of the static views are contained in live views (¶¶24, 26-28, 40); and
provide information from which a circuit is to be fabricated based on parameters that have been adjusted to fix violations based on the information transferred from the at least one scenario of the static view (¶2), the timing information including timing information timing of signals traveling through the plurality of paths of the IC design that are part of the static view, therein timing violation and ECO data from scenarios associated with the static views and the live views are contained in the live views, therein allowing timing violations held in the static views to be fixed (¶¶24, 26-28, 40), and
change the IC design to fix the timing violations, based on the view to which the margins were applied, causing the timing violations in the live and the static views to be fixed while preventing any ping pong effect between the live and the static views (¶¶15, 16, 28, 40).
Foreman does not appear to explicitly disclose merging live views to form a merged live view. Fung (col. 15, lines 1-15) and/or Tsai (¶¶52, 53) disclose these limitations. The application of Fung and/or Tsai to Foreman suggests determining worst case corners (as taught by Foreman), merging the worst case corners (as taught by Fung and/or Tsai), and then providing the merged corner for optimization with an applied margin (as taught by Foreman). Motivation to combine remains consistent with claim 1.
Persons having ordinary skill in the art would understand Foreman’s corners to correspond to views, as evidenced by Han (col. 3, lines 25-26), and would further understand Foreman’s selected worst corners to correspond to the claimed live views, and unselected corners to correspond to the claimed static views, as also evidence by Han (col. 2, lines 28-33). Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear regarding dividing, based on one or more defined criteria, operational scenarios into live views that are of a type that is updated in response to changes and static views that are not, the static views being captured before fixes are implemented to remove the timing violations, Mottaez also discloses divide, based on one or more defined criteria, operational scenarios into live views that are of a type that is updated in response to changes made to an Integrated Circuit (IC) design to fix timing violations and static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (¶¶77-80), and that timing violations in the live and static views are fixed while preventing any ping pong effect between the live and the static views (¶40). The combination of Foreman and Mottaez suggests dividing operational scenarios into live and static views, and only further analyzing the live scenarios (as taught by Foreman), so that when a design is modified during optimization, circuit information is updated only in the live scenarios (as taught by Mottaez). Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear information transferred from the at least one scenario of the static view, the timing information including timing information timing of signals traveling through the plurality of paths of the IC design that are part of the static view, therein timing violation and ECO data from scenarios associated with the static views and the live views are contained in the live views, therein allowing timing violations held in the static views to be fixed, Shrivastava discloses the same (Abstract; col. 3, line 64 to col. 4, line 7; col. 6, lines 30-42).
Shrivastava also discloses identifying a plurality of operational scenarios with at least one operational condition (col. 2, lines 8-11; col. 3, lines 29-34);
determining an operational status for a plurality of operational features under the conditions associated with the plurality of operational scenarios (col. 3, lines 35-42);
dividing, based on one or more defined criteria, operational scenarios into live views that are of a type that is updated in response to changes made to an Integrated Circuit (IC) design to fix timing violations and static views that are of a type that is captured without updating the static views in response to changes made to the IC design to fix timing violations, the static views being captured before fixes are implemented to remove the timing violations (col. 3, line 64 to col. 4, line 7; col. 4, lines 23-27; col. 6, lines 35-40; col. 7, lines 36-50); and
determine margins associated with operational features within at least one scenario of the static views based on differences between the operational features of the static views and the live views and transfer timing information, associated with the margins, from the static views to a merged live view so that the timing violations of the static views are contained in live views (col. 6, lines 30-42).
Specifically, Foreman already discloses applying a margin to the worst corner(s) to capture other corners around the worst corner, based on the slack differences between the corners, and timing optimization is performed using the worst corner(s) having the applied margin (¶¶26, 28). Thus, Foreman clearly discloses “transferring information from the at least one scenario of a static view to the live view through the application of one of the margins, therein allowing timing violations held in the static views to be fixed”, since Foreman’s worst corner(s) (live views) used for timing optimization have a margin applied to cover other corners (static views) based on their slack differences. Shrivastava provides even more explicit disclosure of such a feature, in which a dominant scenario has a margin applied to cover non-dominant scenarios, thus allowing optimization to be performed only using the dominant scenarios but still covering the timing violation and ECO data of the non-dominant scenario.
Furthermore, Fig. 5 of Applicant’s drawings illustrates these limitations, where the merged live view has a U2/D slack of -1, which doesn’t account for the U2/D slack of -4 in the static view, so a margin of -3 is applied to U2/D of the merged live view, so that the merged live view now covers the static view. Both Foreman and Shrivastava do this; applying the margin in both cases causes the selected worst/dominant view to cover other views, so that analyzing the selected worst/dominant view with the applied margin accounts for data of the unselected views (Foreman ¶¶24, 26, 40; Shrivastava col. 6, lines 30-42). Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear regarding data being ECO data, Sircar (Fig. 3; col. 13, lines 24-35) and/or Singh (¶12) disclose the same. As would be recognized by persons having ordinary skill in the art, Sircar and/or Singh each disclose that ECO data includes the timing information such as slack, slew, etc. disclosed by Foreman, Fung, Tsai, Han, Mottaez, and Shrivastava. Motivation to combine remains consistent with claim 1.
If Foreman is found to be unclear regarding fabricating a circuit based on parameters that have been adjusted to fix violations, Oh discloses the same (Fig. 2A; ¶53). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Foreman, Fung and/or Tsai, Han, Mottaez, Shrivastava, Sircar and/or Singh, and Oh, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of fabricating designs without timing violations. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Foreman discloses a circuit fabrication process including timing analysis to identify violations. Oh discloses fixing violations by adjusting design parameters and fabricating the design. The teachings of Oh are directly applicable to Foreman in the same way, so that Foreman’s fabrication process would similarly fix violations so that that fabricated circuit is functional.
Response to Arguments
Applicant's arguments filed 18 February 2026 have been fully considered but they are not persuasive.
Applicant asserts that Foreman, Han, Tsai, Fung, Mottaez, and Shrivastava discloses ECO, and Sircar does not disclose live and static views. Remarks 9. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant further asserts that “claim 1 recites more than just a timing ECO database” and requires the live views to contain the ECO data, whereas “there is no disclosure of the ECO module being contained in the live views”. Remarks 9. The examiner disagrees. Foreman, Han, Tsai, Fung, Mottaez, and Shrivastava disclose timing data in the live view; the gap is only that they do not appear to explicitly use the term ‘ECO’. ECO is a timing optimization/correction design stage, and the cited references teach the live views containing timing information for timing optimization/correction. Sircar is relied upon merely to provide evidence of the ECO timing optimization/correction design phase. The application of Sircar thus teaches performing the timing optimization/correction using live views, as taught by the other cited references, in the ECO design stage. For this reason, even assuming, arguendo, that Applicant’s asserted incompatibility between location-aware timing corrections and Foreman’s worst timing corner had merit, it would not be relevant to the proposed combination, which performs Foreman’s process, using Foreman’s corners and timing information, during the ECO stage. Nevertheless, solely in the interest of advancing prosecution, the Singh reference has also been cited to teach these features.
Applicant asserts that “Foreman and Han are silent about how and when the other corners are updated. Silence is not a disclosure of live and static views.” Remarks 12. The examiner disagrees. Foreman explicitly discloses selecting worst corners, and using those worst corners for timing correction (¶28), while Han explicitly discloses pruning the number of views to a small set of dominant views in order to increase computing device efficiency (col. 2, lines 28-36). Clearly, the worst corners/dominant views are the live views which are updated, and the other corners/views are the static views which are not updated. Furthermore, Foreman explicitly discloses applying a margin to the worst corners in order to cover other corners, so at a minimum, those other covered corners correspond to static views. And even assuming, arguendo, that Foreman and Han failed to teach what is and is not updated, Shrivastava (col. 6, lines 35-40) and Mottaez (¶80) do.
Applicant continues to distinguish ‘corners’ from ‘views’; the examiner continues to disagree. Remarks 13. Corners, scenarios, and views are all sets of conditions of process and operational variables that timing analysis is performed under, as made clear by at least Foreman, Han, Mottaez, Shrivastava, and the Specification. It is also not clear why “the statistical uncertainties inherent in large collections of small electrical components” suggests that there would not be an expectation of success when ‘interchanging’ corners and views, as asserted by Applicant. Id. The process conditions and operational variables for the corresponding corner or view are the same; each set of conditions/variables defines a corner or view, as clearly disclosed in Han. Applicant’s assertion that Mottaez and Shrivastava apply to corners and not views is also inaccurate; both explicitly use scenarios. Applicant is invited to contact the examiner to discuss ‘corners’ vs ‘views’, which may be more effective in advancing prosecution regarding this point than further written argument.
Applicant asserts that “Foreman just teaches to perform further analysis on the worst comers and does not teach the use of static and live views” and Han does not teach live and static views because “Presumably, all views are altered, even though just the dominant views are given greater analysis (otherwise, in the prior art thinking, one cannot leave the nondominant views unchanged, because they include design violations)”. Remarks 13. The examiner disagrees. Foreman and Han select worst/dominant corners/views for timing correction explicitly in order to reduce the number of corners/views that need to be analyzed, which contradicts Applicant’s presumption. Furthermore, Foreman explicitly discloses applying a margin to the worst corners in order to cover other corners, so at a minimum, those other covered corners correspond to static views. And even assuming, arguendo, that Foreman and Han failed to teach what is and is not updated, Shrivastava (col. 6, lines 35-40) and Mottaez (¶80) do.
It is not clear what Applicant is arguing regarding Foreman and subsets. Remarks 14. If Applicant is suggesting that there are no corners aside from the worst corners, this is contradicted by Foreman’s selection of worst corners and the application of margin to the worst corners to cover other corners. Applicant also asserts that Foreman does not specify what is updated and what is not updated; as discussed above, this is not a reasonable reading of Foreman, which specifically selects worst corners for timing optimization.
Applicant asserts that the combination of references does not teach that “information is transferred from the at least one scenario of a static view to the merged live view through application of one of the margins. The information that is transferred includes information about the timing of signals traveling through each of the plurality of paths of the IC design”. Remarks 15. The examiner disagrees. This limitation is illustrated in Fig. 5, where ‘transferring information’ is applying the -3 margin to U2/D so that the live view’s -1 slack reflects the worse -4 slack in Scenario C. As discussed in the rejection, this is exactly what Foreman (¶26) and Shrivastava (col. 6, lines 32-34) do: modifying the dominant scenario to also cover other scenarios by determining a margin based on the slack difference between scenarios, to reduce the slack of the dominant scenario to the slack of the other scenario being covered.
Applicant asserts that combining Foreman and Tsai switches between paths and libraries and “changes the manner in which the invention operates.” Remarks 16. The examiner disagrees. Tsai teaches forming a synthetic corner using the worst delays across multiple corners, which is applicable to both cells and paths; persons having ordinary skill in the art, reading Foreman and Tsai, would clearly understand the straightforward application of Tsai to Foreman to form a synthetic corner by combining the worst paths from Foreman’s corners. “When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one.” KSR International Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396.
Applicant asserts that Foreman teaches away from MCMM while Tsai relies on MCMM. Remarks 17. The examiner disagrees. Foreman does not “teach away” from MCMM broadly, but merely states that MCMM used for timing signoff risks lower accuracy than statistical static timing analysis (SSTA). Similarly, Applicant asserts that Tsai teaches that systems like Foreman “lead to high rejection rates, convergence problems and long runtimes and, therefore, should not be used”. Remarks 18. However, this is not a teaching away from Foreman, because Foreman applies a margin to cover other corners. Applicant also asserts that Tsai suggests there is no need for margins. Id. Tsai does not address margins, and Tsai’s synthetic corner is not over all corners, so margin would still be useful.
Applicant asserts that Fung fails to teach merging live and static views. Remarks 20. However, Fung was not relied upon to teach merging live and static views.
Applicant asserts that it would not make sense to apply margins, as taught by Shrivastava, to Foreman or Tsai, because Foreman and Tsai already include the maximum delay in the worst/synthetic corner. Remarks 20. Foreman itself already teaches applying a margin to cover other corners, and Tsai’s synthetic corner is not over all corners, so there is clearly no incompatibility.
Applicant asserts that Mottaez teaches against Tsai and the claimed merged live views. Remarks 21. This is a misreading of Mottaez; the cited portion of Mottaez is describing the situation that Foreman, Tsai, and Shrivastava also seek to improve: “performing static timing analysis for all scenarios and update timing information for all scenarios when an optimization transformation is applied to a gate”. The references are consistent in addressing the need to perform timing updates across all scenarios (by selecting dominant/worst scenarios for timing updates), rather than teaching away. Applicant also asserts that Mottaez does not teach transferring information from static to live views; however, Mottaez was not relied upon to teach those limitations.
Conclusion
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23 September 2026
/ARIC LIN/ Examiner, Art Unit 2851
