DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed February 19, 2026 with respect to claims 12 and 14-17 have been fully considered but they are not persuasive.
Applicant’s argument that Elsherbini does not disclose the recited first die and second die is not persuasive. Elsherbini discloses a host chip 102 and a chiplet 101 that are electrically and mechanically coupled, with each having its own metallization structure and conductive traces. See, e.g., Elsherbini paras. [0036]-[0055], [0086]-[0105], [0108]-[0115]. Although Elsherbini refers to the embedded structure as a “chiplet,” the disclosure nevertheless teaches a composite integrated circuit structure including distinct circuit-bearing portions with separate metallization stacks and conductive pathways therebetween. The claim does not require a particular nomenclature for the two dies, only that the structure include first and second dies coupled through interconnects and conductive traces as recited.
Applicant further argues that the rejection improperly maps “upper” and “lower” portions of chiplet 101 to the claimed first and second dies. To the extent the Office Action description referred to different portions of the integrated structure, the rejection is directed to the separate host-chip and chiplet regions disclosed by Elsherbini, not to a physical severing of a single die into two unrelated parts. Elsherbini expressly discloses a host chip BEOL metallization stack 103 and a chiplet metallization stack 114, with interconnection through hybrid bonding/direct bond interconnects and vias. These teachings are sufficient to meet the claimed first and second dies.
Applicant’s assertion that the cited interconnects 118/M5 do not couple the claimed dies is also not persuasive. Elsherbini discloses DTD interconnects 118 between the host chip and the chiplet, and further discloses conductive pathways through region-specific portions of those interconnects proximate the periphery of a blocked region. See paras. [0037], [0039]-[0041], [0054]-[0055]. The rejection relied on the disclosed conductive pathway as a whole, not on any single numeral in isolation. The fact that some vias or pads are located in the host BEOL stack does not negate the disclosure of a conductive pathway through interconnect portions proximate to the periphery of the region.
Applicant’s contention that Elsherbini’s interlevel vias 126 are part of the host BEOL stack rather than the chiplet metallization stack does not overcome the rejection. The claim only requires that the second conductive trace be in the second metallization stack. Elsherbini discloses a separate chiplet metallization stack 114 and a host BEOL stack 103. The rejection reads the claimed second metallization stack on the chiplet metallization stack 114, with the conductive coupling extending to the host side through the disclosed bonding/interconnect structures. Accordingly, the anticipation rejection of claim 12 is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elsherbini et al. (US 2021/0098407).
As for claim 12, Elsherbini et al. disclose in Fig. 1A and the related text microelectronic assembly, comprising:
a first die (host chip 102 / lower structure of Fig. 1A) having a three-dimensional region (e.g., a blocked region or region underlying chiplet 101) extending through a first metallization stack (BEOL metallization stack 103); and
a second die (chiplet 101) electrically and mechanically coupled to the first die with a plurality of interconnects (e.g., DTD interconnects / hybrid bond interconnects 118), wherein:
the second die comprises a second metallization stack (chiplet metallization stack 114),
a first conductive trace in the first metallization stack is electrically coupled to a second conductive trace in the second metallization stack by a conductive pathway through a portion of the plurality of interconnects (e.g., conductive pathway 146 through DTD interconnects 118 / adjacent vias as shown in Fig. 1B), and
the portion of the plurality of interconnects is located proximate to a periphery of the three-dimensional region (e.g., periphery 202 of blockage region 114 / region underlying chiplet 101).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini et al. as applied to claim 12 above, and further in view of Yu et al. (US 2020/0381397).
As for claim 14, Elsherbini et al. disclose substantially the microelectronic assembly of claim 12, but does not disclose the insulating material surrounding the second die, wherein respective surfaces of the insulating material and the second die opposite to the first die comprise conductive bond pads, and conductive TDVs through the insulating material configured to provide electrical coupling between the first die and at least some of the bond pads as required by the claim.
Yu et al. teach an insulating material 250 surrounding the second die 210′, wherein respective upper surfaces of the insulating material 250 and the second die 210′ opposite to the first die 110′ comprise conductive bond pads 258, and conductive TDVs 252 through the insulating material configured to provide electrical coupling between the first die 110′ and at least some of the bond pads. See Yu et al., e.g., Figs. 1-18 and the related text, including Fig. 13.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Elsherbini et al. to include the insulating material and TDV arrangement taught by Yu et al. in order to improve interconnection reliability and packaging integration.
As for claim 15, Elsherbini et al. disclose the microelectronic assembly of claim 12 and further disclose a third conductive trace in the first metallization stack and a fourth conductive trace in the second metallization stack, wherein the third conductive trace is orthogonal to the first conductive trace, the fourth conductive trace is orthogonal to the second conductive trace, and the third conductive trace is electrically coupled to the fourth conductive trace by a second conductive pathway through another portion of interconnects located proximate to the periphery of the three-dimensional region. See Elsherbini et al., e.g., Fig. 8 and para. [0063].
As for claim 16, Elsherbini et al. disclose the microelectronic assembly of claim 12 and further disclose that the first conductive trace comprises a first plurality of conductive traces, the second conductive trace comprises a second plurality of conductive traces, and the second plurality of conductive traces is parallel to the first plurality of conductive traces. See Elsherbini et al., e.g., Fig. 7 and para. [0062].
As for claim 17, Elsherbini et al. disclose the microelectronic assembly of claim 12 and further disclose that the second plurality of conductive traces has a lower routing density than the first plurality of conductive traces. See Elsherbini et al., e.g., Fig. 9 and para. [0064].
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini et al. in view of Yu et al.
Elsherbini et al. (Fig. 1A, Fig. 7A, Fig. 8A, Fig. 10A-10E, and paragraphs [0028]-[0035], [0050]-[0056], [0108]-[0124], and [0133]-[0141]) discloses an Integrated Circuit (IC), comprising:
a first conductive trace in a first die (host-chip BEOL metallization, conductive layers, traces, and interconnect features in the host chip);
a second conductive trace in a second die (chiplet metallization stack 114 with conductive layers 115 and pads 117); and
a conductive pathway electrically coupling the first conductive trace with the second conductive trace (electrical coupling between host chip and chiplet through interconnects / vias / bonded interfaces), wherein:
the second die is coupled to the first die with interconnects (chiplet-host coupling by interconnects, hybrid bonding, DTPS interconnects, DTD interconnects, vias, etc.).
Elsherbini does not clearly disclose the conductive pathway comprises a first portion of the interconnects located proximate to a first side of a periphery of a region in the first die through which the first conductive trace is not routable; and
the conductive pathway further comprises a second portion of the interconnects, located proximate to a second side of the periphery of the region in the first die opposite the first side, coupling the second conductive trace to a third conductive trace in the first die, wherein the first conductive trace is on the first side of the periphery of the region in the first die, the third conductive trace is on the second side of the periphery of the region in the first die, and the second conductive trace spans from the first side of the periphery region to the second side of the periphery region.
Yu et al. disclose a microelectronic assembly having a first die and a second die coupled by interconnects, with conductive contacts on opposing surfaces of one or more dies and with the dies arranged in an overlapped, stacked, or embedded configuration. Yu further teaches routing between dies through conductive interconnect structures and using package-level or die-level conductive pathways to communicate signals and power between separate dies. See, e.g., Yu Fig. 1A, Fig. 1B, Fig. 2A, Fig. 2B, Fig. 31-37, and paragraphs [0033]-[0055], [0091]-[0105], [0118]-[0124], and [0133]-[0149].
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Elsherbini’s embedded-chiplet composite IC structure using Yu’s teachings of inter-die conductive coupling and package-level/die-level interconnect configurations in order to provide conductive routing between separate conductive traces on opposite sides of an embedded or non-routable region, while maintaining chiplet integration and enabling flexible high-density signal and power routing. The combination would have predictably improved routing flexibility, allowed interconnection of traces located on different sides of a constrained routing region, and provided an alternative interconnect topology compatible with the embedded chiplet architecture of Elsherbini and the inter-die coupling teachings of Yu.
Accordingly, claim 1 would have been obvious over the combined teachings of Elsherbini in view of Yu.
Regarding claim 2, Elsherbini et al. in view of Yu et al. disclose the IC of claim 1.
Elsherbini discloses hybrid bonding between chiplet pads and host-chip pads, stating that chiplet metallization stack 114 may be hybrid-bonded to BEOL metallization stack 103, such that pads 111 and 117 are fused together by diffusion bonds. See, e.g., Elsherbini paragraphs [0047], [0089], and Fig. 6B.
Yu is consistent with the use of hybrid bond interconnects in multi-die assemblies.
Regarding claim 3, Elsherbini discloses a package substrate 102 coupled to a circuit board 133 by second-level interconnects 137, and the dies are electrically coupled to the package substrate 102 by DTPS interconnects 150. See, e.g., Elsherbini Fig. 1 and paragraphs [0033], [0047], and [0051].
Yu likewise teaches multi-die and package-support coupling arrangements.
Regarding claim 4, Elsherbini discloses a package substrate with a recess and/or embedded chiplet arrangements in which conductive paths extend through dielectric material, and further discloses vias extending through fill dielectric adjacent to chiplet sidewalls to interconnect to upper metallization levels. See, e.g., Elsherbini Fig. 7A–7C, Fig. 8A–8C, Fig. 10A–10E, and paragraphs [0108]–[0124].
Yu teaches TDV-based routing in composite IC structures and package-coupled assemblies in which conductive vias and DTPS-type interconnects are used to connect dies through insulating material surrounding an embedded structure.
It would have been obvious to combine these teachings to provide TDVs in insulating material surrounding the second die and DTPS interconnects to the package support. Therefore, claim 4 would have been obvious over Elsherbini in view of Yu.
Regarding claim 5, Elsherbini expressly teaches package substrate coupling by DTPS interconnects 150, including embodiments in which multiple dies are coupled to the package substrate. See, e.g., Elsherbini Fig. 1, Fig. 4, Fig. 5, and paragraphs [0042], [0046], [0059]–[0061].
Yu further supports this multi-die package-support coupling. Accordingly, claim 5 would have been obvious over Elsherbini in view of Yu.
Regarding claim 6, Elsherbini in view of Yu discloses the IC of claim 1, where the second die is electronically coupled to a third die (205, chiplet) (Fig 2B).
Regarding claim 7, Elsherbini discloses through-dielectric/via-based routing structures in fill dielectric material surrounding embedded chiplets, including vias 124 through fill dielectric 122 and vias adjacent to chiplet sidewalls. See, e.g., Elsherbini Fig. 2A, 7A–7C, Fig. 8A–8C, Fig. 10A–10E, and paragraphs [0052], [0108]–[0124], and [0126]–[0132].
Yu further teaches TDV-style routing through insulating material in multi-die assemblies.
It would have been obvious to arrange the TDVs at least partially in insulating material surrounding the second die so as to provide routing between the first die and third die. Therefore, claim 7 would have been obvious over Elsherbini in view of Yu.
Regarding claim 8, Elsherbini discloses die-to-die interconnects between multiple dies and also discloses vias in fill dielectric adjacent to chiplets. See, e.g., Elsherbini Fig. 1, Fig. 4–8, and paragraphs [0042]–[0047], [0058]–[0063], and [0108]–[0124].
Yu likewise teaches DTD interconnects among dies in a multi-die assembly. Accordingly, claim 8 would have been obvious over Elsherbini in view of Yu.
Regarding claim 9, Elsherbini expressly teaches hybrid bonding between chiplet pads and host-chip pads, and Yu also teaches hybrid bond interconnects in multi-die assemblies. See, e.g., Elsherbini paragraphs [0047], [0089], and Fig. 6B.
Therefore, claim 9 would have been obvious over Elsherbini in view of Yu.
Regarding claim 10, Elsherbini expressly discloses package substrate 102 coupled to dies 114 by DTPS interconnects 150. See, e.g., Elsherbini Fig. 1, Fig. 4, Fig. 5, and paragraphs [0033], [0042], [0047], and [0059]–[0061].
Yu is consistent with this package-support coupling. Accordingly, claim 10 would have been obvious over Elsherbini in view of Yu.
Regarding claim 11, Elsherbini discloses that chiplet metallization stack 114 includes multiple metallization layers, including metal layers 115 interleaved with dielectric layers 116, and that the chiplet includes multiple routing levels such as M’1, M’2, M’3, and M’4. See, e.g., Elsherbini paragraphs [0043]–[0046], [0050], and [0064]–[0071]. Elsherbini further teaches frontside pads 117 and backside pads 118 connected through multiple layers of metallization and vias, thereby showing multiple conductive traces at different metal layers in the chiplet.
Yu likewise teaches multi-layer conductive routing in dies.
It would have been obvious to provide an additional conductive trace in a different metal layer of the second die to facilitate routing between traces and interconnects, as such a modification would merely amount to a predictable use of known multi-layer metallization routing techniques.
Therefore, claim 11 would have been obvious over Elsherbini in view of Yu.
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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