DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/02/2026 has been entered.
Response to Arguments
Applicant’s arguments, see pages 9-13, filed 01/05/2026, with respect to the rejection(s) of Claims 1, 4, 5, 7, 9, 12-25 are rejected under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin et al. (US 20160079161 A1).
Claim Objections
Claims 3, 4 and 9 objected to because of the following informalities: claim 3 says (original) but the claim appears canceled, claim 4 is dependent on claim 3 (which appears canceled) and claim 9 depends on canceled claim 8. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Sell et al. (US 20190237404 A1) in view of Xie et al. (US 20190013241 A1) and Lin et al. (US 20160079161 A1).
Regarding claim 1, Sell discloses an integrated circuit structure, comprising:
a plurality of gate structures (mentioned in claim 1) above a substrate (102) each of the plurality of gate structures (104) having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a plurality of conductive trench contact structures (120) alternating with the plurality of gate structures (mentioned in claim 1); ([0015], Fig. 1F) each of the plurality of conductive trench contact structures (120) having an uppermost surface (122) at a same level as the uppermost surfaces (121) of the gate electrodes (104) of the plurality of gate structures (mentioned in claim 1); ([0008], Fig. 1F)
a plurality of dielectric spacers (106) a corresponding one of the plurality of dielectric spacers (106) between adjacent ones of the plurality of gate structures (mentioned in claim 1) and the plurality of conductive trench contact structures (120), each of the plurality of dielectric spacers (106) having an uppermost surface at a same level as the uppermost surface of each of the plurality of conductive trench contact structures (120); ([0008], Fig. 1F)
a plurality of conductive vias (128), individual ones of the plurality of conductive vias (128) on corresponding ones of the plurality of conductive trench contact structures (120), ([0016], Fig. 1F)
Sell does not disclose:
Wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures.
However, Xie discloses:
Wherein bottommost surfaces of the conductive vias (110) are below the uppermost surfaces of the plurality of conductive trench contact structures (30). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell and Xie to arrive at the claimed invention in order to have “reliably contacted raised source and drain regions of FETs, wherein the source/drain contacts show a low contact resistance.” (Xie, [0045])
Sell in view of Xie do not disclose:
and wherein individual ones of the plurality of conductive vias are in a recess in the corresponding one of the plurality of conductive trench contact structures and in a recess in a corresponding one of the plurality of dielectric spacers, the recess in the corresponding one of the plurality of conductive trench contact structures in a same horizontal plane as the recess in the corresponding one of the plurality of dielectric spacers.
However, Lin discloses:
and wherein individual ones of the plurality of conductive vias (54) are in a recess (labeled 49 in Fig. 5) in the corresponding one of the plurality of conductive trench contact structures (32) and in a recess (annotated below) in a corresponding one of the plurality of dielectric spacers (30), the recess (labeled 49 in Fig. 5) in the corresponding one of the plurality of conductive trench contact structures (32) in a same horizontal plane (below 40) as the recess (annotated below) in the corresponding one of the plurality of dielectric spacers (30).
PNG
media_image1.png
452
609
media_image1.png
Greyscale
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell, Xie and Lin to arrive at the claimed invention so that “the contact areas are thus increased, and the contact resistance is reduced.” (Lin, [0042])
Regarding claim 4, Lin discloses wherein the recess (labeled 49 in Fig. 5) in the corresponding one of the plurality of conductive trench contact structures (32) has a first depth, and wherein the recess (annotated above) in the corresponding one of the plurality of dielectric spacers (30) has a second depth herein the second depth is different than the first depth. (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lin for similar reasons mentioned beforehand.
Regarding claim 5, Xie discloses the integrated circuit structure of claim 1, wherein
individual ones of the plurality of conductive vias wrap (110) around a corner of corresponding ones of the plurality of conductive trench contact structures (30). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Xie for similar reasons mentioned beforehand.
Claims 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sell et al. (US 20190237404 A1) in view of Lin et al. (US 20160079161 A1).
Regarding claim 7, Sell discloses an integrated circuit structure, comprising:
a gate structure (mentioned in claim 1) above a substrate (102) the gate structure having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a conductive trench contact structure (120) adjacent to the gate structure (mentioned in claim 1); ([0015], Fig. 1F) the conductive trench contact structure (120) having an uppermost surface (122) at a same level as the uppermost surface (121) of the gate electrode (104) of the gate structure (mentioned in claim 1); (Fig. 1F)
a dielectric spacer (106) between the gate structure (mentioned in claim 1) and the conductive trench contact structure (120), the dielectric spacer (106) having an uppermost surface at a same level as the uppermost surface (122) of the conductive trench contact structure (120). ([0008], Fig. 1F)
a conductive via (128) over the dielectric spacer (106) and over the conductive trench contact structure (120), ([0016], Fig. 1F)
Sell does not disclose:
Wherein a bottommost surface of the conductive via is below the uppermost surface of the conductive trench contact structure.
and wherein the conductive via is in a recess in the conductive trench contact structure and in a recess in the dielectric spacer, the recess in the conductive trench contact structure in a same horizontal plane as the recess in the dielectric spacer.
However, Lin discloses:
Wherein a bottommost surface of the conductive via (54) is below the uppermost surface of the conductive trench contact structure (32). (Fig. 7)
and wherein the conductive via (54) is in a recess (labeled 49 in Fig. 5) in the conductive trench contact structure (32) and in a recess (annotated below) in the dielectric spacer (30), the recess in the conductive trench contact structure (32) in a same horizontal plane (below 40) as the recess in the dielectric spacer (30). (Fig. 7)
PNG
media_image1.png
452
609
media_image1.png
Greyscale
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell and Lin to arrive at the claimed invention so that “the contact areas are thus increased, and the contact resistance is reduced.” (Lin, [0042])
Regarding claim 9, Lin discloses wherein the recess (labeled 49 in Fig. 5) in the conductive trench contact structure (32) has a different depth than the recess (annotated above) in the dielectric spacer (30). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lin for similar reasons mentioned beforehand.
Claims 12-25 are rejected under 35 U.S.C. 103 as being unpatentable over Sell et al. (US 20190237404 A1) in view of Pethe et al. (US 20140077305 A1) and Lin et al. (US 20160079161 A1).
Regarding claim 12, Sell discloses:
a plurality of gate structures (mentioned in claim 1) above a substrate (102) each of the plurality of gate structures (mentioned in claim 1) having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a plurality of conductive trench contact structures (120) alternating with the plurality of gate structures (mentioned in claim 1); ([0015], Fig. 1F) each of the plurality of conductive trench contact structures (120) having an uppermost surface (122) at a same level as the uppermost surfaces (121) of the gate electrodes (104) of the plurality of gate structures (mentioned in claim 1); (Fig. 1F)
a plurality of dielectric spacers (106) a corresponding one of the plurality of dielectric spacers (106) between adjacent ones of the plurality of gate structures (mentioned in claim 1) and the plurality of conductive trench contact structures (120), each of the plurality of dielectric spacers (106) having an uppermost surface at a same level as the uppermost surface of each of the plurality of conductive trench contact structures (120); ([0008], Fig. 1F)
a plurality of conductive vias (128), individual ones of the plurality of conductive vias (128) on corresponding ones of the plurality of conductive trench contact structures (120), ([0016], Fig. 1F)
Sell does not disclose:
A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure and
wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures.
However, Pethe discloses:
A computing device (800), ([0077], Fig. 8) comprising:
a board (802); ([0071], Fig. 8) and
a component (800) coupled to the board (802), the component including an integrated circuit structure (806), ([0071], Fig. 8)
it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe to have a computing device comprising: a board; and a component coupled to the board, the component including an integrated circuit structure in order to “fabricate of products with increased capacity… to optimize the performance of each device” (Pethe, [0002])
Sell in view of Pethe do not disclose:
Wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures,
and wherein individual ones of the plurality of conductive vias are in a recess in the corresponding one of the plurality of conductive trench contact structures and in a recess in a corresponding one of the plurality of dielectric spacers, the recess in the corresponding one of the plurality of conductive trench contact structures in a same horizontal plane as the recess in the corresponding one of the plurality of dielectric spacers.
However, Lin discloses:
Wherein bottommost surfaces of the conductive vias (54) are below the uppermost surfaces of the plurality of conductive trench contact structures (32). (Fig. 7)
and wherein individual ones of the plurality of conductive vias (54) are in a recess (labeled 49 in Fig. 5) in the corresponding one of the plurality of conductive trench contact structures (32) and in a recess (annotated below) in a corresponding one of the plurality of dielectric spacers (30), the recess (labeled 49 in Fig. 5) in the corresponding one of the plurality of conductive trench contact structures (32) in a same horizontal plane (below 40) as the recess (annotated below) in the corresponding one of the plurality of dielectric spacers (30).
PNG
media_image1.png
452
609
media_image1.png
Greyscale
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell, Pethe, and Lin to arrive at the claimed invention so that “the contact areas are thus increased, and the contact resistance is reduced.” (Lin, [0042])
Regarding claim 13, Pethe discloses the computing device of claim 12, further comprising: a memory (DRAM) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 14, Pethe discloses the computing device of claim 12, further comprising: a communication chip (806) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 15, Pethe discloses the computing device of claim 12, further comprising: a camera (camera) coupled to the board (802), ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 16, Pethe discloses the computing device of claim 12, wherein the component (800) is a packaged integrated circuit die. ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Claims 17-25 are rejected under 35 U.S.C. 103 as being unpatentable over Sell et al. (US 20190237404 A1) in view of Pethe et al. (US 20140077305 A1), Xie et al. (US 20190013241 A1) and Lin et al. (US 20160079161 A1).
Regarding claim 17, Sell discloses:
a gate structure (mentioned in claim 1) over a substrate (102) the gate structure having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a conductive trench contact structure (120) adjacent to the gate structure, (mentioned in claim 1) the conductive trench contact structure (120) having an uppermost surface (122) at a same level as the uppermost surface (121) of the gate electrode (104) of the gate structure (mentioned in claim 1); ([0015], Fig. 1F)
a dielectric spacer (106) between the gate structure (104) and the conductive trench contact structure (120), the dielectric spacer (106) having an uppermost surface at a same level as the uppermost surface (122) of the conductive trench contact structure (120). ([0008], Fig. 1F)
a conductive via (128) over the dielectric spacer (106) and over the conductive trench contact (120). ([0016], Fig. 1F)
Sell does not disclose:
A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure and
However, Pethe discloses:
A computing device (800), ([0077], Fig. 8) comprising:
a board (802); ([0071], Fig. 8) and
a component (800) coupled to the board (802), the component including an integrated circuit structure (806), ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe to have a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure in order to “fabricate of products with increased capacity… to optimize the performance of each device” (Pethe, [0002])
Sell in view of Pethe do not disclose:
Sell does not disclose:
Wherein a bottommost surface of the conductive via is below the uppermost surface of the conductive trench contact structure.
However, Xie discloses:
Wherein a bottommost surface of the conductive via (110) is below the uppermost surface of the conductive trench contact structure (30). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell Pethe and Xie to arrive at the claimed invention in order to have “reliably contacted raised source and drain regions of FETs, wherein the source/drain contacts show a low contact resistance.” (Xie, [0045])
Sell in view of Pethe and Xie do not disclose:
and wherein the conductive via is in a recess in the conductive trench contact structure and in a recess in the dielectric spacer, the recess in the conductive trench contact structure in a same horizontal plane as the recess in the dielectric spacer.
However, Lin discloses:
and wherein the conductive via (54) is in a recess (labeled 49 in Fig. 5) in the conductive trench contact structure (32) and in a recess (annotated below) in the dielectric spacer (30), the recess in the conductive trench contact structure (32) in a same horizontal plane (below 40) as the recess in the dielectric spacer (30). (Fig. 7)
PNG
media_image1.png
452
609
media_image1.png
Greyscale
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell, Pethe, Xie and Lin to arrive at the claimed invention so that “the contact areas are thus increased, and the contact resistance is reduced.” (Lin, [0042])
Regarding claim 18, Pethe discloses the computing device of claim 17, further comprising: a memory (DRAM) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 19, Pethe discloses the computing device of claim 17, further comprising: a communication chip (806) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 20, Pethe discloses the computing device of claim 17, further comprising: a camera (camera) coupled to the board (802), ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 21, Pethe discloses the computing device of claim 17, wherein the component (800) is a packaged integrated circuit die. ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe for similar reasons mentioned beforehand.
Regarding claim 22, Lin discloses the computing device of claim 17, further comprising:
a first recess (annotated above) in the dielectric spacer (30); (Fig. 7) and
a second recess (labeled 49 in Fig. 5) in the conductive trench contact structure (32). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lin to arrive at the claimed invention for similar mentioned beforehand.
Regarding claim 23, Lin discloses the computing device of claim of claim 22, wherein the first recess (annotated above) has a different depth than the second recess (labeled 49 in Fig. 5). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lin to arrive at the claimed invention for similar mentioned beforehand.
Regarding claim 24, Xie discloses the computing device of claim 17, further comprising: a recess (95) into the dielectric spacer, wherein the conductive via (110) fills the recess and wraps around a corner of the conductive trench contact structure (30). (Fig. 2n and 2o).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Xie to arrive at the claimed invention for similar mentioned beforehand.
Regarding claim 25, Lin discloses the computing device of claim of claim 17, a recess (labeled 49 in Fig. 5) into the conductive trench contact structure (32), wherein the conductive via (54) fills the recess (labeled 49 in Fig. 5). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lin to arrive at the claimed invention for similar mentioned beforehand.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights