DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 9-13, filed 01/05/2026, with respect to the rejection(s) of Claims 1-25 are rejected under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sell et al. (US 20190237404 A1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sell et al. (US 20190237404 A1) in view of Xie et al. (US 20190013241 A1).
Regarding claim 1, Sell discloses an integrated circuit structure, comprising:
a plurality of gate structures (mentioned in claim 1) above a substrate (102) each of the plurality of gate structures (104) having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a plurality of conductive trench contact structures (120) alternating with the plurality of gate structures (mentioned in claim 1); ([0015], Fig. 1F) each of the plurality of conductive trench contact structures (120) having an uppermost surface (122) at a same level as the uppermost surfaces (121) of the gate electrodes (104) of the plurality of gate structures (mentioned in claim 1); ([0008], Fig. 1F)
a plurality of dielectric spacers (106) a corresponding one of the plurality of dielectric spacers (106) between adjacent ones of the plurality of gate structures (mentioned in claim 1) and the plurality of conductive trench contact structures (120), each of the plurality of dielectric spacers (106) having an uppermost surface at a same level as the uppermost surface of each of the plurality of conductive trench contact structures (120); ([0008], Fig. 1F)
a plurality of conductive vias (128), individual ones of the plurality of conductive vias (128) on corresponding ones of the plurality of conductive trench contact structures (120), ([0016], Fig. 1F)
Sell does not disclose:
Wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures.
However, Xie discloses:
Wherein bottommost surfaces of the conductive vias (110) are below the uppermost surfaces of the plurality of conductive trench contact structures (30). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures so that “a very reliable connection between the CA contact structures 110 and the TS structures 30 with an enhanced contact area can be provided.” (Xie, [0043])
Regarding claim 2, Xie discloses the integrated circuit structure of claim 1, wherein
individual ones of the plurality of conductive trench contact structures (30) comprise recesses (90 and 95), (Fig. 2j-2r) and wherein
individual ones of the plurality of conductive vias (110) fill corresponding ones of the recesses (90 and 95). (Fig. 2j-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 3, Xie discloses the integrated circuit structure of claim 2, wherein
the recesses (90 and 95) extend into adjacent ones of the plurality of dielectric spacers (60+70). (Fig. 2j-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 4, Xie discloses the integrated circuit structure of claim 3, wherein
the recesses (90 and 95) have a first depth (of 95) in individual ones of the plurality of conductive trench contact structures (30), (Fig. 2m-2o) and wherein
the recesses (90 and 95) have a second depth (of 90) in individual ones of the plurality of dielectric spacers (60+70), wherein
the second depth (of 90) is different than the first depth (of 95). (Fig. 2m-2o).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 5, Xie discloses the integrated circuit structure of claim 1, wherein
individual ones of the plurality of conductive vias wrap (110) around a corner of corresponding ones of the plurality of conductive trench contact structures (30). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 6, Xie discloses the integrated circuit structure of claim 5, wherein
individual ones of the plurality of conductive vias (110) fill a recess in a neighboring dielectric spacer (60+70). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 7, Sell discloses an integrated circuit structure, comprising:
a gate structure (mentioned in claim 1) above a substrate (102) the gate structure having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a conductive trench contact structure (120) adjacent to the gate structure (mentioned in claim 1); ([0015], Fig. 1F) the conductive trench contact structure (120) having an uppermost surface (122) at a same level as the uppermost surface (121) of the gate electrode (104) of the gate structure (mentioned in claim 1); (Fig. 1F)
a dielectric spacer (106) between the gate structure (mentioned in claim 1) and the conductive trench contact structure (120), the dielectric spacer (106) having an uppermost surface at a same level as the uppermost surface (122) of the conductive trench contact structure (120). ([0008], Fig. 1F)
a conductive via (128) over the dielectric spacer (106) and over the conductive trench contact structure (120), ([0016], Fig. 1F)
Sell does not disclose:
Wherein a bottommost surface of the conductive via is below the uppermost surface of the conductive trench contact structure.
However, Xie discloses:
Wherein a bottommost surface of the conductive via (110) is below the uppermost surface of the conductive trench contact structure (30). (Fig. 2p-2r).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for a bottommost surface of the conductive via is below the uppermost surface of the conductive trench contact structure so that “a very reliable connection between the CA contact structures 110 and the TS structures 30 with an enhanced contact area can be provided.” (Xie, [0043])
Regarding claim 8, Xie discloses the integrated circuit structure of claim 7, further comprising:
a first recess (90) in the dielectric spacer (60+70); (Fig. 2m-2o) and
a second recess (95) in the conductive trench contact structure (30). (Fig. 2m-2o).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 9, Xie discloses the integrated circuit structure of claim 8, wherein
the first recess (95) has a different depth than the second recess (90). (Fig. 2m-2o).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 10, Xie discloses the integrated circuit structure of claim 7, further comprising:
a recess (90) into the dielectric spacer (60+70), wherein the conductive via (110) fills the recess (90) and wraps around a corner of the conductive trench contact structure (30). (Fig. 2n and 2q).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Regarding claim 11, Xie discloses the integrated circuit structure of claim 7, further comprising:
a recess (95) into the conductive trench contact structure (30), wherein the conductive via (110) fills the recess (95). (Fig. 2n and 2q).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for similar reasons mentioned beforehand.
Claims 12-25 are rejected under 35 U.S.C. 103 as being unpatentable over Sell et al. (US 20190237404 A1) in view of Pethe et al. (US 20140077305 A1) and Xie et al. (US 20190013241 A1).
Regarding claim 12, Sell discloses:
a plurality of gate structures (mentioned in claim 1) above a substrate (102) each of the plurality of gate structures (mentioned in claim 1) having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a plurality of conductive trench contact structures (120) alternating with the plurality of gate structures (mentioned in claim 1); ([0015], Fig. 1F) each of the plurality of conductive trench contact structures (120) having an uppermost surface (122) at a same level as the uppermost surfaces (121) of the gate electrodes (104) of the plurality of gate structures (mentioned in claim 1); (Fig. 1F)
a plurality of dielectric spacers (106) a corresponding one of the plurality of dielectric spacers (106) between adjacent ones of the plurality of gate structures (mentioned in claim 1) and the plurality of conductive trench contact structures (120), each of the plurality of dielectric spacers (106) having an uppermost surface at a same level as the uppermost surface of each of the plurality of conductive trench contact structures (120); ([0008], Fig. 1F)
a plurality of conductive vias (128), individual ones of the plurality of conductive vias (128) on corresponding ones of the plurality of conductive trench contact structures (120), ([0016], Fig. 1F)
Sell does not disclose:
A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure and
wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures.
However, Pethe discloses:
A computing device (800), ([0077], Fig. 8) comprising:
a board (802); ([0071], Fig. 8) and
a component (800) coupled to the board (802), the component including an integrated circuit structure (806), ([0071], Fig. 8)
it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe to have a computing device comprising: a board; and a component coupled to the board, the component including an integrated circuit structure in order to “fabricate of products with increased capacity… to optimize the performance of each device” (Pethe, [0002])
and furthermore, Xie discloses:
Wherein bottommost surfaces of the conductive vias (110) are below the uppermost surfaces of the plurality of conductive trench contact structures (30). (Fig. 2p)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Xie for wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures in order to “connect the circuit elements fumed in the semiconductor material with the metallization layers” (Xie, [0006]) so as to “reduce the physical size of the semiconductor device”. (Xie, [0004]).
Regarding claim 13, Pethe discloses the computing device of claim 12, further comprising:
a memory (DRAM) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 14, Pethe discloses the computing device of claim 12, further comprising:
a communication chip (806) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 15, Pethe discloses the computing device of claim 12, further comprising:
a camera (camera) coupled to the board (802), ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 16, Pethe discloses the computing device of claim 12, wherein
the component (800) is a packaged integrated circuit die. ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 17, Sell discloses:
a gate structure (mentioned in claim 1) over a substrate (102) the gate structure having a gate electrode (104) with an uppermost surface (121); ([0014], Fig. 1F)
a conductive trench contact structure (120) adjacent to the gate structure, (mentioned in claim 1) the conductive trench contact structure (120) having an uppermost surface (122) at a same level as the uppermost surface (121) of the gate electrode (104) of the gate structure (mentioned in claim 1); ([0015], Fig. 1F)
a dielectric spacer (106) between the gate structure (104) and the conductive trench contact structure (120), the dielectric spacer (106) having an uppermost surface at a same level as the uppermost surface (122) of the conductive trench contact structure (120). ([0008], Fig. 1F)
a conductive via (128) over the dielectric spacer (106) and over the conductive trench contact (120). ([0016], Fig. 1F)
Sell does not disclose:
A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure and
wherein bottommost surfaces of the conductive vias are below the uppermost surfaces of the plurality of conductive trench contact structures.
However, Pethe discloses:
A computing device (800), ([0077], Fig. 8) comprising:
a board (802); ([0071], Fig. 8) and
a component (800) coupled to the board (802), the component including an integrated circuit structure (806), ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe to have a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure in order to “fabricate of products with increased capacity… to optimize the performance of each device” (Pethe, [0002])
And furthermore, Xie discloses:
wherein a bottommost surface of the conductive via (110) is below the uppermost surface of the conductive trench contact structure (30). (Fig. 2p)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Pethe and Xie for wherein a bottommost surface of the conductive via is below the uppermost surface of the conductive trench contact structure in order to “connect the circuit elements fumed in the semiconductor material with the metallization layers” (Xie, [0006]) so as to “reduce the physical size of the semiconductor device”. (Xie, [0004])
Regarding claim 18, Pethe discloses the computing device of claim 17, further comprising:
a memory (DRAM) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 19, Pethe discloses the computing device of claim 17, further comprising:
a communication chip (806) coupled to the board (802). ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 20, Pethe discloses the computing device of claim 17, further comprising:
a camera (camera) coupled to the board (802), ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 21, Pethe discloses the computing device of claim 17, wherein
the component (800) is a packaged integrated circuit die. ([0071], Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Sell and Pethe for similar reasons mentioned beforehand.
Regarding claim 22, Xie discloses the computing device of claim 17, further comprising:
a first recess (90) in the dielectric spacer (60+70); (Fig. 2m-2o) and a second recess (95) in the conductive trench contact structure (30). (Fig. 2m-2o).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell and Xie to arrive at the claimed invention for similar mentioned beforehand.
Regarding claim 23, Xie discloses the computing device of claim of claim 22, wherein
the first recess (90) has a different depth than the second recess (95). (Fig. 2m-2o).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell and Xie to arrive at the claimed invention for similar mentioned beforehand.
Regarding claim 24, Xie discloses the computing device of claim 17, further comprising:
a recess (90) into the dielectric spacer (60+70), wherein the conductive via (110) fills the recess (90) and wraps around a corner of the conductive trench contact structure (30). (Fig. 2n and 2o).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell and Xie to arrive at the claimed invention for similar mentioned beforehand.
Regarding claim 25, Xie discloses the computing device of claim of claim 17
a recess (95) into the conductive trench contact structure (30), wherein the conductive via (110) fills the recess (95). (Fig. 2n and 2q).
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Sell and Xie to arrive at the claimed invention for similar mentioned beforehand.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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