Attorney’s Docket Number: AC8343-US 111548-262240
Filing Date: 6/14/2021
Claimed Priority Date: none
Inventors: Guler et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 12/29/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 12/29/2025 in reply to the previous Office action mailed on 09/30/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3, 5-8, and 10-20, with claims 6-8, 10, and 16-20 remaining withdrawn from consideration.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 112 and 118 have both been used to designate the same additional dummy gate material in figure 1D.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character 122 has been used to designate an insulator cap, a nanowire, and a gate cut landing structure in figure 1E.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 304 and 306 have both been used to designate the same shallow trench isolation (STI) structures in figure 3A.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 706’ and 706 have both been used to designate the same recessed nanowires in figure 7J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character 716 has been used to designate both a protective cap and cavity spacers in figure 7J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: 1000.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Paul (US 2021/0020644) in view of Smith (US 2019/0172828), Chanemougame (US 10,510,620), and Lim (US 2020/0135848).
Regarding claims 1 and 11, Paul (see, e.g., fig. 15 and par.0064/ll.11-18) shows most aspects of the instant invention, including an integrated circuit structure comprising a board and a component coupled to the board, the component including an integrated circuit structure comprising:
a sub-fin and a shallow trench isolation (STI) structure 114;
a plurality of horizontally stacked nanowires 220N over the sub-fin;
a gate dielectric material layer 240 over the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer 242A/242B over the gate dielectric material layer;
a conductive gate fill material 244 over the conductive gate layer;
a dielectric gate cap 250 on the conductive gate fill material (see, e.g., par.0060/ll.1-3);
a dielectric structure 162 laterally spaced apart from the plurality of horizontally stacked nanowires; and
a dielectric gate plug 164 landed on the dielectric structure, wherein the dielectric gate plug is in contact with the dielectric gate cap, and wherein the dielectric gate plug has an uppermost surface in direct contact with the dielectric gate cap
Paul teaches that the gate cap 250 may be composed of a nitride, and that nitrides can be dielectric materials (see, e.g., par.0046/ll.23-26). Therefore, Paul teaches that Paul’s gate cap is a dielectric gate cap. Furthermore, Smith, in the same field of endeavor, teaches that dielectric gate caps (such as those made from nitride) can isolate gates from other components of a device (see, e.g., Smith: par.0057/ll.7-9 and 0118/ll.14). Paul, however, fails to specify that the sub-fin may have a portion protruding above the STI structure. Chanemougame, in the same field of endeavor and in a similar device to Paul, shows a portion of a sub-fin protruding above an STI structure 114 (see, e.g., Chanemougame: fig. 17). Lim, also in the same field of endeavor and in a similar device to Paul, also shows a portion of a sub-fin ARP protruding above an STI structure 15 (see, e.g., Lim: fig. 2).
Chanemougame and Lim evidence showing that one of ordinary skill in the art would appreciate that having a sub-fin protruding above an STI structure would be equivalent to having a sub-fin and STI structure matching in height, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Paul. That is, the sub-fins of both Chanemougame or Lim and Paul would yield the predictable result of providing a substrate active region that would support forming nanostructures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the cap layer of Paul be dielectric, as already suggested by Paul, so as to improve the isolation of Paul’s gates, as taught by Smith. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a sub-fin having a portion protruding above an STI structure, as taught by Chanemougame and Lim, or a sub-fin matching in height to an STI structure, as taught by Paul, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a support substrate for forming nanostructures. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Additionally, Paul teaches most aspects of the instant invention (see paragraphs 12-15 above). Paul further teaches that that a dielectric material may comprise the uppermost surface of Paul’s integrated circuit structure, that Paul’s dielectric gate plug and dielectric gate cap may both comprise nitrides, and that an uppermost surface of Paul’s dielectric gate plug may directly contact Paul’s dielectric gate cap (see, e.g., Paul: fig. 15 and pars.0046/ll.23-26 and 0060/ll.1-3). Paul, however, fails to explicitly specify that Paul’s dielectric gate plug has an uppermost surface at a same level as an uppermost surface of the dielectric gate cap.
Lim, in the same field of endeavor and in a similar device to Paul, teaches an integrated circuit structure wherein a dielectric gate plug 80 directly contacts and penetrates through a dielectric gate cap 75 such that the dielectric gate plug has an uppermost surface at a same level as an uppermost surface of the dielectric gate cap, wherein Lim also teaches that Lim’s dielectric gate plug and dielectric gate cap may both comprise nitrides (see, e.g., Lim: fig. 2 and pars.0034/ll.5-10 and 0037/ll.3-4). Lim further teaches that the structure Lim depicts allows the dielectric gate cap to function as a protection layer preventing oxygen from penetrating underlying conductive layers, ensuring voltage threshold stability (see, e.g., Lim: par.0071).
Lim is evidence showing that one of ordinary skill in the art would appreciate that a dielectric gate plug having an uppermost surface at a same level as an uppermost surface of a dielectric gate cap would be equivalent to an uppermost surface of a dielectric gate plug in direct contact with a dielectric gate cap, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Paul. That is, the dielectric gate plugs and dielectric gate caps of both Lim and Paul would yield the predictable result of providing insulative structures capable of isolating various elements and components of an integrated circuit structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a dielectric gate plug having an uppermost surface at a same level as an uppermost surface of a dielectric gate cap, as taught by Lim, or an uppermost surface of a dielectric gate plug in direct contact with a dielectric gate cap, as taught by Paul, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a support substrate for forming nanostructures. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Furthermore, Lim is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Paul’s dielectric gate plug have an uppermost surface at a same level as an uppermost surface of Paul’s dielectric gate cap, as taught by Lim, so as to allow Paul’s dielectric gate cap to function as a protection layer preventing oxygen from penetrating underlying conductive layers, ensuring voltage threshold stability in Paul’s integrated circuit structure.
Regarding claim 2, Paul (see, e.g., par.0049/ll.3-4) shows that the gate dielectric material layer 240 is a high-k gate dielectric layer.
Regarding claim 3, Paul (see, e.g., par.0049/ll.4) shows that the conductive gate layer 242A/242B is a workfunction metal layer.
Regarding claim 5, Paul (see, e.g., fig. 15) shows that the gate dielectric material layer 240 and conductive gate layer 242A/242B are not along sides of the dielectric gate plug 164, and that the conductive gate fill material 244 is in contact with the sides of the dielectric gate plug.
Regarding claim 12, Paul shows a memory (see, e.g., par.0008/ll.1-2) coupled to the board (see, e.g., par.0064/ll.11-14).
Regarding claim 14, Paul shows that the component (see, e.g., par.0064/ll.11-14) may be a packaged integrated circuit die (see, e.g., par.0064/ll.1-10).
Regarding claim 15, Paul (see, e.g., par.0064/ll.11-18) shows that the component may be a processor.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Paul/Smith/Chanemougame/Lim in view of Guha (US 2020/0091348).
Regarding claim 13, Paul/Smith/Chanemougame/Lim shows most aspects of the instant invention (see paragraphs 12-20 above). Paul further shows that the component (see, e.g., par.0064/ll.11-18) may be used as part of advanced computer products having a display, a keyboard, or other input device, but fails to specify that there is a communication chip coupled to the board (see, e.g., par.0064/ll.11-14). Guha, in the same field of endeavor, teaches that having a communication chip coupled to a board may enable wireless communications for the transfer of data to and from a computing device (see, e.g., Guha: fig. 10 and par.0152/ll.1-3).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the communication chip of Guha in the computing device of Paul/Smith/Chanemougame/Lim to facilitate the transfer of data to and from the computing device of Paul/Smith/Chanemougame/Lim.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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