Attorney’s Docket Number: AC8343-US 111548-262240
Filing Date: 6/14/2021
Claimed Priority Date: none
Inventors: Guler et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the RCE filed on 04/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection mailed on 02/17/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 04/13/2026 has been entered.
Amendment Status
The RCE submission filed on 04/13/2026 as an amendment in reply to the Office action mailed on 02/17/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3, 5-8, and 10-20, with claims 6-8, 10, and 16-20 remaining withdrawn from consideration.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 112 and 118 have both been used to designate the same additional dummy gate material in figure 1D.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character 122 has been used to designate an insulator cap, a nanowire, and a gate cut landing structure in figure 1E.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 304 and 306 have both been used to designate the same shallow trench isolation (STI) structures in figure 3A.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 706’ and 706 have both been used to designate the same recessed nanowires in figure 7J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character 716 has been used to designate both a protective cap and cavity spacers in figure 7J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: 1000.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, and 11-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ghani (US 2022/0392898).
Regarding claims 11 and 1, Ghani (see, e.g., figs. 4B and 12 and par.0143) shows all aspects of the instant invention, including a computing device 1200 comprising a board 1202 and a component (e.g., packaged die within 1204) coupled to the board, the component including an integrated circuit structure 450 comprising:
a sub-fin 452 having a portion protruding above a shallow trench isolation (STI) structure 454;
a plurality of horizontally stacked nanowires 455 over the sub-fin;
a gate dielectric material layer 456 over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer 458 over the gate dielectric material layer;
a conductive gate fill material 460 over the conductive gate layer;
a dielectric gate cap 462 on the conductive gate fill material;
a dielectric structure 453 laterally spaced apart from the plurality of horizontally stacked nanowires; and
a dielectric gate plug 464 landed on the dielectric structure;
wherein:
the dielectric gate plug 464 has a lateral width less than a lateral width of the dielectric structure 453 at an interface between the dielectric gate plug and the dielectric structure;
the dielectric gate plug is in contact with the dielectric gate cap 462; and
the dielectric gate plug has an uppermost surface at a same level as an uppermost surface of the dielectric gate cap (see, e.g., par.0052/ll.7-8)
Regarding claim 2, Ghani (see, e.g., par.0051/ll.9-10) shows that the gate dielectric material layer 456 is a high-k gate dielectric layer.
Regarding claim 3, Ghani (see, e.g., par.0051/ll.20-21) shows that the conductive gate layer 458 is a workfunction metal layer.
Regarding claim 5, Ghani (see, e.g., fig. 4B) shows that the gate dielectric material layer 456 and the conductive gate layer 458 are not along sides of the dielectric gate plug 464, and wherein the conductive gate fill material 460 is in contact with sides of the dielectric gate plug.
Regarding claim 12, Ghani (see, e.g., fig. 12) further shows a memory ROM coupled to the board 1202.
Regarding claim 13, Ghani (see, e.g., fig. 12) further shows a communication chip 1206 coupled to the board 1202.
Regarding claim 14, Ghani (see, e.g., fig. 12 and par.0143) shows that the component (e.g., packaged die within 1204) is a packaged integrated circuit die.
Regarding claim 15, Ghani (see, e.g., pars.0139, 0141, 0144, 0167, and 0172) shows that the component (e.g., packaged die within 1204) is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Paul (US 2021/0020644) in view of Smith (US 2019/0172828), Lim (US 2020/0135848), and Chiang (US 2021/0375858).
Regarding claims 1 and 11, Paul (see, e.g., fig. 15 and par.0064/ll.11-18) shows most aspects of the instant invention, including a computing device comprising a board and a component coupled to the board, the component including an integrated circuit structure comprising:
a sub-fin and a shallow trench isolation (STI) structure 114;
a plurality of horizontally stacked nanowires 220N over the sub-fin;
a gate dielectric material layer 240 over the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer 242A/242B over the gate dielectric material layer;
a conductive gate fill material 244 over the conductive gate layer;
a dielectric gate cap 252 on the conductive gate fill material (see, e.g., par.0060/ll.1-3);
a dielectric structure 162 laterally spaced apart from the plurality of horizontally stacked nanowires; and
a dielectric gate plug 164 landed on the dielectric structure, wherein the dielectric gate plug and the dielectric structure each respectively comprise lateral widths at an interface between the dielectric gate plug and the dielectric structure, wherein the dielectric gate plug is in contact with the dielectric gate cap, and wherein the dielectric gate plug and the dielectric gate cap each respectively comprise uppermost surfaces such that the uppermost surface of the dielectric gate plug contacts the dielectric gate cap
Paul teaches that the gate cap 250 may be composed of a nitride, and that nitrides can be dielectric materials (see, e.g., par.0046/ll.23-26). Therefore, Paul teaches that Paul’s gate cap is a dielectric gate cap. Furthermore, Smith, in the same field of endeavor, teaches that dielectric gate caps (such as those made from nitride) can facilitate isolating gates from other components of a device (see, e.g., Smith: par.0057/ll.7-9 and 0118/ll.14). Paul, however, fails to specify that the sub-fin may have a portion protruding above the STI structure. Lim, in the same field of endeavor and in a similar device to Paul, shows a portion of a sub-fin ARP protruding above an STI structure 15 (see, e.g., Lim: fig. 2).
Lim is evidence showing that one of ordinary skill in the art would appreciate that having a sub-fin protruding above an STI structure would be equivalent to having a sub-fin and STI structure matching in height, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Paul. That is, the sub-fins of both Lim and Paul would yield the predictable result of providing a substrate active region that would support forming nanostructures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the cap layer of Paul be dielectric, as already suggested by Paul, so as to improve the isolation of Paul’s gates, as taught by Smith. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a sub-fin having a portion protruding above an STI structure, as taught by Lim, or a sub-fin matching in height to an STI structure, as taught by Paul, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a support substrate for forming nanostructures. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Additionally, Paul teaches most aspects of the instant invention (see paragraphs 23-26 above). Paul further teaches that that a dielectric material may comprise the uppermost surface of Paul’s integrated circuit structure, that Paul’s dielectric gate plug and dielectric gate cap may both comprise nitrides, and that an uppermost surface of Paul’s dielectric gate plug may contact Paul’s dielectric gate cap (see, e.g., Paul: fig. 15 and pars.0046/ll.23-26 and 0060/ll.1-3). Paul, however, fails to explicitly specify that Paul’s dielectric gate plug has an uppermost surface at a same level as an uppermost surface of the dielectric gate cap.
Lim, in the same field of endeavor and in a similar device to Paul, teaches an integrated circuit structure wherein a dielectric gate plug 80 contacts and penetrates through a dielectric gate cap 75 such that the dielectric gate plug has an uppermost surface at a same level as an uppermost surface of the dielectric gate cap, wherein Lim also teaches that Lim’s dielectric gate plug and dielectric gate cap may both comprise nitrides (see, e.g., Lim: fig. 2 and pars.0034/ll.5-10 and 0037/ll.3-4). Lim further teaches that the structure Lim depicts allows the dielectric gate cap to function as a protection layer preventing oxygen from penetrating underlying conductive layers, ensuring voltage threshold stability (see, e.g., Lim: par.0071).
Lim is evidence showing that one of ordinary skill in the art would appreciate that a dielectric gate plug having an uppermost surface at a same level as an uppermost surface of a dielectric gate cap would be equivalent to an uppermost surface of a dielectric gate plug in contact with a dielectric gate cap, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Paul. That is, the dielectric gate plugs and dielectric gate caps of both Lim and Paul would yield the predictable result of providing insulative structures capable of isolating, insulating, and separating various elements and components of an integrated circuit structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a dielectric gate plug having an uppermost surface at a same level as an uppermost surface of a dielectric gate cap, as taught by Lim, or an uppermost surface of a dielectric gate plug in contact with a dielectric gate cap, as taught by Paul, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing insulative structures capable of isolating, insulating, and separating various elements and components of an integrated circuit structure. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Furthermore, Lim is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have Paul’s dielectric gate plug have an uppermost surface at a same level as an uppermost surface of Paul’s dielectric gate cap, as taught by Lim, so as to allow Paul’s dielectric gate cap to function as a protection layer preventing oxygen from penetrating underlying conductive layers, ensuring voltage threshold stability in Paul’s integrated circuit structure.
Additionally, Paul teaches most aspects of the instant invention (see paragraphs 23-26 above). Paul further teaches that that Paul’s device comprises a dielectric gate plug landed on a dielectric structure and that Paul’s drawings are not necessarily to scale and therefore should not be considered as limiting the scope of Paul’s device (see, e.g., Paul: fig. 15 and par.0026). Paul, however, fails to explicitly specify that Paul’s dielectric gate has a lateral width less than a lateral width of the dielectric structure at an interface between the dielectric gate plug and the dielectric structure.
Chiang, in the same field of endeavor and in a similar device to Paul, teaches an integrated circuit structure comprising nanowires 220’, wherein a dielectric gate plug 365A is landed on a dielectric structure 270A, and wherein the dielectric gate plug has a lateral width D7 less than a lateral width D4 of the dielectric structure at an interface between the dielectric gate plug and the dielectric structure (see, e.g., Chiang: fig. 33 and pars.0045/ll.1-2 and 0051/ll.9-12). Chiang further teaches that other lateral width dispositions (e.g., where the lateral width of the dielectric gate plug is not less than a lateral width of the dielectric structure at a shared interface) function equally as suitable dielectric gate plugs and dielectric structures in integrated circuit structure devices (see, e.g., Chiang: par.0051/ll.30-31).
Chiang is evidence showing that one of ordinary skill in the art would appreciate that a dielectric gate plug having a lateral width less than a lateral width of a dielectric structure at an interface between the dielectric gate plug and the dielectric structure would be equivalent to a dielectric gate plug and dielectric structure having another lateral width relationship at an interface between the dielectric gate plug and the dielectric structure, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Paul. That is, the dielectric gate plugs and dielectric structures of both Chiang and Paul would yield the predictable result of providing insulative structures capable of isolating, insulating, and separating various elements and components of an integrated circuit structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a dielectric gate plug having a lateral width less than a lateral width of a dielectric structure at an interface between the dielectric gate plug and the dielectric structure, as taught by Chiang, or a dielectric gate plug and dielectric structure having another lateral width relationship at an interface between the dielectric gate plug and the dielectric structure, as taught by both Paul and Chiang, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing insulative structures capable of isolating, insulating, and separating various elements and components of an integrated circuit structure. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 2, Paul (see, e.g., par.0049/ll.3-4) shows that the gate dielectric material layer 240 is a high-k gate dielectric layer.
Regarding claim 3, Paul (see, e.g., par.0049/ll.4) shows that the conductive gate layer 242A/242B is a workfunction metal layer.
Regarding claim 5, Paul (see, e.g., fig. 15) shows that the gate dielectric material layer 240 and conductive gate layer 242A/242B are not along sides of the dielectric gate plug 164, and that the conductive gate fill material 244 is in contact with the sides of the dielectric gate plug.
Regarding claim 12, Paul shows a memory (see, e.g., par.0008/ll.1-2) coupled to the board (see, e.g., par.0064/ll.11-14).
Regarding claim 14, Paul shows that the component (see, e.g., par.0064/ll.11-14) may be a packaged integrated circuit die (see, e.g., par.0064/ll.1-10).
Regarding claim 15, Paul (see, e.g., par.0064/ll.11-18) shows that the component may be a processor.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Paul/Smith/Lim/Chiang in view of Guha (US 2020/0091348).
Regarding claim 13, Paul/Smith/Lim/Chiang shows most aspects of the instant invention (see paragraphs 23-31 above). Paul further shows that the component (see, e.g., par.0064/ll.11-18) may be used as part of advanced computer products having a display, a keyboard, or other input device, but fails to specify that there is a communication chip coupled to the board (see, e.g., par.0064/ll.11-14). Guha, in the same field of endeavor, teaches that having a communication chip coupled to a board may enable wireless communications for the transfer of data to and from a computing device (see, e.g., Guha: fig. 10 and par.0152/ll.1-3).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the communication chip of Guha in the computing device of Paul/Smith/Lim/Chiang to facilitate the transfer of data to and from the computing device of Paul/Smith/Lim/Chiang.
Response to Arguments
Applicant has presented no arguments or amendments regarding the objections to the drawings set forth in the previous Office action mailed on 02/17/2026. Accordingly, the objections to the drawings put forth in the previous Office action are maintained.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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