Attorney Docket Number: AD3241-US 111548-262238
Filing Date: 06/14/2021
Claimed Priority Date: none
Inventors: Guler et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 09/17/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection mailed on 07/25/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 09/17/2025 has been entered.
Amendment Status
The RCE submission filed on 09/17/2025, as an amendment in reply to the Office action mailed on 07/25/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20, with claims 5 and 11-20 remaining withdrawn from consideration.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “112” has been used to designate both a gate electrode and a conductive trench contact structure. See figure 1A, wherein both the left and right portions of the figure have the same character 112, which appears to refer to different structures in device 100.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith (US 2019/0172828).
Regarding claim 1, Smith (see, e.g., fig. 4) shows all aspects of the instant invention, including an integrated circuit structure 400 comprising:
a first sub-fin structure 11 over a first stack of nanowires 23;
a second sub-fin structure 11 over a second stack of nanowires 22;
a first gate electrode 812 around the first stack of nanowires;
a second gate electrode 812 around the second stack of nanowires;
a conductive trench contact structure 1312 between the first gate electrode and the second gate electrode; and
a conductive via bar 13 on the conductive trench contact structure
wherein:
an interface 14 between the conductive via bar 13 and the conductive trench contact structure 1312 is laterally between the first stack of nanowires 23 and the second stack of nanowires 22; and
the conductive via bar 13 has a backside surface co-planar with a backside surface of the first and second sub-fin structures
Regarding claim 2, Smith (see, e.g., fig. 4) shows that the conductive via bar 13 is laterally spaced apart from the first sub-fin 11 by a first distance and is laterally spaced apart from the second sub-fin 11 by a second distance, the second distance the same as the first distance.
Regarding claim 3, Smith (see, e.g., fig. 4) shows that a gate dielectric layer 612 separates the first gate electrode 812 from the first stack of nanowires 23, and separates the second gate electrode 812 from the second stack of nanowires 22.
Regarding claim 4, Smith (see, e.g., pars.0057/ll.4-5 and 0060/ll.1-2) shows that the first 11 and second 11 sub-fin structures are semiconductor sub-fin structures.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Lilak (US 2020/0294998).
Regarding claim 6, Smith shows most aspects of the instant invention (see paragraph 8 above). Smith (see, e.g., pars.0003/ll.1-2 and 0138/ll.1-5) further discloses that semiconductor devices may be used in computing devices and that the device of Smith can include further modifications within the scope of the device, but fails to specify that these modifications may include a computing device comprising a board and a component coupled to the board.
Lilak, possessing a similar integrated circuit structure to Smith, teaches that having a computing device, shown to house a board, and having a component (such as a processor) containing an integrated circuit structure may facilitate the processing of electronic data from registers and/or memory and the transformation of said electronic data into other electronic data that may also be stored in registers and/or memory (see, e.g., Lilak: fig. 10 and pars.0065 and 0067/ll.7-8).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Smith to include the computing device and included component of Lilak, so as to facilitate the processing, storing, and transformation of data from the device of Smith.
Regarding claim 7, Lilak (see, e.g., fig. 10) shows a memory ROM coupled to the board 1002.
Regarding claim 8, Lilak (see, e.g., fig. 10) shows a communication chip 1006 coupled to the board 1002.
Regarding claim 9, Lilak (see, e.g., par.0065/ll.1-6) shows that the component is a packaged integrated circuit die.
Regarding claim 10, Lilak (see, e.g., pars.0063/ll.1-16, 0065/ll.1-6, and 0066/ll.1-6) shows that the component may be selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Response to Arguments
The applicant argues:
The claims recite the limitations of a conductive trench contact structure and an interface between a conductive via bar and a conductive trench contact structure being laterally between a first stack of nanowires and a second stack of nanowires. Smith fails to disclose these limitations because 1312 in figure 4 denotes a layer of a gate electrode and not a conductive trench contact structure. Furthermore, Smith fails to disclose an interface between elements 13 and 1312 (which the examiner cites as a “conductive via bar” and a “conductive trench contact structure”), wherein such an interface is laterally between a first stack of nanowires and a second stack of nanowires.
The examiner responds:
Par.0069 in Smith teaches that 1312 is a “third structure” including any suitable conductive material. Furthermore, fig. 4 of Smith shows that “third structure” 1312 contacts trench structures 12. Therefore, 1312 is a conductive trench contact structure. Additionally, fig. 4 of Smith shows that element 14 intervenes to contact both conductive via bar 13 and conductive trench contact structure 1312. One of ordinary skill in the art could appreciate that such a connection feature constitutes an “interface” between the conductive via bar and the conductive trench contact structure. Furthermore, fig. 4 of Smith shows that an orthogonal projection of element 14 on element 2030 falls laterally between orthogonal projections of first and second stack of nanowires 23, 22 on the same feature. Accordingly, Smith shows that an interface between the conductive via bar and the conductive trench contact structure is laterally between the first stack of nanowires and the second stack of nanowires.
All other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814