Attorney Docket Number: AD3241-US 111548-262238
Filing Date: 06/14/2021
Claimed Priority Date: none
Inventors: Guler et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 04/16/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 04/16/2026 in reply to the previous Office action mailed on 01/23/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20, with claims 5 and 11-20 remaining withdrawn from consideration.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “112” has been used to designate both a gate electrode and a conductive trench contact structure. See figure 1A, wherein both the left and right portions of the figure have the same character 112, which appears to refer to different structures in device 100.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu (US 2023/0307515).
Regarding claim 1, Hsu (see, e.g., figs. 13D, 20B, and 21B, par.0045/ll.12-14, and claims 6-7) shows all aspects of the instant invention, including an integrated circuit structure 200 comprising:
a first sub-fin structure (leftmost 204 or 276) over a first stack of nanowires (leftmost 215/215’);
a second sub-fin structure (rightmost 204 or 276) over a second stack of nanowires (rightmost 215/215’);
a first gate electrode (leftmost 350) around the first stack of nanowires;
a second gate electrode (rightmost 350) around the second stack of nanowires;
a conductive trench contact structure 261 (see, e.g., figs. 19B, 20B, and par.0049/ll.13-18) between the first gate electrode and the second gate electrode;
a conductive via bar 282 on the conductive trench contact structure, wherein an interface between the conductive via bar and the conductive trench contact structure is laterally between the first stack of nanowires and the second stack of nanowires such that the interface is horizontally overlapping with the first stack of nanowires and the second stack of nanowires along a horizontal axis (e.g., an axis corresponding to X = -Z), the conductive via bar having a backside surface co-planar with a backside surface of the first and second sub-fin structures
It is additionally remarked that the written description and claims do not place restrictions or distinctions on what planes may constitute a “horizontal axis”. Accordingly, a horizontal axis and horizontal overlap may not necessarily be taken as parallel to any distinct feature of Hsu’s device. See also Fig. 1A of the instant application.
Regarding claim 2, Hsu (see, e.g., figs. 20B, and 21B, par.0045/ll.12-14, and claims 6-7) shows that the conductive via bar 282 is laterally separated from the first sub-fin (e.g., leftmost 276) by a first distance (thickness of 285/289) and is laterally spaced apart from the second sub-fin (e.g., rightmost 276) by a second distance (thickness of 285/289), the second distance the same as the first distance.
Regarding claim 3, Hsu (see, e.g., figs. 13D, 20B, and 21B, pars.0036/ll.7-8 and 0045/ll.12-14, and claims 6-7) shows that a gate dielectric layer 349 separates the first gate electrode (leftmost 350) from the first stack of nanowires (leftmost 215/215’), and separates the second gate electrode (rightmost 350) from the second stack of nanowires (rightmost 215/215’).
Regarding claim 4, Hsu (see, e.g., fig. 20D, pars.0045/ll.12-14 and 0055, and claims 6-7) shows that the first (leftmost 204) and second (rightmost 204) sub-fin structures are semiconductor sub-fin structures.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Lilak (US 2020/0294998).
Regarding claim 6, Hsu shows most aspects of the instant invention (see paragraphs 7-8 above, wherein the integrated structure and its composition are considered to be repeated here). Hsu (see, e.g., pars.0052/ll.18-20 and 0062) further discloses that Hsu’s integrated circuit structure may be readily incorporated into existing manufacturing processes and that the device of Hsu can include further modifications within and without departing from the scope of the device. Hsu, however, fails to specify that these modifications may include a computing device comprising a board and a component coupled to the board.
Lilak, possessing a similar integrated circuit structure to Hsu and the claimed invention, teaches that having a computing device, shown to house a board, and having a component (such as a processor) containing an integrated circuit structure may facilitate the processing of electronic data from registers and/or memory and the transformation of said electronic data into other electronic data that may also be stored in registers and/or memory (see, e.g., Lilak: fig. 10 and pars.0065 and 0067/ll.7-8).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Hsu to include the computing device and included component of Lilak, so as to facilitate the processing, storing, and transformation of data from and to expand the external applications of the device of Hsu.
Regarding claim 7, Lilak (see, e.g., fig. 10) shows a memory ROM coupled to the board 1002.
Regarding claim 8, Lilak (see, e.g., fig. 10) shows a communication chip 1006 coupled to the board 1002.
Regarding claim 9, Lilak (see, e.g., par.0065/ll.1-6) shows that the component is a packaged integrated circuit die.
Regarding claim 10, Lilak (see, e.g., pars.0063/ll.1-16, 0065/ll.1-6, and 0066/ll.1-6) shows that the component may be selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Response to Arguments
Applicant has not provided any arguments regarding the objections to the drawings set forth in the previous Office action mailed on 01/23/2026. Accordingly, the objections to the drawings put forth in the previous Office action are maintained.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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