CTNF 17/347,015 CTNF 99314 Attorney’s Docket Number: AD4238-US 111548-262276 Filing Date: 6/14/2021 Claimed Priority Date: none Inventors: Guler et al. Examiner: Shamita S. Hanumasagar DETAILED ACTION This Office action responds to the amendment filed on 05/29/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis ( i.e. , changing from AIA to pre-AIA) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 07-42-04 A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection mailed on 04/03/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 05/29/2026 has been entered. Amendment Status The RCE submission filed on 05/29/2026 as an amendment in reply to the Office action mailed on 04/03/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20, wherein claims 5 and 11-20 remain withdrawn from consideration. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 112 ” has been used to designate both gate electrodes and dielectric spacers in figure 1. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 108 ” has been used to designate both a stack of nanowires and gate electrodes in figure 2B. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 103 ” has been used to designate both liners in figure 1 and STI structures in figures 3A-3B. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 106 ” has been used to designate both STI structures in figure 1 and liners in figures 3A-3B. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 416 ” has been used to designate both a protective cap and cavity spacers in figure 4J. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 580 ” has been used to designate both an interface and sub-fin regions in figure 5. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4 and 6-10 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Cappellani (US 2013/0313513) . Regarding claims 1 and 6, Cappellani (see, e.g. , figs. 1A, 1B, 1B’, and 6, par.0025, and paragraph 37 below) shows all aspects of the instant invention, including a computing device 600 comprising a board 602 and a component 604 coupled to the board, the component including an integrated circuit structure 100’/100 comprising: a first insulator sub-fin structure 130’ over a first stack of nanowires portion of 106’ (see paragraph 37 below and, e.g. , par.0025) a second insulator sub-fin structure 130 over a second stack of nanowires portion of 106 (see paragraph 37 below and, e.g. , par.0025); a first gate electrode 108’ around the first stack of nanowires; and a second gate electrode 108 around the second stack of nanowires; wherein: the second stack of nanowires portion of 106 has a greater number of nanowires than the first stack of nanowires portion of 106’ ; the second insulator sub-fin structure 130 has a vertical thickness less than a vertical thickness of the first insulator sub-fin structure 130’ ; the first gate electrode 108’ [is] vertically intervening between and in contact with the first stack of nanowires and the first insulator sub-fin structure along a first vertical axis 105’ through the first stack of nanowires and the first insulator sub-fin structure such that the first insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the first stack of nanowires (see, e.g. , pars.0025 and 0031/ll.10 and paragraph 37 below); the second gate electrode 108 [is] vertically intervening between and in contact with the second stack of nanowires and the second insulator sub-fin structure along a second vertical axis 105 through the second stack of nanowires and the second insulator sub-fin structure such that the second insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the second stack of nanowires (see, e.g. , pars.0025 and 0031/ll.10 and paragraph 37 below) Regarding claim 2, Cappellani (see, e.g. , par.0032/ll.5-6) shows that a gate dielectric layer separates the first gate electrode from the first stack of nanowires and separates the second gate electrode from the second stack of nanowires. Regarding claim 3, Cappellani shows epitaxial source or drain structures 110/112 at ends of the first and second stacks of nanowires. Regarding claim 4, Cappellani (see, e.g. , par.0054/ll.4-8) shows that the epitaxial source or drain structures are non-discrete epitaxial source or drain structures. Regarding claim 7, Cappellani shows a memory ROM coupled to the board. Regarding claim 8, Cappellani shows a communication chip 606 coupled to the board. Regarding claim 9, Cappellani (see, e.g. , par.0061) shows that a battery may be coupled to the board. Regarding claim 10, Cappellani (see, e.g. , par.0063/ll.1-6) shows that the component is a packaged integrated circuit die . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cappellani in view of Lee (US 2020/0098879) and Lilak (US 2020/0294998) . Regarding claims 1 and 6, Cappellani (see, e.g. , figs. 1A, 1B, 1B’, and 6 and par.0025) shows all aspects of the instant invention, including a computing device 600 comprising a board 602 and a component 604 coupled to the board, the component including an integrated circuit structure 100’/100 comprising: a first insulator sub-fin structure 130’ over a first stack of nanowires portion of 106’ (see paragraph 37 below and, e.g. , par.0025) a second insulator sub-fin structure 130 over a second stack of nanowires portion of 106 (see paragraph 37 below and, e.g. , par.0025); a first gate electrode 108’ around the first stack of nanowires; and a second gate electrode 108 around the second stack of nanowires; wherein: the second stack of nanowires portion of 106 has a greater number of nanowires than the first stack of nanowires portion of 106’ ; the second insulator sub-fin structure 130 has a vertical thickness less than a vertical thickness of the first insulator sub-fin structure 130’ ; the first gate electrode 108’ [is] vertically intervening between and in contact with the first stack of nanowires and the first insulator sub-fin structure along a first vertical axis 105’ through the first stack of nanowires and the first insulator sub-fin structure such that the first insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the first stack of nanowires (see, e.g. , pars.0025 and 0031/ll.10 and paragraph 37 below); the second gate electrode 108 [is] vertically intervening between and in contact with the second stack of nanowires and the second insulator sub-fin structure along a second vertical axis 105 through the second stack of nanowires and the second insulator sub-fin structure such that the second insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the second stack of nanowires (see, e.g. , pars.0025 and 0031/ll.10 and paragraph 37 below) Cappellani teaches that the first gate electrode is vertically intervening between and in contact with the first stack of nanowires and the first insulator sub-fin structure along a first vertical axis through the first stack of nanowires and the first insulator sub-fin structure, specifically such that the first insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the first stack of nanowires, and that the second gate electrode is vertically intervening between and in contact with the second stack of nanowires and the second insulator sub-fin structure along a second vertical axis through the second stack of nanowires and the second insulator sub-fin structure, specifically such that the second insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the second stack of nanowires (see paragraph 37 below and, e.g. , pars.0025 and 0031/ll.10). Furthermore, Cappellani is not the only evidence that it is known in the art that first and second gate electrodes may be vertically intervening between and in contact with respective first or second stacks of nanowires and first or second (insulator) sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second (insulator) sub-fin structures such that the first or second (insulator) sub-fin is vertically spaced apart from and does not contact any of the nanowires of the respective first or second stack of nanowires. Lee, in the same field of endeavor, teaches a device showing both (1) a first gate electrode 170 vertically intervening between and in contact with a respective first 160 stack of nanowires and a first 106P sub-fin structure along a respective first vertical axis through the first stack of nanowires and first sub-fin such that the first sub-fin structure is vertically spaced apart from and does not contact any of the nanowires of the respective first stack of nanowires and (2) a second gate electrode 130 not vertically intervening between, albeit in contact, with a respective second 120 stack of nanowires and a second 104P sub-fin structure along a respective second vertical axis through the second stack of nanowires and second sub-fin such that the second sub-fin structure is not vertically spaced apart from and contacts the nanowires of the respective first stack of nanowires (see, e.g. , Lee: fig. 3I-3J). Furthermore, Lilak, also in the same field of endeavor, additionally shows a device having first 120 and second 120 gate electrodes vertically intervening between and in contact with first 116 or second 116 stacks of nanowires and first 136 and second 136 insulator sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the respective first or second stack of nanowires (see, e.g. , Lilak: fig. 9A). Cappellani, Lilak, and especially Lee are evidence showing that one of ordinary skill in the art would appreciate that first and second gate electrodes being vertically intervening between and in contact with respective first or second stacks of nanowires and first or second sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second sub-fin structures such that the first or second sub-fins are vertically spaced apart from and do not contact any of the nanowires of the respective first or second stack of nanowires would be equivalent to another first and second gate electrode, first and second nanowire stack, and first and second sub-fin structure disposition and arrangement, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Cappellani. That is, the first and second gate electrode, nanowire stack, and sub-fin dispositions of all of Cappellani, Lee, and Lilak would yield the predictable result of providing appropriately proportioned and positioned gate electrode, nanowire stack, and sub-fin structure arrangements capable of supporting the effective functioning of an integrated circuit structure while facilitating electrical and mechanical interconnections with various other elements in a semiconductor device. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have first and second gate electrodes being vertically intervening between and in contact with respective first or second stacks of nanowires and first or second sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second sub-fin structures such that the first or second sub-fin are vertically spaced apart from and do not contact any of the nanowires of the respective first or second stack of nanowires, as already taught by Cappellani, Lee, and Lilak, or first and second gate electrodes, nanowire stacks, and sub-fin structures of an alternative disposition and/or arrangement, as taught by Lee, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing appropriately proportioned and positioned gate electrode, nanowire stack, and sub-fin structure arrangements capable of supporting the effective functioning of an integrated circuit structure while facilitating electrical and mechanical interconnections with various other elements in a semiconductor device. KSR International Co. v. Teleflex Inc. , 550 U.S.-- ,82 USPQ2d 1385 (2007). Regarding claim 2, Cappellani (see, e.g. , par.0032/ll.5-6) shows that a gate dielectric layer separates the first gate electrode from the first stack of nanowires, and separates the second gate electrode from the second stack of nanowires. Regarding claim 3, Cappellani shows epitaxial source or drain structures 110/112 at ends of the first and second stacks of nanowires. Regarding claim 4, Cappellani (see, e.g. , par.0054/ll.4-8) shows that the epitaxial source or drain structures are non-discrete epitaxial source or drain structures. Regarding claim 7, Cappellani shows a memory ROM coupled to the board. Regarding claim 8, Cappellani shows a communication chip 606 coupled to the board. Regarding claim 9, Cappellani (see, e.g. , par.0061) shows that a battery may be coupled to the board. Regarding claim 10, Cappellani (see, e.g. , par.0063/ll.1-6) shows that the component is a packaged integrated circuit die. Response to Arguments The applicant argues: Claims 1 and 6 recite the limitation of a first and second gate electrode being vertically intervening between and in contact with respective first and second stack of nanowires and first and second insulator sub-fin structures along a respective first or second vertical axis through their respective first and second stack of nanowires and first and second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the respective first or second stack of nanowires. Cappellani fails to disclose this limitation as in figures 1B-1B’ Cappellani shows the bottom nanowire of the first and second stacks of nanowires in contact with their respective insulator sub-fin structure. The examiner responds: Par.0025 in Cappellani asserts that Cappellani’s first and second nanowire sets may contain more nanowires than are shown in the figures, so long as the total counts of the first and second nanowire sets differ by one or more. In this manner, the nanowire stacks in Cappellani’s device ( i.e. , the nanowires comprised in the nanowire stacks) may be defined such that the first and second gate electrodes are vertically intervening between and in contact with their respective first or second stacks of nanowires and first or second insulator sub-fin structures along a respective first or second vertical axis through their respective first or second stack of nanowires and first or second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact any of the nanowires of the respective first or second stack of nanowires while maintaining the asserted differing nanowire counts integral to Cappellani’s device. Applicant has provided no arguments or amendments regarding the objections to the drawings put forth in the previous Office action mailed on 10/17/2025. Accordingly, the objections to the drawings put forth in the previous Office action are maintained. Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new and withstanding grounds of rejection. Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300 . The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Shamita S. Hanumasagar/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 2 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 3 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 4 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 5 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 6 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 7 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 8 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 9 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 10 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 11 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 12 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 13 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 14 Art Unit: 2814 Application/Control Number: 17/347,015 (Non-Final Rejection) Page 15 Art Unit: 2814
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