Attorney’s Docket Number: AD4238-US 111548-262276
Filing Date: 6/14/2021
Claimed Priority Date: none
Inventors: Guler et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 01/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 01/15/2026 in reply to the previous Office action mailed on 10/17/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20, wherein claims 5 and 11-20 remain withdrawn from consideration.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “112” has been used to designate both gate electrodes and dielectric spacers in figure 1.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “108” has been used to designate both a stack of nanowires and gate electrodes in figure 2B.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “103” has been used to designate both liners in figure 1 and STI structures in figures 3A-3B.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “106” has been used to designate both STI structures in figure 1 and liners in figures 3A-3B.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “416” has been used to designate both a protective cap and cavity spacers in figure 4J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “580” has been used to designate both an interface and sub-fin regions in figure 5.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cappellani (US 2013/0313513).
Regarding claims 1 and 6, Cappellani (see, e.g., figs. 1A, 1B, 1B’, and 6 and par.0025) shows all aspects of the instant invention, including a computing device 600 comprising a board 602 and a component 604 coupled to the board, the component including an integrated circuit structure 100’/100 comprising:
a first insulator sub-fin structure 130’ over a first stack of nanowires 106’ (see, e.g., par.0025)
a second insulator sub-fin structure 130 over a second stack of nanowires 106 (see, e.g., par.0025)
wherein:
the second stack of nanowires 106 has a greater number of nanowires than the first stack of nanowires 106’;
the second insulator sub-fin structure 130 has a vertical thickness less than a vertical thickness of the first insulator sub-fin structure 130’;
a first gate electrode 108’ is around the first stack of nanowires;
the first gate electrode [is] vertically intervening between and in contact with the first stack of nanowires and the first insulator sub-fin structure along a first vertical axis 105’ through the first stack of nanowires and the first insulator sub-fin structure such that the first insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the first stack of nanowires (see, e.g., pars.0025 and 0031/ll.10);
a second gate electrode 108 is around the second stack of nanowires; and
the second gate electrode [is] vertically intervening between and in contact with the second stack of nanowires and the second insulator sub-fin structure along a second vertical axis 105 through the second stack of nanowires and the second insulator sub-fin structure such that the second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the second stack of nanowires (see, e.g., pars.0025 and 0031/ll.10)
Regarding claim 2, Cappellani (see, e.g., par.0032/ll.5-6) shows that a gate dielectric layer may separate the first gate electrode from the first stack of nanowires and separate the second gate electrode from the second stack of nanowires.
Regarding claim 3, Cappellani shows epitaxial source or drain regions 110/112 at ends of the first and second stacks of nanowires.
Regarding claim 4, Cappellani (see, e.g., par.0054/ll.4-8) shows that the epitaxial source or drain structures may be non-discrete.
Regarding claim 7, Cappellani shows a memory ROM coupled to the board.
Regarding claim 8, Cappellani shows a communication chip 606 coupled to the board.
Regarding claim 9, Cappellani (see, e.g., par.0061) shows that a battery may be coupled to the board.
Regarding claim 10, Cappellani (see, e.g., par.0063/ll.1-6) shows that the component is a packaged integrated circuit die.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cappellani in view of Lee (US 2020/0098879) and Lilak (US 2020/0294998).
Regarding claims 1 and 6, Cappellani (see, e.g., figs. 1A, 1B, 1B’, and 6 and par.0025) shows all aspects of the instant invention, including a computing device 600 comprising a board 602 and a component 604 coupled to the board, the component including an integrated circuit structure 100’/100 comprising:
a first insulator sub-fin structure 130’ over a first stack of nanowires 106’ (see, e.g., par.0025)
a second insulator sub-fin structure 130 over a second stack of nanowires 106 (see, e.g., par.0025)
wherein:
the second stack of nanowires 106 has a greater number of nanowires than the first stack of nanowires 106’;
the second insulator sub-fin structure 130 has a vertical thickness less than a vertical thickness of the first insulator sub-fin structure 130’;
a first gate electrode 108’ is around the first stack of nanowires;
the first gate electrode [is] vertically intervening between and in contact with the first stack of nanowires and the first insulator sub-fin structure along a first vertical axis 105’ through the first stack of nanowires and the first insulator sub-fin structure such that the first insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the first stack of nanowires see, e.g., pars.0025 and 0031/ll.10);
a second gate electrode 108 is around the second stack of nanowires; and
the second gate electrode [is] vertically intervening between and in contact with the second stack of nanowires and the second insulator sub-fin structure along a second vertical axis 105 through the second stack of nanowires and the second insulator sub-fin structure such that the second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the second stack of nanowires (see, e.g., pars.0025 and 0031/ll.10)
Cappellani teaches that the first gate electrode [is] vertically intervening between and in contact with the first stack of nanowires and the first insulator sub-fin structure along a first vertical axis through the first stack of nanowires and the first insulator sub-fin structure, specifically such that the first insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the first stack of nanowires, and that the second gate electrode [is] vertically intervening between and in contact with the second stack of nanowires and the second insulator sub-fin structure along a second vertical axis 105 through the second stack of nanowires and the second insulator sub-fin structure, specifically such that the second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the second stack of nanowires (see, e.g., pars.0025 and 0031/ll.10). Furthermore, Cappellani is not the only evidence that it is known in the art that first and second gate electrodes may be vertically intervening between and in contact with respective first or second stacks of nanowires and first or second (insulator) sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second (insulator) sub-fin structures such that the first or second (insulator) sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires. Lee, in the same field of endeavor, teaches a device showing first 130 and second 170 gate electrodes vertically intervening between and in contact with respective first 120 or second 160 stacks of nanowires and first 104P or second 106P sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second sub-fin structures such that the first or second sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires (see, e.g., Lee: fig. 3I). Lilak, also in the same field of endeavor, further shows a device having first 120 and second 120 gate electrodes vertically intervening between and in contact with first 116 or second 116 stacks of nanowires and first 136 and second 136 insulator sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires (see, e.g., Lilak: fig. 9A).
Cappellani, Lee, and Lilak are evidence showing that one of ordinary skill in the art would appreciate that first and second gate electrodes being vertically intervening between and in contact with respective first or second stacks of nanowires and first or second insulator sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires would be equivalent to another first and second gate electrode, first and second nanowire stack, and first and second insulator sub-fin structure disposition and arrangement, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Cappellani. That is, the first and second gate electrode, nanowire stack, and sub-fin dispositions of all of Cappellani, Lee, and Lilak would yield the predictable result of providing appropriately proportioned gate electrode, nanowire stack, and sub-fin structure arrangements suitable for interconnection with other elements in a semiconductor device and the effective functioning of an integrated circuit structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have first and second gate electrodes being vertically intervening between and in contact with respective first or second stacks of nanowires and first or second insulator sub-fin structures along a respective first or second vertical axis through the respective first or second stack of nanowires and first or second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires, as already taught by Cappellani, Lee, and Lilak, or first and second gate electrodes, nanowire stacks, and sub-fin structures of an alternative disposition and/or arrangement, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a conductive pathway between layers of an integrated circuit structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Regarding claim 2, Cappellani (see, e.g., par.0032/ll.5-6) shows that a gate dielectric layer may separate the first gate electrode from the first stack of nanowires and separate the second gate electrode from the second stack of nanowires.
Regarding claim 3, Cappellani shows epitaxial source or drain regions 110/112 at ends of the first and second stacks of nanowires.
Regarding claim 4, Cappellani (see, e.g., par.0054/ll.4-8) shows that the epitaxial source or drain structures may be non-discrete.
Regarding claim 7, Cappellani shows a memory ROM coupled to the board.
Regarding claim 8, Cappellani shows a communication chip 606 coupled to the board.
Regarding claim 9, Cappellani (see, e.g., par.0061) shows that a battery may be coupled to the board.
Regarding claim 10, Cappellani (see, e.g., par.0063/ll.1-6) shows that the component is a packaged integrated circuit die.
Response to Arguments
The applicant argues:
Claims 1 and 6 recite the limitation of a first and second gate electrode being vertically intervening between and in contact with respective first and second stack of nanowires and first and second insulator sub-fin structures along a respective first or second vertical axis through their respective first and second stack of nanowires and first and second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires. Cappellani fails to disclose this limitation as in figures 1B-1B’ Cappellani shows the bottom nanowire of the first and second stacks of nanowires in contact with their respective insulator sub-fin structure.
The examiner responds:
Par.0025 in Cappellani asserts that Cappellani’s first and second stacks of nanowires may contain more nanowires than are shown in the figures, so long as the counts of the first and second stacks of nanowires differ by one or more. In this manner, the nanowire stacks may be defined such that the first and second gate electrodes are vertically intervening between and in contact with their respective first or second stacks of nanowires and first or second insulator sub-fin structures along a respective first or second vertical axis through their respective first or second stack of nanowires and first or second insulator sub-fin structures such that the first or second insulator sub-fin is vertically spaced apart from and does not contact the nanowires of the respective first or second stack of nanowires while maintaining the asserted differing nanowire counts integral to Cappellani’s device.
Applicant has provided no arguments or amendments regarding the objections to the drawings put forth in the previous Office action mailed on 10/17/2025. Accordingly, the objections to the drawings put forth in the previous Office action are maintained. Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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