Detailed Action
This office action is in response to the request for continued examination filed on November 5th, 2025. Claims 1-5, 7-14, 17-20, 47-53, and 56-63 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 5th, 2025, has been entered.
Response to Arguments
Applicant's arguments filed November 5th, 2025, have been fully considered but they are not persuasive.
Applicant argues (pg. 16, “Remarks”) that the combination of Kim and Lee would place SiN above and below the sacrificial SiN/SiON thereby decreasing or elimination the etch selectivity.
Examiner notes that the use of Lee’s second tiers provide the proper etch selectivity in a device using polysilicon as a sacrificial material. The rejections for Claim 1, 47, and 48 have been updated to clarify the combination of the features of Kim and Lee.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pg. 16, “Remarks”) the disclosure of Yoo is a general explanation of differing materials and does not provide any purposeful use or configuration of silicon nitride variants. The varied nitrogen contents of Yoo are clearly not an equivalent with respect to etch selectivity and in combination with Kim and Lee does not render obvious the recited configuration of materials.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Yoo establishes that the use of different structures of silicon nitride are known in the art and commonly used in semiconductor devices. Yoo does not make note of any results that are not predictable and, as a result, one of ordinary skill in the art would find it obvious to substitute the material of Yoo as discussed in the rejections of Claim 1, 47, and 48 below.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., equivalent etching selectivity of silicon nitride variants) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In this instance, Yoo need not teach that the silicon nitride variants have or do not have the same etching selectively. Regardless, Yoo notes that variants of silicon nitride ([0046]) may be used in a semiconductor device wherein silicon oxide layers and silicon nitride layers are disposed adjacent to each other and required to maintain etch selectivity ([0051]) and thus has some understanding of etch selectivity requirements amongst the variants.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pg. 17, “Remarks”) that Lee specifies O-N-O or O-N-O-N configurations and does not teach the amendments of Claims 1, 47, and 48 requiring a bilayer configuration.
However, as seen below, the amendments provided by applicant result in indefinite claims and have been rejected under 35 U.S.C. 112(b). As a result of having to interpret indefinite claims, the amended Claims 1, 47, and 48 are still rejected using the combination of Kim and Lee below.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pgs. 17-18, “Remarks”) that there is no motivation to use Tang as suggested by the examiner for Claims 10-14 and 53.
However, as seen below, Claims 10-14 and 53 are rejected utilizing Tsai.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7-14, 17-20, 47-53, and 56-63 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the lowest second tier and the next-lowest second tier independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier and the next-lowest second tier comprising (b) or (c)" in lines 20-23. While the transitional phrases “consisting of” and “comprising” are well-defined, see MPEP § 2111.03 I. and II., it is unclear as to what elements or steps may or may not be excluded from applicant’s features (b) and (c) since both transitional phrases apply to applicant’s features. For the purpose of examination, features (b) and (c) will be interpreted as following the transitional phrase “comprising” and therefore not excluding additional, unrecited elements.
Claim 2 recites the limitation "one of the lowest second tier and the next-lowest second tier comprise the (a)" in lines 1-2. While the transitional phrases “consisting of” and “comprising” are well-defined, see MPEP § 2111.03 I. and II., it is unclear as to what elements or steps may or may not be excluded from applicant’s feature (a) since both transitional phrases apply to applicant’s feature. See 112(b) rejection for Claim 1 above. For the purpose of examination, feature (a) will be interpreted as following the transitional phrase “comprising” and therefore not excluding additional, unrecited elements.
Claim 47 recites the limitation "the lowest second tier and the next-lowest second tier independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier and the next-lowest second tier comprising (b) or (c)" in lines 17-20. While the transitional phrases “consisting of” and “comprising” are well-defined, see MPEP § 2111.03 I. and II., it is unclear as to what elements or steps may or may not be excluded from applicant’s features (b) and (c) since both transitional phrases apply to applicant’s features. For the purpose of examination, features (b) and (c) will be interpreted as following the transitional phrase “comprising” and therefore not excluding additional, unrecited elements.
Claim 48 recites the limitation "the lowest second tier and the next-lowest second tier independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier and the next-lowest second tier comprising (b) or (c)" in lines 20-23. While the transitional phrases “consisting of” and “comprising” are well-defined, see MPEP § 2111.03 I. and II., it is unclear as to what elements or steps may or may not be excluded from applicant’s features (b) and (c) since both transitional phrases apply to applicant’s features. For the purpose of examination, features (b) and (c) will be interpreted as following the transitional phrase “comprising” and therefore not excluding additional, unrecited elements.
Claim 50 recites the limitation "one of the lowest second tier and the next-lowest second tier comprise the (a)" in lines 2-3. While the transitional phrases “consisting of” and “comprising” are well-defined, see MPEP § 2111.03 I. and II., it is unclear as to what elements or steps may or may not be excluded from applicant’s feature (a) since both transitional phrases apply to applicant’s feature. See 112(b) rejection for Claim 48 above. For the purpose of examination, feature (a) will be interpreted as following the transitional phrase “comprising” and therefore not excluding additional, unrecited elements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 17-20, 47-52, and 56-63 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2021/0305276 A1; hereinafter Kim), Yu et al. (U.S. 2018/0122906 A1; hereinafter Yu), Yoo et al. (2018/0315758 A1; hereinafter Yoo), Lee (2018/0138195 A1; hereinafter Lee), and Son et al. (U.S. 2020/0203370 A1; hereinafter Son).
Regarding Claim 1, Kim (figs. 3 and 6-11) teaches a method used in forming a memory array ([0019]) comprising strings of memory cells ([0021]), comprising:
forming a conductor tier ([0077], LSL) comprising conductor material ([0077], polysilicon) on a substrate ([0076]), the conductor material (LSL) having a conductively doped semiconductive material region ([0031], LSL may be n-type doped poly-silicon) [];
forming a lower portion ([0077], bottommost IL1, IL3, LHL, IL4) of a stack ([0079], MO, IL3, LHL, IL4, see fig. 7) that will comprise vertically-alternating first tiers ([0079], HL) and second tiers ([0079], IL1) above the conductor tier (LSL), the stack (MO, IL3, LHL, IL4) comprising laterally-spaced memory-block regions ([0051], regions between separation structures SPS in CAR region, see fig. 3), material of the first tiers (HL) being of different composition ([0080], HL may be silicon nitride, IL1 may be silicon oxide) from material of the second tiers (IL1), the lower portion consisting of:
a lowest of the second tiers (IL3) directly on the conductor material (LSL);
a next-lowest of the second tiers (IL4) directly above the lowest second tier (IL3);
a lowest of the first tiers (LHL) comprising sacrificial material ([0077]) vertically between the lowest second tier (IL3) and the next-lowest second tier (IL4);
a conductive material tier ([0078], USL) directly on the next lowest of the second tiers;
an uppermost second tier (bottommost IL1, see fig. 7) directly on the conductive material tier (USL);
forming vertically-alternating first tiers (HL) and second tiers (IL1) of an upper portion (MO) of the stack (MO, IL3, LHL, IL4) above and in direct physical contact with the uppermost second tier (bottommost IL1) of the lower portion (bottommost IL1, IL3, LHL, IL4), and
forming channel-material strings ([0085], VS) that extend through the first tiers (HL) and the second tiers (IL1) in the upper portion (MO) to the lowest first tier (LHL) in the lower portion (bottommost IL1, IL3, LHL, IL4);
forming horizontally-elongated trenches ([0095]-[0096], cutting holes later filled with SPS) through the upper portion (MO) and that extend through the next-lowest second tier (IL4) to the sacrificial material of the lowest first tier (LHL), the horizontally-elongated trenches (cutting holes filled with SPS) individually being between immediately-laterally-adjacent of the memory-block regions (regions between adjacent SPS);
through the horizontally-elongated trenches (cutting holes), replacing the sacrificial material in the lowest first tier (LHL) with conductive material ([0096], SSL) that directly electrically couples together ([0097]) channel material of the channel-material strings (VS) and the conductor material of the conductor tier (LSL);
removing only some ([0098], bottommost IL1, IL3, LHL, IL4 in CNR is not removed, see fig. 11) of the at least one of the (a), the (b), and the (c) from each of the lowest second tier (IL3) and the next-lowest second tier (IL4) before the replacing that forms the conductive material (SSL),
a remaining portion (bottommost IL1, IL3, LHL, IL4 in CNR) of the at least one of the (a), the (b), and the (c) in the next-lowest second tier (IL4) remaining directly above a remaining portion of the at least one of the (a), the (b), and the (c) in the lowest second tier (IL3) laterally outside of the memory-block regions (CNR is outside of CAR, see fig. 3) during and after the replacing (see fig. 11); and
forming an isolation material ([0095], SPS) within the horizontally-elongated trenches (cutting holes) and in direct physical contact with an upper surface of the conductor tier (LSL) along a bottom of the trenches.
Kim doesn’t teach the conductor material having a conductively doped semiconductive material region over a metal silicide region.
However, Yu (fig. 1) teaches the conductor material ([0152], 112, 108) having a conductively doped semiconductive material region ([0153], 112) over a metal silicide region ([0152], 108). Yu also teaches the source layer provides a highly conductive horizontal current path for source electrodes to be subsequently formed ([0152]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory array of Kim to include the metal silicide source layer of Yu to provide a highly conductive horizontal current path for source electrodes to be subsequently formed.
Kim doesn’t teach that the lowest second tier and the next-lowest second tier independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier and the next-lowest second tier comprising (b) or (c), where (a): SiNx, where "x" is greater than 1.33 and no more than 2.0, or alternately where "x" is 0.5 to less than 1.33; (b): a bilayer comprising SiNy and comprising silicon dioxide positioned vertically relative one another, where "y" is 0.5 to no more than 2.0, the silicon dioxide of the bilayer being closer to the sacrificial material of the lowest first tier than is the SiNy; and (c): carbon-doped SiNz having carbon present at 0.1 to 10.0 atomic percent, "z" being 0.5 to no more than 2.0.
However, Lee (fig. 2A) teaches the lowest second tier ([0083], 113) and the next-lowest second tier ([0083], 117) independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier (113) and the next-lowest second tier (117) comprising (b) ([0084], may be oxide-nitride-oxide-nitride, the first oxide-nitride portion is defined to be the bilayer) or (c), where (b): a bilayer comprising SiNy ([0084]) and comprising silicon dioxide ([0084]) positioned vertically relative one another, where "y" is 0.5 to no more than 2.0, the silicon dioxide of the bilayer ([0032], [0083], polysilicon has a high etching selectivity relative to oxide, oxide is formed first in the oxide-nitride bilayer) being closer to the sacrificial material of the lowest first tier ([0082], 115 is sacrificial and may be formed of polysilicon) than is the SiNy. Lee teaches that a silicon nitride and silicon oxide bilayer may be used while still maintaining the function of insulating layers and having an etching selectivity relative to following processes when the sacrificial material is polysilicon ([0083]). One of ordinary skill in the art could have substituted the second tiers and sacrificial material of Lee for the second tiers and sacrificial material of Kim and obtained the predictable results of insulating layers and having an etching selectivity relative to following processes of removing the sacrificial material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the second tiers and sacrificial material of Lee for the second tiers and sacrificial material of Kim, since simple substitution of second tiers and sacrificial material for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Neither Kim nor Lee explicitly teaches the specific composition of the silicon nitride used throughout the device.
However, Yoo (see fig. 2), in a similar stack comprising alternating first and second tiers, teaches that silicon nitride can be any one of Si2N, SiN, Si3N4, and Si2N3 ([0046]). One of ordinary skill in the art could have substituted any of the silicon nitride variants of Yoo for the silicon nitride layers of Lee and obtained the predictable results of silicon nitride use in semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the known variations of silicon nitride taught by Yoo for the silicon nitride layers of Lee, since simple substitution of silicon nitride layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). As a result, the combination of Lee and Yoo teaches that “x” is greater than or less than 1.33.
Kim doesn’t teach after the replacing and prior to subsequent processing, removing the conductive material from within the horizontally-elongated trenches to expose the conductor tier.
However, Son (figs. 22A and 23A) teaches after the replacing and prior to subsequent processing, removing the conductive material ([0075], 180) from within the horizontally-elongated trenches ([0075], H) to expose the conductor tier ([0025], top portion of substrate 10W). Son also teaches that this process forms a functional first source conductive pattern ([0076]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim and Son to enable the formation of a source conductive pattern of Kim to be performed according to the teachings of Son because one of ordinary skill in the art would have been motivated to look to alternative suitable methods of performing the formation of a conductive material step disclosed in Kim and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 2, Lee (see figs 2A-K) teaches the method of claim 1 wherein one of the lowest second tier (113) and the next-lowest second tier (117) comprise the (a) ([0084], bilayer may include silicon nitride). Yoo teaches the specific composition of the silicon nitride as discussed in Claim 1.
Regarding Claim 3, Yoo teaches the method of claim 2 wherein “x” is greater than 1.33 ([0046]).
Regarding Claim 4, Yoo teaches the method of claim 2 wherein “x” is less than 1.33 ([0046]).
Regarding Claim 5, Lee (see figs 2A-K) teaches the method of claim 1 wherein the lowest second tier (113) and the next-lowest second tier (117) comprise the (b) ([0084], can be oxide-nitride-oxide-nitride or nitride-oxide-nitride, the first oxide-nitride portion is defined to be the bilayer). Additionally, Yoo teaches the specific composition of the silicon nitride as discussed in Claim 1.
Regarding Claim 7, Yoo teaches the method of claim 5 wherein “y” is 1.33 ([0046]).
Regarding Claim 8, Yoo teaches the method of claim 5 wherein “y” is less than 1.33 ([0046]).
Regarding Claim 9, Yoo teaches the method of claim 5 wherein “y” is greater than 1.33 ([0046]).
Regarding Claim 17, Lee (see figs. 2A-K) teaches the method of claim 1 wherein the lowest second tier (113) and the next-lowest second tier (117) have different ones of the (a) ([0084], 113 satisfies (a)), the (b) ([0084], 117 satisfies (b)), and the (c).
Regarding Claim 18, Lee (see figs. 2A-K) teaches the method of claim 1 wherein at least one of the lowest second tier (113) and the next-lowest second tier (117) have at least two ([0084], nitride-oxide-nitride satisfies both (a) and (b)) of the (a), the (b), and the (c).
Regarding Claim 19, Kim (figs. 3 and 6-11) teaches the method of claim 1 wherein at least one of the lowest second tier (IL3) and the next-lowest second tier (IL4) is directly against the sacrificial material of the lowest first tier (LHL).
Regarding Claim 20, Kim (figs. 3 and 6-11) teaches the method of claim 19 wherein each of the lowest second tier (IL3) and the next-lowest second tier (IL4) is directly against the sacrificial material of the lowest first tier (LHL).
Regarding Claim 47, Kim (figs. 3 and 6-11) teaches a method used in forming integrated circuitry comprising a memory array ([0019]) comprising strings of memory cells ([0021]), comprising:
forming a conductor tier ([0077], LSL) comprising conductor material ([0077], polysilicon) on a substrate ([0076]), the conductor material (LSL) comprising [] conductively doped semiconductive material ([0031], LSL may be n-type doped poly-silicon);
forming a lower portion ([0077], bottommost IL1, IL3, LHL, IL4) of a stack ([0079], MO, bottommost IL1, IL3, LHL, IL4, see fig. 7) that will comprise vertically-alternating first tiers ([0079], HL) and second tiers ([0079], IL1) above the conductor tier (LSL), the stack (MO, IL3, LHL, IL4) comprising laterally-spaced memory-block regions ([0051], regions between separation structures SPS in CAR region, see fig. 3), material of the first tiers (HL) being of different composition ([0080], HL may be silicon nitride, IL1 may be silicon oxide) from material of the second tiers (IL1), the lower portion comprising:
a lowest of the second tiers (IL3);
a next-lowest of the second tiers (IL4) directly above the lowest second tier (IL3);
a lowest of the first tiers (LHL) comprising sacrificial material ([0077]) vertically between the lowest second tier (IL3) and the next-lowest second tier (IL4); and
forming vertically-alternating first tiers (HL) and second tiers (IL1) of an upper portion (MO) of the stack (MO, IL3, LHL, IL4) above the lower portion (bottommost IL1, IL3, LHL, IL4), and
forming channel-material strings ([0085], VS) that extend through the first tiers (HL) and the second tiers (IL1) in the upper portion (MO) to the lowest first tier (LHL) in the lower portion (bottommost IL1, IL3, LHL, IL4);
forming horizontally-elongated trenches ([0095]-[0096], cutting holes later filled with SPS) through the upper portion (MO) and that extend through the next-lowest second tier (IL4) to the sacrificial material of the lowest first tier (LHL), the horizontally-elongated trenches (cutting holes filled with SPS) individually being between immediately-laterally-adjacent of the memory-block regions (regions between adjacent SPS);
through the horizontally-elongated trenches (cutting holes), replacing the sacrificial material in the lowest first tier (LHL) with conductive material ([0096], SSL) that directly electrically couples together ([0097]) channel material of the channel-material strings (VS) and the conductor material of the conductor tier (LSL);
removing only some ([0098], bottommost IL1, IL3, LHL, IL4 in CNR is not removed, see fig. 11) of the at least one of the (a), the (b), and the (c) from each of the lowest second tier (IL3) and the next-lowest second tier (IL4) before the replacing that forms the conductive material (SSL),
a remaining portion (bottommost IL1, IL3, LHL, IL4 in CNR) of the at least one of the (a), the (b), and the (c) in the next-lowest second tier (IL4) remaining directly above a remaining portion of the at least one of the (a), the (b), and the (c) in the lowest second tier (IL3) laterally outside of the memory-block regions (CNR is outside of CAR, see fig. 3) during and after the replacing (see fig. 11); and
forming an isolation material ([0095], SPS) within the horizontally-elongated trenches (cutting holes) and in direct physical contact with an upper surface of the conductor tier (LSL) along a bottom of the trenches.
Kim doesn’t teach the conductor material comprising metal silicide and conductively doped semiconductive material.
However, Yu (fig. 1) teaches the conductor material ([0152], 112, 108) comprising metal silicide ([0152], 108) and conductively doped semiconductive material ([0153], 112). Yu also teaches the source layer provides a highly conductive horizontal current path for source electrodes to be subsequently formed ([0152]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory array of Kim to include the metal silicide source layer of Yu to provide a highly conductive horizontal current path for source electrodes to be subsequently formed.
Kim doesn’t teach that the lowest second tier and the next-lowest second tier independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier and the next-lowest second tier comprising (b) or (c), where (a): SiNx, where "x" is greater than 1.33 and no more than 2.0, or alternately where "x" is 0.5 to less than 1.33; (b): a bilayer comprising SiNy and comprising silicon dioxide positioned vertically relative one another, where "y" is 0.5 to no more than 2.0, the silicon dioxide of the bilayer being closer to the sacrificial material of the lowest first tier than is the SiNy; and (c): carbon-doped SiNz having carbon present at 0.1 to 10.0 atomic percent, "z" being 0.5 to no more than 2.0.
However, Lee (fig. 2A) teaches the lowest second tier ([0083], 113) and the next-lowest second tier ([0083], 117) independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier (113) and the next-lowest second tier (117) comprising (b) ([0084], may be oxide-nitride-oxide-nitride, the first oxide-nitride portion is defined to be the bilayer) or (c), where (b): a bilayer comprising SiNy ([0084]) and comprising silicon dioxide ([0084]) positioned vertically relative one another, where "y" is 0.5 to no more than 2.0, the silicon dioxide of the bilayer ([0032], [0083], polysilicon has a high etching selectivity relative to oxide, oxide is formed first in the oxide-nitride bilayer) being closer to the sacrificial material of the lowest first tier ([0082], 115 is sacrificial and may be formed of polysilicon) than is the SiNy. Lee teaches that a silicon nitride and silicon oxide bilayer may be used while still maintaining the function of insulating layers and having an etching selectivity relative to following processes when the sacrificial material is polysilicon ([0083]). One of ordinary skill in the art could have substituted the second tiers and sacrificial material of Lee for the second tiers and sacrificial material of Kim and obtained the predictable results of insulating layers and having an etching selectivity relative to following processes of removing the sacrificial material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the second tiers and sacrificial material of Lee for the second tiers and sacrificial material of Kim, since simple substitution of second tiers and sacrificial material for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Neither Kim nor Lee explicitly teaches the specific composition of the silicon nitride used throughout the device.
However, Yoo (see fig. 2), in a similar stack comprising alternating first and second tiers, teaches that silicon nitride can be any one of Si2N, SiN, Si3N4, and Si2N3 ([0046]). One of ordinary skill in the art could have substituted any of the silicon nitride variants of Yoo for the silicon nitride layers of Lee and obtained the predictable results of silicon nitride use in semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the known variations of silicon nitride taught by Yoo for the silicon nitride layers of Lee, since simple substitution of silicon nitride layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). As a result, the combination of Lee and Yoo teaches that “x” is greater than or less than 1.33.
Kim doesn’t teach after the replacing and prior to subsequent processing, removing the conductive material from within the horizontally-elongated trenches to expose the conductor tier.
However, Son (figs. 22A and 23A) teaches after the replacing and prior to subsequent processing, removing the conductive material ([0075], 180) from within the horizontally-elongated trenches ([0075], H) to expose the conductor tier ([0025], top portion of substrate 10W). Son also teaches that this process forms a functional first source conductive pattern ([0076]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim and Son to enable the formation of a source conductive pattern of Kim to be performed according to the teachings of Son because one of ordinary skill in the art would have been motivated to look to alternative suitable methods of performing the formation of a conductive material step disclosed in Kim and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 48, Kim (figs. 3 and 6-11) teaches a method used in forming a memory array ([0019]) comprising strings of memory cells ([0021]), comprising:
forming a conductor tier ([0077], LSL) comprising conductor material ([0077], polysilicon) on a substrate ([0076]), the conductor material (LSL) containing conductively doped semiconductive material ([0031], LSL may be n-type doped poly-silicon) [];
forming a lower portion ([0077], bottommost IL1, IL3, LHL, IL4) of a first vertical stack ([0079], MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region, see fig. 7) that will comprise vertically-alternating first tiers ([0079], HL) and second tiers ([0079], IL1) above the conductor tier (LSL), the first vertical stack (MO, IL3, LHL, IL4 formed in CAR region) comprising laterally-spaced memory-block regions ([0051], regions between separation structures SPS in CAR region, see fig. 3), material of the first tiers (HL) being of different composition ([0080], HL may be silicon nitride, IL1 may be silicon oxide) from material of the second tiers (IL1);
forming a lower portion ([0077], bottommost IL1, IL3, LHL, IL4) of a second vertical stack ([0079], MO, bottommost IL1, IL3, LHL, IL4 formed in CNR region, see fig. 7) that will comprise vertically-alternating first tiers ([0079], HL) and second tiers ([0079], IL1) above the conductor tier (LSL), the second vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CNR region) being aside (see fig. 7) the first vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region) the lower portion in each of the first and second vertical stacks comprising:
a lowest of the second tiers (IL3);
a next-lowest of the second tiers (IL4) directly above the lowest second tier (IL3);
a lowest of the first tiers (LHL) comprising sacrificial material ([0077]) vertically between the lowest second tier (IL3) and the next-lowest second tier (IL4); and
forming vertically-alternating first tiers (HL) and second tiers (IL1) of an upper portion (MO) of each of the first and second vertical stacks (MO, IL3, LHL, IL4) above its lower portion (bottommost IL1, IL3, LHL, IL4), and
forming channel-material strings ([0085], VS) that extend through the first tiers (HL) and the second tiers (IL1) in the upper portion (MO) in the first vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region) to the lowest first tier (LHL) in the lower portion (bottommost IL1, IL3, LHL, IL4) in the first vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region);
forming horizontally-elongated trenches ([0095]-[0096], cutting holes later filled with SPS) through the upper portion (MO) of the first vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region) and that extend through the next-lowest second tier (IL4) to the sacrificial material of the lowest first tier (LHL) in the first vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region), the horizontally-elongated trenches (cutting holes filled with SPS) individually being between immediately-laterally-adjacent of the memory-block regions (regions between adjacent SPS) in the first vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CAR region);
through the horizontally-elongated trenches (cutting holes), replacing the sacrificial material in the lowest first tier (LHL) with conductive material ([0096], SSL) that directly electrically couples together ([0097]) channel material of the channel-material strings (VS) and the conductor material of the conductor tier (LSL),
the at least one of the (a), the (b), and the (c) of the lowest second tier (IL3) and the next-lowest second tier (IL4) having the sacrificial material (LHL) there-between remaining in the second vertical stack (MO, bottommost IL1, IL3, LHL, IL4 formed in CNR region) in a finished construction of the integrated circuitry, the second vertical stack being laterally outside of the memory-block regions (CNR is outside of CAR, see fig. 3); and
forming an isolation material ([0095], SPS) within the horizontally-elongated trenches (cutting holes) and in direct physical contact with an upper surface of the conductor tier (LSL) along a bottom of the trenches.
Kim doesn’t teach the conductor material comprising conductively doped semiconductive material and metal silicide.
However, Yu (fig. 1) teaches the conductor material ([0152], 112, 108) comprising conductively doped semiconductive material ([0153], 112) and metal silicide ([0152], 108). Yu also teaches the source layer provides a highly conductive horizontal current path for source electrodes to be subsequently formed ([0152]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory array of Kim to include the metal silicide source layer of Yu to provide a highly conductive horizontal current path for source electrodes to be subsequently formed.
Kim doesn’t teach that the lowest second tier and the next-lowest second tier independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier and the next-lowest second tier comprising (b) or (c), where (a): SiNx, where "x" is greater than 1.33 and no more than 2.0, or alternately where "x" is 0.5 to less than 1.33; (b): a bilayer comprising SiNy and comprising silicon dioxide positioned vertically relative one another, where "y" is 0.5 to no more than 2.0, the silicon dioxide of the bilayer being closer to the sacrificial material of the lowest first tier than is the SiNy; and (c): carbon-doped SiNz having carbon present at 0.1 to 10.0 atomic percent, "z" being 0.5 to no more than 2.0.
However, Lee (fig. 2A) teaches the lowest second tier ([0083], 113) and the next-lowest second tier ([0083], 117) independently consisting of one of (a), (b), and (c), with at least one of the lowest second tier (113) and the next-lowest second tier (117) comprising (b) ([0084], may be oxide-nitride-oxide-nitride, the first oxide-nitride portion is defined to be the bilayer) or (c), where (b): a bilayer comprising SiNy ([0084]) and comprising silicon dioxide ([0084]) positioned vertically relative one another, where "y" is 0.5 to no more than 2.0, the silicon dioxide of the bilayer ([0032], [0083], polysilicon has a high etching selectivity relative to oxide, oxide is formed first in the oxide-nitride bilayer) being closer to the sacrificial material of the lowest first tier ([0082], 115 is sacrificial and may be formed of polysilicon) than is the SiNy. Lee teaches that a silicon nitride and silicon oxide bilayer may be used while still maintaining the function of insulating layers and having an etching selectivity relative to following processes when the sacrificial material is polysilicon ([0083]). One of ordinary skill in the art could have substituted the second tiers and sacrificial material of Lee for the second tiers and sacrificial material of Kim and obtained the predictable results of insulating layers and having an etching selectivity relative to following processes of removing the sacrificial material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the second tiers and sacrificial material of Lee for the second tiers and sacrificial material of Kim, since simple substitution of second tiers and sacrificial material for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Neither Kim nor Lee explicitly teaches the specific composition of the silicon nitride used throughout the device.
However, Yoo (see fig. 2), in a similar stack comprising alternating first and second tiers, teaches that silicon nitride can be any one of Si2N, SiN, Si3N4, and Si2N3 ([0046]). One of ordinary skill in the art could have substituted any of the silicon nitride variants of Yoo for the silicon nitride layers of Lee and obtained the predictable results of silicon nitride use in semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the known variations of silicon nitride taught by Yoo for the silicon nitride layers of Lee, since simple substitution of silicon nitride layers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). As a result, the combination of Lee and Yoo teaches that “x” is greater than or less than 1.33.
Kim doesn’t teach after the replacing and prior to subsequent processing, removing the conductive material from within the horizontally-elongated trenches to expose the conductor tier.
However, Son (figs. 22A and 23A) teaches after the replacing and prior to subsequent processing, removing the conductive material ([0075], 180) from within the horizontally-elongated trenches ([0075], H) to expose the conductor tier ([0025], top portion of substrate 10W). Son also teaches that this process forms a functional first source conductive pattern ([0076]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim and Son to enable the formation of a source conductive pattern of Kim to be performed according to the teachings of Son because one of ordinary skill in the art would have been motivated to look to alternative suitable methods of performing the formation of a conductive material step disclosed in Kim and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 49, Kim (fig. 11) teaches the method of claim 48 comprising, in the finished construction of the integrated circuitry (see fig. 11): an upper polysilicon-comprising layer ([0078], USL) above and directly against the next-lowest second tier (IL4); and a lower polysilicon-comprising layer ([0077], LSL) below and directly against the lowest second tier (IL3).
Regarding Claim 50, Lee (see figs 2A-K) teaches the method of claim 48 wherein one of the lowest second tier (113) and the next-lowest second tier (117) comprise the (a) ([0084], bilayer may include silicon nitride). Yoo teaches the specific composition of the silicon nitride as discussed in Claim 48.
Regarding Claim 51, Lee (see figs 2A-K) teaches the method of claim 48 wherein the lowest second tier (113) and the next-lowest second tier (117) comprise the (b) ([0084], can be oxide-nitride-oxide-nitride or nitride-oxide-nitride). Additionally, Yoo teaches the specific composition of the silicon nitride as discussed in Claim 48.
Regarding Claim 52, Lee (see figs. 2A-K) teaches the method of claim 51 wherein the (b) comprises part of a trilayer ([0084], may be oxide-nitride-oxide-nitride, the oxide-nitride-oxide portion is defined to be the trilayer), the silicon dioxide comprising one layer of silicon dioxide that is one of directly above or directly below the SiNy ([0084]), the trilayer comprising another layer of silicon dioxide the other of directly above or directly below the SiNy, the SiNy comprising a third layer of the trilayer that is vertically between the one and another layers of silicon dioxide ([0084]).
Regarding Claim 56, Lee (see figs. 2A-K) teaches the method of claim 48 wherein the lowest second tier (113) and the next-lowest second tier (117) have different ones of the (a) ([0084], 113 satisfies (a)), the (b) ([0084], 117 satisfies (b)), and the (c).
Regarding Claim 57, Lee (see figs. 2A-K) teaches the method of claim 48 wherein at least one of the lowest second tier (113) and the next-lowest second tier (117) have at least two ([0084], nitride-oxide-nitride satisfies both (a) and (b)) of the (a), the (b), and the (c).
Regarding Claim 58, Kim (figs. 3 and 6-11) teaches the method of claim 1 wherein the sacrificial material [] (LHL) that is vertically between the lowest second tier (IL3) and the next-lowest second tier (IL4) laterally outside of the memory-block regions (CNR is outside of CAR) during and after the replacing (see fig. 11). Lee (fig. 2A) teaches the sacrificial material comprises polysilicon ([0082]).
Regarding Claim 59, Kim (figs. 3 and 6-11) teaches the method of claim 47 wherein the sacrificial material [] (LHL) that is vertically between the lowest second tier (IL3) and the next-lowest second tier (IL4) laterally outside of the memory-block regions (CNR is outside of CAR) during and after the replacing (see fig. 11). Lee (fig. 2A) teaches the sacrificial material comprises polysilicon ([0082]).
Regarding Claim 60, Lee (fig. 2A) teaches the method of claim 48 wherein the sacrificial material comprises polysilicon ([0082]).
Regarding Claim 61, Kim doesn’t teach the conductive material within the lowest first tier projects laterally to outside of the memory-block regions to within the horizontally-elongated trenches between the immediately-laterally-adjacent memory-block regions, the conductive material within the lowest first tier being discontinuous between the immediately-laterally-adjacent memory-block regions and having terminal ends that are within lateral confines of the horizontally-elongated trenches.
However, Son (figs. 3 and 24A) teaches the method of claim 1 wherein the conductive material within the lowest first tier ([0026], SCP1) projects laterally to outside (SCP1 is formed partially in region where CSP is formed, see fig. 3) of the memory-block regions (regions between adjacent CSP in CAR region, see fig. 3) to within the horizontally-elongated trenches ([0078], GIR is later filled with CSP and the terminal ends of SCP1 are within the lateral confines of the trench GIR/CSP, see fig. 3) between the immediately-laterally-adjacent memory-block regions (regions between adjacent CSP in CAR region, see fig. 3), the conductive material within the lowest first tier (SCP1) being discontinuous between the immediately-laterally-adjacent memory-block regions (regions between adjacent CSP in CAR region, see fig. 3) and having terminal ends that are within lateral confines of the horizontally-elongated trenches (the terminal ends of SCP1 are within the lateral confines of the trench GIR/CSP, see fig. 3). Son teaches that the conductive material within the lowest first tier may change while still maintaining the function of electrically connecting adjacent conductive layers. One of ordinary skill in the art could have substituted the conductive material within the lowest first tier of Son for the lowest first tier of Kim and yielded the predictable results of maintaining electrical connection between conductive layers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lowest first tier of Son for the lowest first tier of Kim, since simple substitution of lowest first tiers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 62, Kim doesn’t teach the conductive material within the lowest first tier projects laterally to outside of the memory-block regions to within the horizontally-elongated trenches between the immediately-laterally-adjacent memory-block regions, the conductive material within the lowest first tier being discontinuous between the immediately-laterally-adjacent memory-block regions and having terminal ends that are within lateral confines of the horizontally-elongated trenches.
However, Son (figs. 3 and 24A) teaches the method of claim 47 wherein the conductive material within the lowest first tier ([0026], SCP1) projects laterally to outside (SCP1 is formed partially in region where CSP is formed, see fig. 3) of the memory-block regions (regions between adjacent CSP in CAR region, see fig. 3) to within the horizontally-elongated trenches ([0078], GIR is later filled with CSP and the terminal ends of SCP1 are within the lateral confines of the trench GIR/CSP, see fig. 3) between the immediately-laterally-adjacent memory-block regions (regions between adjacent CSP in CAR region, see fig. 3), the conductive material within the lowest first tier (SCP1) being discontinuous between the immediately-laterally-adjacent memory-block regions (regions between adjacent CSP in CAR region, see fig. 3) and having terminal ends that are within lateral confines of the horizontally-elongated trenches (the terminal ends of SCP1 are within the lateral confines of the trench GIR/CSP, see fig. 3). Son teaches that the conductive material within the lowest first tier may change while still maintaining the function of electrically connecting adjacent conductive layers. One of ordinary skill in the art could have substituted the conductive material within the lowest first tier of Son for the lowest first tier of Kim and yielded the predictable results of maintaining electrical connection between conductive layers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lowest first tier of Son for the lowest first tier of Kim, since simple substitution of lowest first tiers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 63, Kim doesn’t teach the conductive material within the lowest first tier projects laterally to outside of the memory-block regions to within the horizontally-elongated trenches between the immediately-laterally-adjacent memory-block regions, the conductive material within the lowest first tier being discontinuous between the immediately-laterally-adjacent memory-block regions and having terminal ends that are within lateral confines of the horizontally-elongated trenches.
However, Son (figs. 3 and 24A) teaches the method of claim 48 wherein the conductive material within the lowest first tier ([0026], SCP1) projects laterally to outside (SCP1 is formed partially in region where CSP is formed, see fig. 3) of the memory-block regions (regions between adjacent CSP in CAR region, see fig. 3) to within the horizontally-elongated trenches ([0078], GIR is later filled with CSP and the terminal ends of SCP1 are within the lateral confines of the trench GIR/CSP, see fig. 3) between the immediately-laterally-adjacent memory-block regions (regions between adjacent CSP in CAR region, see fig. 3), the conductive material within the lowest first tier (SCP1) being discontinuous between the immediately-laterally-adjacent memory-block regions (regions between adjacent CSP in CAR region, see fig. 3) and having terminal ends that are within lateral confines of the horizontally-elongated trenches (the terminal ends of SCP1 are within the lateral confines of the trench GIR/CSP, see fig. 3). Son teaches that the conductive material within the lowest first tier may change while still maintaining the function of electrically connecting adjacent conductive layers. One of ordinary skill in the art could have substituted the conductive material within the lowest first tier of Son for the lowest first tier of Kim and yielded the predictable results of maintaining electrical connection between conductive layers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the lowest first tier of Son for the lowest first tier of Kim, since simple substitution of lowest first tiers for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 10-14 and 53 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Lee, Yu, Yoo, and Son, as applied to Claims 1 and 48, respectively, and in further view in view of Tsai et al. (U.S. 2017/0323954 A1; hereinafter Tsai).
Regarding Claim 10, neither Kim nor Lee teach the method of claim 1 wherein the lowest second tier and the next-lowest second tier comprise the (c). Lee does teach the lowest second tier (113) and the next-lowest second tier (117) comprise materials that have high etching selectivity with polysilicon ([0032], [0083]).
However, Tsai (see fig. 2C), teaches the (c) ([0016], silicon carbide nitride with carbon concentration of 1-12 at%). Tsai also teaches this material improves the needed etching selectivity with polysilicon ([0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Kim and Lee to utilize the carbon doped silicon nitride of Tsai to improve etching selectivity with polysilicon. Additionally, Yoo teaches the specific composition of the silicon nitride as discussed in Claim 1.
Regarding Claim 11, Tsai (see fig. 2C) teaches the method of claim 10 wherein the carbon is present at no more than 2.0 atomic percent ([0016], can be 1-2 at%).
Regarding Claims 12, Yoo teaches the method of claim 10 wherein “z” is 1.33 ([0046]).
Regarding Claims 13, Yoo teaches the method of claim 10 wherein “z” is less than 1.33 ([0046]).
Regarding Claims 14, Yoo teaches the method of claim 10 wherein “z” is greater than 1.33 ([0046]).
Regarding Claim 53, Kim nor Lee teach the method of claim 48 wherein the lowest second tier and the next-lowest second tier comprise the (c). Lee does teach the lowest second tier (113) and the next-lowest second tier (117) comprise materials that have high etching selectivity with polysilicon ([0032], [0083]).
However, Tsai (see fig. 2C), teaches the (c) ([0016], silicon carbide nitride with carbon concentration of 1-12 at%). Tsai also teaches this material improves the needed etching selectivity with polysilicon ([0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Kim and Lee to utilize the carbon doped silicon nitride of Tsai to improve etching selectivity with polysilicon. Additionally, Yoo teaches the specific composition of the silicon nitride as discussed in Claim 48.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 13, 2026