DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025, 02/05/2026 has been entered.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed applications, Application No. 16/139,093, Application No. 16/986,007, and U.S. Provisional Patent Application Serial No. 63/134,941, fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. Independent claims 1, 12, and 20 recite decomposing limitations, claims 1 and 20 recite a decomposition circuit, of which insufficient disclosure is provided from the prior-filed applications. Accordingly, claims 1-20 are not entitled to the benefit of the prior applications, and instead have an effective filing date of 17 June 2021.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 12, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200089472 A1 Pareek et al. (hereinafter “Pareek”) in view of US 20200310818 A1 Ware et al. (hereinafter “Ware”) in view of US 20180322390 A1 Das et al. (hereinafter “Das”).
Regarding claim 1, Pareek teaches a multiplier circuitry comprising:
one or more storage register circuits (Fig. 6, 602, 604; [0040]) configured to store digital bits corresponding to first operand (Fig. 6, 602; [0040], floating point) and a second operand (Fig. 6, 604; [0040], floating point);
a decomposition circuit (Fig. 6, 606; [0041]) configured to: decompose the first operand into a first plurality of first operand values (Fig. 6, sign bits, exponents, mantissa; [0043], [0046-0047],
w
i
s
,
w
i
(
e
)
,
w
i
m
), and decompose the second operand into a second plurality of second operand values (Fig. 6, sign bits, exponents, mantissa; [0043], [0046-0047],
x
j
s
,
x
j
(
e
)
,
x
j
m
);
a plurality of multiplier circuits (Fig. 6, 620; [0043]), each multiplier circuit configured to multiply a respective first operand value of the first plurality of first operand values with a respective second operand value of the second plurality of second operand values to generate a corresponding partial result of a plurality of partial results (Fig. 6, 622; [0043], four products known as mantissa products);
an accumulator circuit (Fig. 6, 638, 640; [0048] accumulator 638 sums the output from XOR 636 with value held in accumulation register 640) configured to accumulate the plurality of partial results using a format to generate a complete result of the format that is stored in the accumulator circuit ([0047] partial results further processed by XOR 636 that outputs a fixed point representation, which is inputted into accumulator 638 and [0048] further accumulated); and
a first conversion circuit (Fig. 6, 642; [0048]) configured to convert the complete result of the format into an output result of an output format ([0048] floating point).
Pareek discloses the claimed invention except for disclosing a plurality of multiplier circuits.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to substitute a multiplier circuit with a plurality of multiplier circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. See MPEP 2144.04(vi)(B).
Further, Pareek is silent with disclosing an intermediate format that comprises an extended length fixed point format, a first bit length of the extended length fixed point format being greater than a second bit length of at least one of the first operand or the second operand.
Ware teaches an intermediate format that comprises an extended length fixed point format ([0095] existing formats (16 and 32 bit) additional two or four bits), a first bit length of the extended length fixed point format being greater ([0095] existing formats (16 and 32 bit) additional two or four bits (i.e. 16 + 2 = 18 or 16 + 4 = 20 or 32 + 2 = 34 or 32 + 4 = 36)) than a second bit length of at least one format ([0095] existing formats before additional bits, 16 and 32 bits) of the first operand or the second operand.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Ware’s intermediate format feature because they are in the claimed invention’s same field of endeavor of multiplier accumulator circuitry ([0003]). Das is in the claimed invention’s same field of endeavor of multiply-accumulate operations (Fig. 7A, 711, [0161]) and teaches that accumulate operations can cause overflow in the accumulator (Fig. 7A, 714, [0161]). However, Das remedies this by performing right-shift operations on the product (Fig. 7A, 716, [0161]; Fig. 7B, 727, [0162]). However, to incorporate shifter circuitry and determining if overflow would occur would be less efficient, area and power wise, than extending the original length by two or four bits (Ware, [0095]). It would have been obvious to one of ordinary skill in the art to implement the intermediate format feature as the values can generally handle the additional two or four bits or precision range (Ware, [0095]). A person of ordinary skill in the art would look to Ware’s intermediate format feature in order to utilize an efficient method for data processing concerning area and power of the device, instead of incorporating additional shift circuitry as taught by Das.
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches further comprising:
a third conversion circuit (Fig. 6, 636; [0047-0048]; Note: “XOR” 636 performs same functionality of “conversion circuit” despite having a different name) configured to convert the plurality of partial results from a first format to the format before the accumulation ([0047] outputs in fixed point representation after performing XOR operation).
Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Ware teaches an intermediate format ([0095] existing formats (16 and 32 bit) additional two or four bits).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches further comprising:
a plurality of adders (Fig. 6, 626; [0046]) each configured to add respective first operand values and second operand values corresponding to exponent portions of the first operand and the second operand (Fig. 6, exponents
w
i
(
e
)
and
x
j
(
e
)
) to generate a plurality of exponent values ([0046] summed exponents of the exponents of the floating point operands); and
a plurality of shift circuits (Fig. 6, 628; [0046]) each configured to shift a respective partial result of the plurality of partial results before the accumulation based on a corresponding exponent value of the plurality of exponent values to generate a corresponding shifted partial result of a plurality of shifted partial results (Fig. 6, output of 628; [0046] left shifter 628 left shifts mantissa products by number of bits indicated by summed exponents).
Pareek discloses the claimed invention except for a plurality of adders and a plurality of shift circuits.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to substitute an adder for a plurality of adders and a shift circuit for a plurality of shift circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. See MPEP 2144.04(vi)(B).
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches further comprising:
a plurality of conversion circuits (Fig. 6, 636; [0047-0048] Note: “XOR” 636 performs same functionality of “conversion circuit” despite having a different name) each coupled to an output of a corresponding shift circuit (Fig. 6, XOR 636 coupled to left shifter 628 through concatenation 630) of the plurality of shift circuits and configured to convert the corresponding shifted partial result from the first format to the format before the accumulation (Fig. 6, output of 636; [0047] outputs in fixed point representation after performing XOR operation).
Pareek discloses the claimed invention except for a plurality of conversion circuits and a plurality of shift circuits.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to substitute a conversion circuit for a plurality of conversion circuits and a shift circuit for a plurality of shift circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. See MPEP 2144.04(vi)(B).
Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Ware teaches an intermediate format ([0095] existing formats (16 and 32 bit) additional two or four bits).
The motivation to combine provided with respect to claim 1 equally applies.
Claims 12, 14-16 are directed to a method that would be practiced by the
device of claim 1, 4-6. All steps recited in claims 12, 14-16 are practiced by the device of
claims 1, 4-6, respectively. The claims 1, 4-6 analysis equally applies to claims
12, 14-16, respectively.
Claim 20 is directed to a computer program product that would be executed by the device of claim 1. The claim 1 analysis equally applies.
Additionally, Pareek teaches:
a stored hardware description language program having sets of instructions, the instructions when executed produce a digital circuit ([0059-0061], [0066]).
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Ware in view of Das as applied to claim 1 above, and further in view of Elia, Marcus. "Loss of Precision in Implementations of the Toom-Cook Algorithm". Dissertation, The University of Vermont. May, 2021. Chapter 7. pp. 79-98. (hereinafter “Elia”).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches the decomposition circuit is configured to decompose the first operand and the second operand (see claim 1 mapping).
While Pareek teaches the decomposition of operands, they are silent with disclosing the type of algorithm performed to do so, and are specifically silent with disclosing such as a Toom-Cook decomposition algorithm.
Further, Pareek in view of Ware in view of Das are silent with disclosing the type of algorithm performed to do so, and are specifically silent with disclosing such as a Toom-Cook decomposition algorithm.
Elia teaches a Toom-Cook decomposition algorithm (Pg. 6, Para. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Ware in view of Das’s modified multiply-accumulate device with Elia’s Toom-Cook decomposition algorithm because they are in the claimed invention’s same field of endeavor of multiplication methods (Abstract). It would have been obvious to one of ordinary skill in the art to implement the decomposition algorithm, as variations of the decomposition are more suited for the types of formats used in computations (Pg. 14, Para. 2-3; Pg. 15, Para. 1). Making this modification would be beneficial, as based on the decomposition chosen, there are achievable speed ups in computation (Pg. 21, Para. 1; Pg. 15-20, Comparison of Toom-Cook Decompositions Graphs).
Regarding claim 13, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Pareek teaches decompose the first operand and the second operand (see claim 1 mapping).
While Pareek teaches the decomposition of operands, they are silent with disclosing the type of algorithm performed to do so, and are specifically silent with disclosing applying a Toom-Cook decomposition algorithm.
Elia teaches applying a Toom-Cook decomposition algorithm (Pg. 6, Para. 2).
The motivation to combine provided with respect to claim 2 equally applies.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Ware in view of Das as applied to claim 1 above, and further in view of US 20200097799 A1 Divakar et al. (hereinafter “Divakar”).
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated.
Pareek teaches a first operand and the second operand from a floating point format and the decomposition (see claim 1 mapping).
Pareek is silent with disclosing another conversion circuit configured to convert the operand and the other operand from a floating point format into an integer format prior to the decomposition.
Pareek in view of Ware in view of Das are silent with disclosing another conversion circuit configured to convert the operand and the other operand from a floating point format into an integer format prior to the decomposition.
Divakar teaches a second conversion circuit (Fig. 4D, 485a-b, [0040]) configured to convert the first operand and the second operand from a floating point format into an integer format prior ([0040] allows given operands to be converted into any one of multiple different data formats prior to operation by configuration information, provided by the format manager block, to be fed to the multiplexer blocks 486a-b, Fig. 8A, 815, 820, [0053] of which data formats include floating point and integer (or other fixed point) where operands are modified to perform a computation in a particular format to obtain the result in a particular format; [0035] as an example the multiplier is capable of performing fixed point computations only) to the decomposition.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Ware in view of Das’s multiply-accumulate device with Divakar’s conversion circuit because they are in the claimed invention’s same field of endeavor of multiply-accumulate devices ([0021]). Pareek teaches that its storage circuits (Fig. 6, 602, 604) store operands only in floating point format ([0040]). It would have been obvious to one of ordinary skill in the art to implement the conversion circuit, as Divakar teaches an operand can be converted to different data formats prior to computation ([0040]) as pairs of operands can differ in format type and even precision ([0038]). Making this modification would be beneficial, as by including the conversion circuit in Pareek in view of Ware in view of Das’s architecture, Pareek in view of Ware in view of Das’s device now has the capability to receive non-floating point formats values for processing, thus expanding its applications of use.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Ware in view of Das as applied to claims 1 and 12 above, and further in view of US 20200026494 A1 Langhammer et al. (hereinafter “Langhammer”).
Regarding claim 9, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches wherein the conversion circuit (see claim 1 mapping) is further configured:
to convert the complete result of the format into the output result of the output format by truncating the complete result stored in the accumulator circuit based on the output format (Fig. 6, fixed-to-floating point conversion 642 converts accum. reg. 640 to yield output of 642; [0048] floating point).
Although Pareek teaches the converting, they are silent with disclosing converting by truncating. Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Ware teaches an intermediate format ([0095] existing formats (16 and 32 bit) additional two or four bits).
The motivation to combine provided with respect to claim 1 equally applies.
Pareek in view of Ware in view of Das are silent with disclosing converting by truncating.
Langhammer teaches converting by truncating (Fig 7B, 744; [0069] truncates; Fig. 7C, 762; Fig. 7D, 762’; Fig. 7E, 762’’; [0073-0075]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Ware in view of Das’s multiply-accumulate device with Langhammer’s truncation feature because they are in the claimed invention’s same field of endeavor of accumulation methods ([0038]). It would have been obvious to one of ordinary skill in the art to implement the truncation feature, as based on how the truncation parameter is adjusted, there can be a tradeoff between resource utilization and accuracy ([0069]). Making this modification would be beneficial, as based on the adjustment position of the truncation, architecture designers can prioritize accuracy over resource utilization for correctness or they can prioritize resource utilization over accuracy for power and energy efficiency.
Claim 18 is directed to a method that would be practiced by the device of claim 9. All steps recited in claim 18 are practiced by the device of claim 9. The claim 9 analysis equally applies to claim 18.
Claims 7, 10, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Ware in view of Das as applied to claims 1 and 12 above, and further in view of Wong, William G. "What's the Difference Between Fixed-Point, Floating-Point, and Numerical Formats?" Electronic Design. Aug. 31, 2017. (hereinafter “Wong”) in view of Langhammer.
Regarding claim 7, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches a first format of at least one of the first operand or the second operand (Fig. 6, 602, 604; [0040], floating point).
Pareek is silent with explicitly disclosing is selected from the group consisting of an INT8 format, an INT16 format, a FP16 format and a FP32 format.
Pareek in view of Ware in view of Das are silent with explicitly disclosing is selected from the group consisting of an INT8 format, an INT16 format, a FP16 format and a FP32 format.
Wong teaches is selected from the group consisting of an INT8 format, an INT16 format (Pg. 3, Para. 3, 8-, 16-, bit values) a FP16 format and a FP32 format (Pg. 2, Para. 3, 16-bit half precision; Pg. 3, Para. 6, 32-bit).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Ware in view of Das’s multiply-accumulate device with Wong’s numerical format feature because they are in the claimed invention’s same field of endeavor of computing (Pg. 2, Para. 1). Although Pareek generally teaches performing low-precision operations ([0018]), they are silent with disclosing explicitly the numerical formats used and of which the device is capable of processing. It would have been obvious to one of ordinary skill in the art to implement the numerical format feature as they are well-known format types used in computer architecture (Pg. 2, Para. 1-2; Pg. 3, Para. 4-5; Pg. 4, Para. 3) as referenced in the IEEE 754 standards (Pg. 2, Para. 3; Pg. 4, Para. 6), and would have yielded predictable results when implemented. Using the known numerical formats to provide a predictable outcome in Pareek in view of Ware in view of Das would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize that Pareek in view of Ware in view of Das was ready for improvement to incorporate the well-known numerical formats, as taught by Wong.
Wong is silent with disclosing selecting.
Thus, Pareek in view of Ware in view of Das in view of Wong is silent with disclosing selecting.
Langhammer teaches selecting ([0047-0049] fixed-point and floating-point mode).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Ware in view of Das in view of Wong’s multiply-accumulate system with Langhammer’s selecting feature because they are in the claimed invention’s same field of endeavor of accumulation methods ([0038]). It would have been obvious to one of ordinary skill in the art to implement the selecting feature as a way to handle the different data format types to be processed ([0047]). Making this modification would be beneficial, as based on the mode, components in Pareek in view of Ware in view of Das in view of Wong’s multiply-accumulate system can be configured to support a wider range of precisions and utilized only when needed.
Claim 17 is directed to a method that would be practiced by the device of claim 7. All steps recited in claim 17 are practiced by the device of claim 7. The claim 7 analysis equally applies to claim 17.
Regarding claim 10, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches wherein the conversion circuit (see claim 1 mapping) is further configured:
to convert the complete result of the second format into the output result of the output format by truncating the complete result stored in the accumulator circuit (see claim 9 mapping) based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format.
Although Pareek teaches the converting, they are silent with disclosing converting by truncating. Additionally, they are silent with disclosing based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format. Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Ware teaches an intermediate format ([0095] existing formats (16 and 32 bit) additional two or four bits).
The motivation to combine provided with respect to claim 1 equally applies.
Pareek in view of Ware in view of Das are silent with converting by truncating, and with disclosing based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format.
Wong teaches based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format (Pg. 3, Para. 6, 32-bit, 64-bit, 128-bit).
The motivation to combine provided with respect to claim 7 equally applies.
Similarly, Wong is silent with disclosing converting by truncating and based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format.
Thus, Pareek in view of Ware in view of Das in view of Wong is silent with disclosing converting by truncating and based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format.
Langhammer teaches converting by truncating (Fig 7B, 744; [0069] truncates; Fig. 7C, 762; Fig. 7D, 762’; Fig. 7E, 762’’; [0073-0075]) and based at least in part on a defined output precision selected ([0047-0049] floating-point mode).
The motivation to combine provided with respect to claim 9 equally applies in regards to the truncating limitation.
The motivation to combine provided with respect to claim 7 equally applies in regards to the selecting limitation.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Ware in view of Das as applied to claims 1 and 12 above, and further in view of Wong.
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches the output format (see claim 1 mapping).
Although Pareek generally teaches the output format, they are silent with explicitly disclosing as a FP32 format.
Further, Pareek in view of Ware in view of Das are silent with explicitly disclosing as a FP32 format.
Wong teaches a FP32 format (Pg. 3, Para. 6, 32-bit).
The motivation to combine provided with respect to claim 7 equally applies.
Claims 11 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Ware in view of Das as applied to claims 1 and 12 above, and further in view of US 20200249942 A1 Lutz et al. (hereinafter “Lutz”).
Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches wherein the accumulator circuit (see claim 1 mapping) is further configured:
accumulate the plurality of partial results from a smallest partial result among the plurality of partial results to a largest partial result among the plurality of partial results ([0047] partial results further processed by XOR 636 and outputs a fixed point representation, which is inputted into accumulator 638).
Although Pareek teaches the XOR circuit outputting an n-bit value, which is the width of the output of the concatenation circuit 630 to be accumulated in accumulator 638, they are silent with explicitly disclosing a range from smallest to largest partial results.
Pareek in view of Ware in view of Das are silent with explicitly disclosing a range from smallest to largest partial results.
Lutz teaches from a smallest partial result among the plurality of partial results to a largest partial result ([0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Ware in view of Das’s multiply-accumulate device with Lutz’s floating-point number range feature because they are in the claimed invention’s same field of endeavor of floating-point data format operations ([0002]). Although Pareek generally teaches performing processing floating-point values ([0047]), they are silent with disclosing explicitly the numerical range of values as it relates to the format precision. It would have been obvious to one of ordinary skill in the art to implement the floating-point number range feature as there are a finite number of reasonable values the value can be; a double precision floating point (or FP64) has a range from
2
-
1000
to
2
1000
([0036]). Thus, it would have been obvious to try and would have yielded predictable results when implemented. Using the known floating-point number range to provide a predictable outcome in Pareek would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize that Pareek was ready for improvement to incorporate the well-known numerical range, as taught by Lutz.
Claim 19 is directed to a method that would be practiced by the device of claim 11. All steps recited in claim 19 are practiced by the device of claim 11. The claim 11 analysis equally applies to claim 19.
Response to Arguments
Priority. Applicant argues the following in substance:
Applicant asserts that, adequate support and enablement for any person skilled in the art is set forth throughout the prior-filed applications. For example, column 5 lines 48 through 57 of U.S. Patent No. 10,776,078 (corresponding to App. No 16/139,093) recites that "one or more operands, A, may be received in a first storage register circuit 130 and one or more second operands, B, may be received in a second storage register circuit 131. A plurality of multipliers 132-135 are coupled to particular segments of registers 130 and 131 to receive the one or more operands. In this example, different operands, or components of each operand, may be positioned in different locations in registers 130 and 131 based on the mode so that multipliers 132-135 may be efficiently shared." Furthermore, column 6 lines 16 through 21 of U.S. Patent No. 10,776,078 (Remarks p. 7).
Examiner respectfully disagrees. Applicant is pointing to the multipliers 132-135 and registers 130-131, as best exemplified in Fig. 1B of U.S. Patent No. 10,776,078 (16/139,093), as support for the "decomposition circuit configured to decompose". However, it appears that these features provide support for a separate feature of the claimed invention, the "one or more storage register circuits" and "a plurality of multiplier circuits" as recited in claim 1 of the instant application, and as illustrated as multipliers 232-235 and registers 230-231 in Fig. 2C of the instant application. Further,
column 6 lines 16 through 21 describes ‘positioning’ operands, rather than ‘decomposing’ and the functionalities corresponding decomposition circuit.
Applicant asserts that, U.S. Patent No. 10,776,078 discloses in column 6 lines 39 through 41 how "select circuits (e.g., multiplexers)" provide "selective arrangement of inputs in different register segments." Thus, the disclosure of at least 16/139,093 provides sufficient disclosure for specific circuitry capable of decomposing an operand into "different ... components of each operand" and sharing the different components of an operand among a plurality of multipliers. Although not expressly referred to as a "decomposition circuit," the disclosure of the prior-filed applications unequivocally discloses adequate subject matter to enable a person skilled in the art to practice "a decomposition circuit configured to: decompose the first operand into a first plurality of first operand values, and decompose the second operand into a second plurality of second operand values" as required by 35 U.S.C. § 112(a) (Remarks p. 8).
Examiner respectfully disagrees. Applicant points to multiplexers 102-103, as best exemplified in Fig. 1A of U.S. Patent No. 10,776,078, as providing sufficient disclosure for the "decomposition circuit configured to decompose". However, it appears that these features recited are describing a separate feature of the claimed invention, "to selectively couple operands based on a mode control signal" ([0022] of the specification as filed in 16/139,093), that is unlike the decomposition circuit recited in the claims and described in the specification of the instant application. The disclosure of the prior-filed applications does not meet the requirements set forth as the details of the decomposition circuit and its functionality of decomposing are not covered.
35 USC 103. Applicant argues the following in substance:
Applicant asserts that, the claims are entitled to the benefit of priority under the prior-filed applications and an effective filing date of September 23, 2018. For this reason, Applicant further submits that at least Ware (having an effective filing date of February 2, 2020), Elia (having a publication date of May 2021), and Lutz (having an effective priority date of May 29, 2019) postdate the effective filing date afforded the present application, and are therefore not available as prior art under 35 U.S.C. 102(a)(l). Applicant therefore respectfully submits that the present rejection of the independent claims is moot in view of the reliance of the disqualified Ware reference (Remarks p. 9).
Examiner respectfully disagrees. The arguments with respect to the cited prior art as not available as prior art under 35 USC 102(a)(1) have been considered but are not persuasive as the arguments with respect to the priority have been considered and are not persuasive. See response above to Arguments with respect to the Priority. Therefore, the cited prior art qualifies as prior art and thus the 103 rejection has been maintained.
Applicant asserts that, none of the cited references, alone or in combination, teach or reasonably suggest these limitations claim 1. For instance, the Office Action cites to Pareek as allegedly teaching "a decomposition circuit configured to: decompose the first operand into a first plurality of first operand values, and decompose the second operand into a second plurality of second operand values." See Office Action, at 4. In particular, the Office Action contends that the first plurality of first operand values are taught by the sign bits, exponents, and mantissa of Pareek. Pareek includes an "operand formatting circuit 606 [that] is configured to input the mantissas of the multiple multiplicands and combine the mantissas into a single multiplicand." In other words, the mantissas in registers 608/610 are not "operand values" that are generated from a decomposed operand, but are instead combined values corresponding to mantissas of multiple operands that are multiplied concurrently by a single multiplier (620) to generate one output (622) including multiple operand values.
Furthermore, the sign bits/exponent bits are not "multiplied with respective second operand values of [a] second plurality of second operand values" as required by the pending claims. As illustrated in FIG. 6, the sign bits are XORed at 632 and the exponent bits are added by adder 646. Thus, Pareek fails to disclose a number of significant limitations of Applicant's claim 1. The remaining cited references fail to cure this deficiency of Pareek (Remarks p. 9-10).
Examiner respectfully disagrees. The decomposed operands values are the decomposed values of the operands "weights 602" and "input activations 604" of which are decomposed into a plurality of operand values, "sign bit, exponent, mantissa" corresponding to the weight and "sign bit, exponent, mantissa" corresponding to the input activations. To the extent Applicant is arguing that the combined mantissa is unlike operand values due to it being “combined values”, the mantissas from both input activations 604 and weights 602 still need to be extracted separately beforehand to be later combined (Pareek, [0041-0042]). It is unclear how solely the mantissas are the target in this argument as other aspects of plurality of first and second operand values, such as the signs and exponents of the weights and input activations are also encompassed in this mapping. Therefore, given the plain meaning of the claim language as based on the broadest reasonable interpretation, Pareek teaches the limitations.
Second, the language "multiplied with respective second operand values of [a] second plurality of second operand values" is disclosed by Pareek in [0043] as the operands (decomposed weights and input activations) are multiplied by the multiplier 620, corresponding to mantissas, and output. The claims, both independent claims 1, 12, and 20 and their dependent claims, do not specify that the sign/exponent bits are to be multiplied, merely “a respective first operand value of the first plurality of first operand values” with “a respective second operand value of the second plurality of second operand values”. Therefore, given the plain meaning of the claim language as based on the broadest reasonable interpretation, Pareek teaches the limitations.
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151