DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed has been entered. The amendment to the claims has restored benefit to the priority date for claims 1, 4-12, 14-20 and overcome the 35 USC 103 rejections. However, as necessitated by the amendment a new grounds of rejection is made, and claims 1-20 remain pending.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) and has restored benefit to the prior-filed applications, Application No. 16/139,093, Application No. 16/986,007 and U.S. Provisional Patent Application Serial No. 63/134,941, by amendment to the independent claims. Accordingly, claims 1, 4-12, 14-20 are now entitled to the benefit of the prior applications, and have an effective filing date of 23 September 2018.
Claim 2 is not entitled to the benefit of the prior applications. The disclosure of the prior-filed applications, Application No. 16/139,093, Application No. 16/986,007, and U.S. Provisional Patent Application Serial No. 63/134,941, fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. Claim 2 recites a decomposition circuit applying a Toom-Cook decomposition algorithm. Insufficient disclosure is provided from the prior-filed applications. Accordingly, claim 2 is not entitled to the benefit of the prior applications, and instead has an effective filing date of 17 June 2021.
Claims 3 and 13 are entitled to the benefit of the prior applications. The disclosure of U.S. Provisional Patent Application Serial No. 63/134,941 provides adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. Claims 3 and 13 recite decomposition. Accordingly, claims 3 and 13 are entitled to the benefit of the U.S. Provisional Patent Application Serial No. 63/134,941, and have an effective filing date of 07 January 2021.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the decomposition" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-12, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200089472 A1 Pareek et al. (hereinafter “Pareek”) in view of US 20040117422 A1 Debes et al. (hereinafter “Debes”).
Claims 1, 4-12, 14-20 are now entitled to the benefit of the prior applications, and have an effective filing date of 23 September 2018.
Regarding claim 1, Pareek teaches a multiplier circuitry comprising:
one or more storage register circuits (Fig. 6, 602, 604; [0040]) configured to store digital bits corresponding to first operand (Fig. 6, 602; [0040], floating point) and a second operand (Fig. 6, 604; [0040], floating point);
a plurality of multiplier circuits (Fig. 6, 620; [0043]) configured to receive a first plurality of first operand values (Fig. 6, sign bits, exponents, mantissa; [0043], [0046-0047],
w
i
s
,
w
i
(
e
)
,
w
i
m
), and a second plurality of second operand values (Fig. 6, sign bits, exponents, mantissa; [0043], [0046-0047],
x
j
s
,
x
j
(
e
)
,
x
j
m
),
wherein each multiplier circuit is configured to multiply to generate a plurality of partial results (Fig. 6, 622; [0043], four products known as mantissa products);
an accumulator circuit (Fig. 6, 638, 640; [0048] accumulator 638 sums the output from XOR 636 with value held in accumulation register 640) configured to accumulate the plurality of partial results using a format to generate a complete result of the format that is stored in the accumulator circuit ([0047] partial results further processed by XOR 636 that outputs a fixed point representation, which is inputted into accumulator 638 and [0048] further accumulated); and
a first conversion circuit (Fig. 6, 642; [0048]) configured to convert the complete result of the format into an output result of an output format ([0048] floating point).
Pareek discloses the claimed invention except for disclosing a plurality of multiplier circuits.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to substitute a multiplier circuit with a plurality of multiplier circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. See MPEP 2144.04(vi)(B).
Further, Pareek is silent with disclosing a first plurality of first operand values comprising at least a first higher-order component and a first lower order component and a second plurality of second operand values comprising at least a second higher-order component and a second lower order component; the multiplier circuits configured to multiply the first higher-order component with the second higher-order component and the first lower-order component with the second lower-order component; an intermediate format that comprises an extended length fixed point format, a first bit length of the extended length fixed point format being greater than a second bit length of at least one of the first operand or the second operand.
Debes discloses a first plurality of first operand values comprising at least a first higher-order component (Fig. 8A “A7” [0129]) and a first lower order component (Fig. 8A “A0” [0129]) and a second plurality of second operand values comprising at least a second higher-order component (Fig. 8A “B7” [0129]) and a second lower order component (Fig. 8A “B0” [0129]);
the multiplier circuits configured to multiply the first higher-order component with the second higher-order component (Fig. 8A “809” [0129]) and the first lower-order component with the second lower-order component (Fig. 8A “802” [0129]);
an intermediate format that comprises an extended length fixed point format (Fig. 2B extension registers “210” store 128-bits in one embodiment corresponding to integer registers “201” which concurrently store 128-bits [0070]), a first bit length of the extended length fixed point format being greater (Fig. 2B “210” 128-bits) than a second bit length of at least one format (Fig. 2B “210” 64-bit embodiment) of the first operand or the second operand.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Debes’ higher/lower order components and intermediate format features because they are in the claimed invention’s same field of endeavor multiply-adder circuitry ([0092]). Modifying with Debes’ features would have yielded predictable results of sizing the lengths of the operands and intermediate results before, during, and after computation as doing so would assist in distribution of operand values and reduce expensive memory accesses ([0014], [0086]). It would have been obvious one of ordinary skill in the art would have been able to implement the higher/lower order components and intermediate format features as a person of ordinary skill in the art would look to Debes’ features before the effective filing date to utilize an efficient method for data retrieval, operand distribution to derive the benefit of more efficiently performing calculations with reduced memory accesses.
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches further comprising:
a third conversion circuit (Fig. 6, 636; [0047-0048]; Note: “XOR” 636 performs same functionality of “conversion circuit” despite having a different name) configured to convert the plurality of partial results from a first format to the format before the accumulation ([0047] outputs in fixed point representation after performing XOR operation).
Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Debes discloses an intermediate format (Fig. 2B extension registers “210” store 128-bits in one embodiment corresponding to integer registers “201” which concurrently store 128-bits [0070]).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches further comprising:
a plurality of adders (Fig. 6, 626; [0046]) each configured to add respective first operand values and second operand values corresponding to exponent portions of the first operand and the second operand (Fig. 6, exponents
w
i
(
e
)
and
x
j
(
e
)
) to generate a plurality of exponent values ([0046] summed exponents of the exponents of the floating point operands); and
a plurality of shift circuits (Fig. 6, 628; [0046]) each configured to shift a respective partial result of the plurality of partial results before the accumulation based on a corresponding exponent value of the plurality of exponent values to generate a corresponding shifted partial result of a plurality of shifted partial results (Fig. 6, output of 628; [0046] left shifter 628 left shifts mantissa products by number of bits indicated by summed exponents).
Pareek discloses the claimed invention except for a plurality of adders and a plurality of shift circuits.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to substitute an adder for a plurality of adders and a shift circuit for a plurality of shift circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. See MPEP 2144.04(vi)(B).
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches further comprising:
a plurality of conversion circuits (Fig. 6, 636; [0047-0048] Note: “XOR” 636 performs same functionality of “conversion circuit” despite having a different name) each coupled to an output of a corresponding shift circuit (Fig. 6, XOR 636 coupled to left shifter 628 through concatenation 630) of the plurality of shift circuits and configured to convert the corresponding shifted partial result from the first format to the format before the accumulation (Fig. 6, output of 636; [0047] outputs in fixed point representation after performing XOR operation).
Pareek discloses the claimed invention except for a plurality of conversion circuits and a plurality of shift circuits.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to substitute a conversion circuit for a plurality of conversion circuits and a shift circuit for a plurality of shift circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. See MPEP 2144.04(vi)(B).
Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Debes discloses an intermediate format (Fig. 2B extension registers “210” store 128-bits in one embodiment corresponding to integer registers “201” which concurrently store 128-bits [0070]).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 7, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches a first format of at least one of the first operand or the second operand (Fig. 6, 602, 604; [0040], floating point).
Pareek is silent with explicitly disclosing is selected from the group consisting of an INT8 format, an INT16 format, a FP16 format and a FP32 format.
Debes discloses selected from the group consisting of an INT8 format, an INT16 format, a FP16 format, and a FP32 format ([0092]).
The motivation to combine provided with respect to claim 1.
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches the output format (see claim 1 mapping).
Although Pareek generally teaches the output format, they are silent with explicitly disclosing as a FP32 format.
Debes discloses a FP32 format ([0092]).
The motivation to combine with respect to claim 1 equally applies.
Regarding claim 9, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches wherein the conversion circuit (see claim 1 mapping) is further configured:
to convert the complete result of the format into the output result of the output format by truncating the complete result stored in the accumulator circuit based on the output format (Fig. 6, fixed-to-floating point conversion 642 converts accum. reg. 640 to yield output of 642; [0048] floating point).
Although Pareek teaches the converting, they are silent with disclosing converting by truncating. Pareek is silent to teaching an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Debes discloses an intermediate format (Fig. 2B extension registers “210” store 128-bits in one embodiment corresponding to integer registers “201” which concurrently store 128-bits [0070]); by truncating ([0108]).
The motivation to combine with respect to claim 1 similarly applies. In addition, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Debes’ truncation feature because modifying would have yielded predictable results of sizing the lengths of computational results before, during, and after computation, and thereby prevent errors in subsequent or final computations by preventing overflows ([0108]). It would have been obvious to one of ordinary skill in the art to implement the truncation feature as a person of ordinary skill in the art would look to Debes’ features before the effective filing date to utilize this feature to prevent errors in subsequent or final calculations, and memory issues with overflowed values.
Regarding claim 10, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches wherein the conversion circuit (see claim 1 mapping) is further configured:
to convert the complete result of the second format into the output result of the output format by truncating the complete result stored in the accumulator circuit (see claim 9 mapping) based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format.
Although Pareek teaches the converting, they are silent with disclosing converting by truncating; based at least in part on a defined output precision selected from the group consisting of a FP32 format, a FP64 format and a FP128 format; an intermediate format as described earlier in claim 1 that comprises an extended length fixed point format.
Debes discloses converting by truncating ([0108]) based at least in part on a defined output precision selected ([0140] for 64-bit values [0127]) from the group consisting of a FP32 format, a FP64 format ([0092]) and a FP128 format ([0070], [0096]); the intermediate format (Fig. 2B extension registers “210” store 128-bits in one embodiment corresponding to integer registers “201” which concurrently store 128-bits [0070]).
The motivation to combine with respect to claim 1 and 9 equally applies.
Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches wherein the accumulator circuit (see claim 1 mapping) is further configured:
accumulate the plurality of partial results from a smallest partial result among the plurality of partial results to a largest partial result among the plurality of partial results ([0047] partial results further processed by XOR 636 and outputs a fixed point representation, which is inputted into accumulator 638).
Although Pareek teaches the XOR circuit outputting an n-bit value, which is the width of the output of the concatenation circuit 630 to be accumulated in accumulator 638, they are silent with explicitly disclosing a range from smallest to largest partial results.
Debes discloses from a smallest partial result among the plurality of partial results to a largest partial result ([0104-0105]).
The motivation to combine with respect to claim 1 equally applies. In addition, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Debes’ ranging sizes of partial results feature because modifying would have yielded predictable results of sizing the lengths of computational results before, during, and after the computation and thereby prevent errors in subsequent or final computations by preventing overflows and underflows using clamping ([0104]). It would have been obvious to one of ordinary skill in the art to implement setting a range for intermediary or final computational results feature as a person of ordinary skill in the art would look to Debes’ features before the effective filing date to utilize this feature to prevent errors in subsequent or final calculations, and memory issues with overflowed or underflowed values.
Claims 12, 14-19 are directed to a method that would be practiced by the
device of claim 1, 4-7, 9, 11. All steps recited in claims 12, 14-19 are practiced by the device of claims 1, 4-7, 9, 11, respectively. The claims 1, 4-7, 9, 11 analysis equally applies to claims 12, 14-19, respectively.
Claim 20 is directed to a computer program product that would be executed by the device of claim 1. The claim 1 analysis equally applies.
Additionally, Pareek teaches:
a stored hardware description language program having sets of instructions, the instructions when executed produce a digital circuit ([0059-0061], [0066]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Debes as applied to claim 1 above, and further in view of Elia, Marcus. "Loss of Precision in Implementations of the Toom-Cook Algorithm". Dissertation, The University of Vermont. May, 2021. Chapter 7. pp. 79-98. (hereinafter “Elia”).
Accordingly, claim 2 is not entitled to the benefit of the prior applications, and instead has an effective filing date of 17 June 2021.
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Pareek teaches the decomposition circuit is configured to decompose the first operand and the second operand (see claim 1 mapping).
While Pareek teaches the decomposition of operands, they are silent with disclosing the type of algorithm performed to do so, and are specifically silent with disclosing such as a Toom-Cook decomposition algorithm.
Further, Pareek in view of Debes are silent with disclosing the type of algorithm performed to do so, and are specifically silent with disclosing such as a Toom-Cook decomposition algorithm.
Elia teaches a Toom-Cook decomposition algorithm (Pg. 6, Para. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Debes’ modified multiply-accumulate device with Elia’s Toom-Cook decomposition algorithm because they are in the claimed invention’s same field of endeavor of multiplication methods (Abstract). It would have been obvious to one of ordinary skill in the art to implement the decomposition algorithm, as variations of the decomposition are more suited for the types of formats used in computations (Pg. 14, Para. 2-3; Pg. 15, Para. 1). Making this modification would be beneficial, as based on the decomposition chosen, there are achievable speed ups in computation (Pg. 21, Para. 1; Pg. 15-20, Comparison of Toom-Cook Decompositions Graphs).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Debes as applied to claim 1 above, and further in view of US 20200097799 A1 Divakar et al. (hereinafter “Divakar”).
Accordingly, claim 3 is entitled to the benefit of the prior applications (U.S. Provisional Patent Application Serial No. 63/134,941), and has an effective filing date of 07 January 2021.
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated.
Pareek teaches a first operand and the second operand from a floating point format and the decomposition (see claim 1 mapping).
Pareek is silent with disclosing another conversion circuit configured to convert the operand and the other operand from a floating point format into an integer format prior to the decomposition.
Pareek in view of Debes are silent with disclosing another conversion circuit configured to convert the operand and the other operand from a floating point format into an integer format prior to the decomposition.
Divakar teaches a second conversion circuit (Fig. 4D, 485a-b, [0040]) configured to convert the first operand and the second operand from a floating point format into an integer format prior ([0040] allows given operands to be converted into any one of multiple different data formats prior to operation by configuration information, provided by the format manager block, to be fed to the multiplexer blocks 486a-b, Fig. 8A, 815, 820, [0053] of which data formats include floating point and integer (or other fixed point) where operands are modified to perform a computation in a particular format to obtain the result in a particular format; [0035] as an example the multiplier is capable of performing fixed point computations only) to the decomposition.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Debes’ multiply-accumulate device with Divakar’s conversion circuit because they are in the claimed invention’s same field of endeavor of multiply-accumulate devices ([0021]). Pareek teaches that its storage circuits (Fig. 6, 602, 604) store operands only in floating point format ([0040]). It would have been obvious to one of ordinary skill in the art to implement the conversion circuit, as Divakar teaches an operand can be converted to different data formats prior to computation ([0040]) as pairs of operands can differ in format type and even precision ([0038]). Making this modification would be beneficial, as by including the conversion circuit in Pareek in view of Debes’ architecture, Pareek in view of Debes’ device now has the capability to receive non-floating point formats values for processing, thus expanding its applications of use.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Pareek in view of Debes as applied to claim 1 above, and further in view of Donald E. Knuth. 1997. The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms. Addison-Wesley Longman Publishing Co., Inc., USA. (hereinafter “Knuth”).
Accordingly, claim 13 is entitled to the benefit of the prior applications (U.S. Provisional Patent Application Serial No. 63/134,941), and has an effective filing date of 07 January 2021.
Regarding claim 13, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Pareek teaches decompose the first operand and the second operand (see claim 1 mapping).
While Pareek teaches the decomposition of operands, they are silent with disclosing the type of algorithm performed to do so, and Pareek in view of Debes are specifically silent with disclosing applying a Toom-Cook decomposition algorithm.
Knuth discloses applying a Toom-Cook decomposition algorithm (p. 300 Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek in view of Debes’ modified multiply-accumulate device with Knuth’s Toom-Cook decomposition algorithm because they are in the claimed invention’s same field of endeavor of multiplication methods (p. 299 ¶1). It would have been obvious to one of ordinary skill in the art to implement this decomposition algorithm and yielded predictable results of performing multiplications (p. 300 Fig. 8). Making this modification would be beneficial as utilizing the Toom-Cook algorithm for high-precision decomposition would lead to considerably reduced execution times by optimizing multiplication operations (p. 302 Theorem B).
Response to Arguments
Priority. Applicant has successfully restored the benefit to the prior-filed applications for claims 1, 4-12, 14-20 due to the amendment of the claims for 23 September 2018.
Claim 2 is not entitled to the benefit of the prior applications and instead has an effective filing date of 17 June 2021.
Claims 3, 13 are entitled to the benefit of the prior applications (U.S. Provisional Patent Application Serial No. 63/134,941) and have an effective filing date of 07 January 2021.
35 USC 103. Applicant’s arguments, see Remarks p. 8, filed 06 July 2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 104 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Debes and in view of Knuth as necessitated by the amendment to independent claims 1, 12, and 20.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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