Attorney Docket Number: AD3337-US 111548-262287
Filing Date: 6/21/2021
Claimed Priority Date: none
Inventors: Ghani et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 02/18/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 02/18/2026 in reply to the previous Office action mailed on 11/25/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20, wherein claims 1-5 and 11-15 remain withdrawn from consideration.
Drawings
Quotes from the specification are from the published application US 2022/0406778.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a dielectric gate cap on the conductive fill material, as recited in claim 9, must be shown or the features canceled from the claims. No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, an oxidized portion of a sub-fin and horizontally stacked nanowires between the protruding portion of the sub-fin and a gate dielectric material layer, and between the horizontally stacked nanowires and the gate dielectric material layer, as recited in claim 10, must be shown or the features canceled from the claims. No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a) because they (e.g., figures 2-4) fail to show an oxidized portion of fins present between protruding portions of the fins and a gate dielectric material layer as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "114A" and "116" have both been used to designate the sides of a dielectric gate plug in figure 1E.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "7I" and "71" have both been used to designate figure 7I (see, e.g., par.0066/ll.7).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "706" and "706'" have both been used to designate recessed nanowires in figure 7J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “716” has been used to designate both a protective cap and cavity spacers in figure 7J.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “900” has been used to designate both an integrated circuit structure with self-aligned gate endcap (SAGE) walls and an integrated circuit structure without SAGE walls in figure 9(b) (see par.0105/ll.14-15).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “952” has been used to designate both a substrate and an isolation structure in figure 9(b) (see par.0105/ll.10).
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "1020" and "1020'" have both been used to designate topographic masking portions in figure 10.
The drawings (e.g., figures 1E and 10) are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: 108A, 116, and 1020'.
Corrected drawing sheets incompliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu (US 2022/0140097).
Regarding claim 6, Hsu (see, e.g., fig. 14) shows all aspects of the instant invention, including an integrated circuit structure 200B comprising:
a sub-fin (portion of 202 laterally between 230) having a portion protruding (protruding portion of 202) above a shallow trench isolation (STI) structure 230;
a plurality of horizontally stacked nanowires 215 over the sub-fin;
a gate dielectric material layer 282 over the protruding portion of the sub--fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer 284 over the gate dielectric material layer;
a conductive gate fill material 285 over the conductive gate layer; and
a dielectric gate plug 231 (see, e.g., par.0023/ll.3-5) laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires;
wherein:
the dielectric gate plug 231 is on the STI structure 230;
the gate dielectric material layer 282 and the conductive gate layer 284 are along a side of the dielectric gate plug;
the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug;
the gate dielectric material layer has an uppermost surface above an uppermost surface of the conductive gate fill material 285; and
the conductive gate layer 284 has an uppermost surface above the uppermost surface of the conductive gate fill material
It is noted that relative positional terms such as “uppermost” and “lowermost” are used to describe spatial relationships among structural features and are not contingent on a specific universally-applied reference orientation. Accordingly, when viewed from an orientation where “uppermost” is defined as closest to 0 and “lowermost” is defined as approaching infinity along the z-axis, the gate dielectric material layer has an “uppermost” surface above an “uppermost” surface of the conductive gate fill material and the conductive gate layer has an “uppermost” surface above the “uppermost” surface of the conductive gate fill material.
Regarding claim 7, Hsu (see, e.g., par.0025/ll.1-3) shows that the gate dielectric material layer 282 is a high-k gate dielectric layer.
Regarding claim 8, Hsu (see, e.g., par.0027/ll.8-16) shows that the conductive gate layer 284 is a workfunction metal layer.
Regarding claim 9, Hsu (see, e.g., fig. 14 and pars.0022/ll.29-32, par.0025/ll.17-20, and 0043/ll.5) shows that a dielectric gate cap 289 (e.g., TiO2) is on the conductive gate fill material 285.
Regarding claim 10, Hsu (see, e.g., figs. 3 and 14 and par.0024/ll.11-20) shows that an oxidized portion 280 of the sub-fin (portion of 202 laterally between 230) is between the protruding portion (protruding portion of 202) of the sub-fin and the gate dielectric material layer 282, and an oxidized portion of the horizontally stacked nanowires 215 is between the horizontally stacked nanowires and the gate dielectric material layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Colombeau (US 2021/0119021).
Regarding claim 6, Regarding claim 6, Hsu (see, e.g., fig. 14) shows an integrated circuit structure 200B comprising:
a sub-fin (portion of 202 laterally between 230) having a portion protruding (protruding portion of 202) above a shallow trench isolation (STI) structure 230;
a plurality of horizontally stacked nanowires 215 over the sub-fin;
a gate dielectric material layer 282 over the protruding portion of the sub--fin, over the STI structure, and surrounding the horizontally stacked nanowires;
a conductive gate layer 284 over the gate dielectric material layer;
a conductive gate fill material 285 over the conductive gate layer; and
a dielectric gate plug 231 (see, e.g., par.0023/ll.3-5) laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires
wherein:
the dielectric gate plug 231 is on the STI structure 230;
the gate dielectric material layer 282 and the conductive gate layer 284 are along a side of the dielectric gate plug;
the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug;
the gate dielectric material layer has an uppermost surface above an uppermost surface of the conductive gate fill material 285; and
the conductive gate layer 284 has an uppermost surface above the uppermost surface of the conductive gate fill material (viewed from an orientation where “uppermost” is defined as closest to 0 and “lowermost” is defined as approaching infinity along the z-axis)
Furthermore, Colombeau, in the same field of endeavor and in a similar device to Hsu, shows a conductive gate fill material 1125 over a conductive gate layer 1320, wherein Colombeau further shows embodiments wherein the conductive gate layer has an uppermost surface above an uppermost surface of the conductive gate fill material and wherein the conductive gate layer may not have an uppermost surface above an uppermost surface of the conductive gate fill material (see, e.g., Colombeau: figs. 12B-12C).
Colombeau is evidence showing that one of ordinary skill in the art would appreciate that having an uppermost surface of a conductive gate layer above an uppermost surface of a conductive gate fill material would be equivalent to not having an uppermost surface of a conductive gate layer above an uppermost surface of a conductive gate fill material, and that such differences would result in no unexpected changes in the performance of the device of Hsu. That is, the conductive gate layer and fill material dispositions of both Hsu and Colombeau would yield the predictable result of providing suitable conductive layers able to surround and encapsulate an insulating gate plug and capable of electrical interconnection with other conductive features in a semiconductor structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either an uppermost surface of a conductive gate layer above an uppermost surface of a conductive gate fill material, as taught by Colombeau and Hsu, or an uppermost surface of a conductive gate layer not necessarily above an uppermost surface of a conductive gate fill material, as taught by Colombeau, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable conductive layers able to surround and encapsulate an insulating gate plug and capable of electrical interconnection with other conductive features in a semiconductor structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Regarding claim 7, Hsu (see, e.g., par.0025/ll.1-3) shows that the gate dielectric material layer 282 is a high-k gate dielectric layer.
Regarding claim 8, Hsu (see, e.g., par.0027/ll.8-16) shows that the conductive gate layer 284 is a workfunction metal layer.
Regarding claim 9, Hsu (see, e.g., fig. 14 and pars.0022/ll.29-32, par.0025/ll.17-20, and 0043/ll.5) shows that a dielectric gate cap 289 (e.g., TiO2) is on the conductive gate fill material 285.
Regarding claim 10, Hsu (see, e.g., figs. 3 and 14 and par.0024/ll.11-20) shows that an oxidized portion 280 of the sub-fin (portion of 202 laterally between 230) is between the protruding portion (protruding portion of 202) of the sub-fin and the gate dielectric material layer 282, and an oxidized portion of the horizontally stacked nanowires 215 is between the horizontally stacked nanowires and the gate dielectric material layer.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Guha (US 2019/0393352).
Regarding claim 16, Hsu shows most aspects of the instant invention, including a specific integrated circuit structure (see paragraphs 18-19 above, wherein the specifics of the integrated circuit structure are considered to be repeated here). Hsu (see, e.g., par.0055) further discloses that one skilled in the art may further modify Hsu’s device within the scope of the device, but fails to specify that these modifications may include a computing device comprising a board and a component coupled to the board, wherein the component includes an integrated circuit structure. Guha, possessing a similar integrated circuit structure to Hsu, teaches that having a computing device, shown to house a board, and having a component (such as a processor) containing an integrated circuit structure may facilitate the processing of electronic data from registers and/or memory and the transformation of said electronic data into other electronic data that may also be stored in registers and/or memory (see, e.g., Guha: fig. 11 and pars.0118 and 0121/ll.8-9).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Hsu to include the computing device and included component of Guha, such that Hsu’s component comprises Hsu’s integrated circuit structure, as taught by Guha, so as to facilitate the processing, storing, and transformation of data from the device of Hsu.
Regarding claim 17, Guha (see, e.g., fig. 11) further shows a memory ROM coupled to the board.
Regarding claim 18, Guha (see, e.g., fig. 11) further shows a communication chip 1106 coupled to the board.
Regarding claim 19, Guha (see, e.g., par.0118) further shows that the component is a packaged integrated circuit die.
Regarding claim 20, Guha (see, e.g., pars. 0116 and 0118-0120) shows that the component may be selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu/Colombeau in view of Guha (2019/0393352).
Regarding claim 16, Hsu/Colombeau shows most aspects of the instant invention, including a specific integrated circuit structure (see paragraphs 26-29 above, wherein the specifics of the integrated circuit structure are considered to be repeated here). Hsu (see, e.g., par.0055) further discloses that one skilled in the art may further modify Hsu’s device within the scope of the device, but fails to specify that these modifications may include a computing device comprising a board and a component coupled to the board, wherein the component includes an integrated circuit structure. Guha, possessing a similar integrated circuit structure to Hsu, teaches that having a computing device, shown to house a board, and having a component (such as a processor) containing an integrated circuit structure may facilitate the processing of electronic data from registers and/or memory and the transformation of said electronic data into other electronic data that may also be stored in registers and/or memory (see, e.g., Guha: fig. 11 and pars.0118 and 0121/ll.8-9).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Hsu to include the computing device and included component of Guha, such that Hsu’s component comprises Hsu’s integrated circuit structure, as taught by Guha, so as to facilitate the processing, storing, and transformation of data from the device of Hsu.
Regarding claim 17, Guha (see, e.g., fig. 11) further shows a memory ROM coupled to the board.
Regarding claim 18, Guha (see, e.g., fig. 11) further shows a communication chip 1106 coupled to the board.
Regarding claim 19, Guha (see, e.g., par.0118) further shows that the component is a packaged integrated circuit die.
Regarding claim 20, Guha (see, e.g., pars. 0116 and 0118-0120) shows that the component may be selected from the group consisting of a processor, a communications chip, and a digital signal processor.
Response to Arguments
Applicant’s documents filed on 02/18/2026 have presented no arguments or amendments regarding the objections to the drawings presented in the Office action mailed on 11/25/2025. Accordingly, the objections to the drawings put forth in the Office action mailed on 11/25/2025 are maintained.
With regards to the claims, Applicant argues:
Applicant understands Hsu as disclosing the electrode layer 284 as having an uppermost surface at a same level as an uppermost surface of the electrode layer 285. As such, Applicant does NOT understand Hsu as disclosing the electrode layer 284 as having an uppermost surface above the uppermost surface of the electrode layer 285.
The Examiner responds:
Hsu shows these aspects of the claimed invention. See paragraphs 18 and 35 above, along with the comments stated in paragraph 19, which demonstrate that Hsu (see, e.g., fig. 14) shows that the conductive gate layer 284 has an uppermost surface above the uppermost surface of the conductive gate fill material 285.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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