Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-12, and 14-16 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini et al. (US 2019/0385977, hereinafter Elsherbini).
With respect to claim 1, Elsherbini discloses a microelectronic assembly (Fig. 5), comprising: a first integrated circuit (IC) die (114-1 & Para 00222) at a first level (104-1); a second IC die (114-2) at a second level (104-2); and a third IC die (114-3/114-10) at a third level (104-3), wherein: the second level is between the first level and the third level (104-2 is between 104-1 and 104-3), a first interface (124 - Para 0078) between the first level and the second level (124 between 104-1 & 104-2) is electrically coupled with first interconnects (130-1) having a first pitch (pitch of 130-1- Para 0028), the first interface comprising a hybrid bonding interface between the first IC die and the second IC die (Para 0038 – hybrid bonding); a second interface (124/148 between 104-2 & 104-3) between the second level and the third level is electrically coupled with second interconnects (155-1/155-2/155-3) having a second pitch (pitch of 155-3), the second interface comprising an interface (152 & 148 &122 – Para 0031) between the third IC die and the first IC die (Fig. 5).
Elsherbini in the same embodiment does not explicitly disclose that the second pitch is larger than the first pitch.
In another embodiment, Elsherbini discloses that pitch of the first, second interconnect structure can be different depending on density of first semiconductor structure (Para 0027-0028; 0040 and 0133) and therefore, the second pitch is shown to be larger than the first pitch (e.g. pitch of 155-3 is larger than 130-1).
Therefore, it would have been obvious to one an ordinary skilled in the art at the time of invention to modify Elsherbini’s disclosed invention and form interconnects with multiple pitches to achieve optimum density area of the semiconductor structure.
With respect to claim 2, Elsherbini discloses wherein at least one of the second IC die and the third IC die comprises a semiconductor interconnect bridge die having no active circuitry (Fig. 10 and Para 0103 -0104).
With respect to claim 3, Elsherbini discloses wherein at least one of the first IC die, the second IC die and the third IC die comprises another microelectronic assembly (Fig. 5 – third IC die comprises another microelectronic assembly).
With respect to claim 5, Elsherbini discloses wherein the microelectronic assembly is a processing element (PE) of a larger IC (Para 0078-0079).
With respect to claim 6, Elsherbini discloses wherein the second IC die (114-2) comprises an electrical interconnect circuit block coupling two different circuit blocks in the PE (114-2 comprises interconnect circuit block coupled with different circuit blocks), and the third IC die (114-3) comprises an electrical interconnect circuit block coupling the PE with another PE in the larger IC (114-3 comprises an interconnect connecting with 114-11).
With respect to claim 7, Elsherbini discloses wherein through-connections in the second level (Para 0099); and through-connections in the third level, wherein the through-connections in the second level are at a smaller pitch than the through-connections in the third level (Para 0038 and 0029).
With respect to claim 8, Elsherbini discloses wherein the first IC die is embedded in a first insulator in the first level (Para 0017; 0122); the second IC die is embedded in a second insulator in the second level (Para 0017; 0122); and the third IC die is embedded in a third insulator in the third level (Para 0017; 0122).
With respect to claim 9, Elsherbini discloses wherein the first insulator, the second insulator and the third insulator comprise a same material (Para 0038 and 0044).
With respect to claim 10, Elsherbini discloses a microelectronic assembly (Fig. 5), comprising:
a microelectronic assembly (Fig. 5) having at least three levels (104-1.. 104-4) with an IC die in each level (114-1/4; 114-2; 114-3/10; 114-11/12/13); and
a package substrate (102) coupled to the microelectronic assembly, wherein:
a first interface (124-Para 0078) between a first level (104-1) and a second level (104-2) in the at least three levels of the microelectronic assembly comprise interconnects (130-1) of a first pitch (pitch of 130-1- Para 0028), wherein the interconnects are in a hybrid bonding interface between a first IC die in the first level and a second IC die in the second level (Para 0038 – hybrid bonding);
a second interface (124/148) between the second level and a third level (124/148 between 104-2 & 104-3) in the at least three levels of the microelectronic assembly comprises interconnects (155-1/155-2/155-3) of a second pitch (pitch of 155-3), and
a third interface (Para 0035 – DTPS connection) between the microelectronic assembly and the package substrate comprises interconnects (150) of a third pitch (pitch of 150 – Para 0025).
Elsherbini in the same embodiment does not explicitly disclose that the interconnects have a pitch of less than 10 micrometers;
In another embodiment, Elsherbini discloses that the interconnects have a pitch of less than 10 micrometers (Para 0028; and 0142-0143 – 5 micron). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Elsherbini’s disclosed invention and form interconnects with multiple pitches to achieve optimum density area of the semiconductor structure.
With respect to claim 11, Elsherbini discloses wherein the first pitch is smaller than the second pitch (Para 0027-0028; 0040 and 0133 - e.g. pitch of 155-2 is larger than 130-1).
With respect to claim 12, Elsherbini discloses wherein the second pitch is smaller than the third pitch (Para 0027-0028; 0040 and 0133 – 155-3 is bigger than 155-2).
With respect to claim 14, Elsherbini discloses wherein the package substrate comprises a printed circuit board (PCB) (Para 0027 and 0033– PCB).
With respect to claim 15, Elsherbini discloses wherein at least one IC die in the microelectronic assembly comprises another microelectronic assembly (Fig. 5 – third IC die comprises another microelectronic assembly).
With respect to claim 16, Elsherbini discloses wherein at least one IC die in the microelectronic assembly comprises a passive semiconductor die without active circuitry (Fig. 10; Para 0103-0104).
With respect to claim 21, Elsherbini discloses wherein the first pitch is a pitch at the hybrid bonding interface between the first IC die and the second IC die (Para 0038), and the first pitch is less than 10 micrometers (Para 0028; and 0142-0143 – 5 micron).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini in view of DAS et al (US 2017/0092621, hereinafter DAS).
With respect to claim 13, Elsherbini does not explicitly disclose wherein the package substrate comprises an organic interposer with an embedded semiconductor die.
In an analogous art, DAS discloses the microelectronic assembly of claim 10, wherein the package substrate comprises an organic interposer with an embedded semiconductor die (e.g. DAS; Para 0058 – Option 2). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Elsherbini’s disclosed invention by having DAS’s disclosure in order to improve electrical performance of a semiconductor device.
Response to Arguments
Based on new ground of rejection, applicant’s arguments regarding amended claims are moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899