DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on June 10, 2025. Claims 1-4, 7-8, 10, and 16 have been amended. Claims 6, 14, and 18 have been canceled. Claims 21-23 have been added. Currently, claims 1-5, 7-13, 15-17, and 19-23 are pending.
Response to Arguments
Applicant’s arguments filed June 10, 2025 have been fully considered but they are not persuasive.
Regarding claims 1 and 10, the Applicants argue:
Lai (nor any of its combinations) discloses such an approach where the voltage regulator
output is coupled to a microelectronic element, opposite the RDL, other than the one having the TSV for coupling a power source. In Lai, the die with the TSV supplying power has its voltage controlled by a voltage regulator die to which the power is supplied by the TSV. See Lai, 8:5-20.
The Examiner responds:
The Examiner respectfully disagrees. As set forth in the rejection below, Lai teaches, in Fig. 9, that the voltage regulator output (150) is coupled to a first microelectronic element (110 on the right) and a second microelectronic element (110 on the left) (col. 8, lines 5-20), as is required by Applicant's claims. As a result, the rejection of claims 1-5, 7-13, and 15 is maintained.
Regarding claim 16, the Applicants argue:
The voltage regulator is coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the second surface of the first microelectronic component. The output of the voltage regulator is electrically coupled to a third conductive pathway in the RDL coupled to a third microelectronic component on the same side of the RDL as the voltage regulator. Lai (nor any of its combinations) discloses such an approach. In Lai, the die with the TSV supplying power has its voltage controlled by a voltage regulator die to which the power is supplied by the TSV. See Lai, 8:5-20.
The Examiner responds:
The Examiner respectfully disagrees. As set forth in the rejection below, Lai, as modified by Zhai, teaches, in Figure 13 of Lai, that the second conductive pathway (142 on the left connecting 110 with 150) electrically couples the TSV (in 110), the second microelectronic component (150), and the second surface of the first microelectronic component (110) (see Fig. 13 of Lai); and that the output of the voltage regulator (Lai; 150; Fig. 13; col. 8, lines 5-20) is electrically coupled to a third conductive pathway in the RDL (Zhai; 132; Figs. 4 and 16) coupled to a third microelectronic component (Zhai; 116; Fig. 16; col. 5, lines 20-30) on the same side of the RDL as the voltage regulator, as is required by Applicant's claims. As a result, the rejection of claims 16-17 and 19-23 is maintained.
All other arguments have been fully addressed in prior Office Actions or in the rejections set forth below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 recites the limitation “the second surface of the third microelectronic component.” There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, the term will be treated as “a surface of the third microelectronic component opposing a first surface electrically coupled to the second surface of the RDL” (see [0263] of the specification).
Claim 8, because it is dependent on claim 2, inherit the deficiency of claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801).
Regarding claim 1, Lai teaches, in Figure 9 separately, a microelectronic assembly, comprising: a package substrate (170), having a surface (171), including a first conductive pathway (172) electrically coupled to a power source (col. 4, lines 50-60);
a first microelectronic component (110 on the right), having a first surface (115) electrically coupled to the surface of the package substrate and an opposing second surface (112), embedded in an insulating material (130, col. 7, lines 1-10) on the surface of the package substrate and including a through-substrate via (TSV) (120, labeled in Figs. 8A-8B) electrically coupled to the first conductive pathway (172);
a second microelectronic component (110 on the left), having a first surface (115) electrically coupled to the second surface of the package substrate and an opposing second surface (112), embedded in the insulating material (130);
a redistribution layer (RDL) (140), having a first surface (141) on the insulating material and an opposing second surface (143), including a second conductive pathway (142, labeled in Fig. 6) electrically coupled to the TSV; and
a third microelectronic component (150) at the second surface of the RDL and electrically coupled to the second conductive pathway (142), wherein the second conductive pathway electrically couples the TSV and the third microelectronic component (col. 8, lines 5-20), and wherein the third microelectronic component comprises a voltage regulator (col. 8, lines 5-15).
Lai, in Fig. 9 separately, does not explicitly teach that the third microelectronic component has an output electrically coupled to a third conductive pathway in the RDL coupling the output to the second surface of the second microelectronic component.
Lai, in Fig. 8B separately, teaches that the third microelectronic component (150) has an output electrically coupled to a third conductive pathway in the RDL (col. 8; lines 55-65; portion of 120 extended in layer 140) coupling the output to the second surface of the second microelectronic component (top surface of 110 on the left).
Lai teaches that its embodiments can be combined to provide further embodiments (col. 3, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the embodiment of Figure 9 with the third conductive pathway of Figure 8B, since Lai teaches that its embodiments can be combined to provide further embodiments.
Regarding claim 3, Lai teaches the limitations of claim 1. Lai further teaches that the power source is on the package substrate (col. 4, lines 50-60).
Regarding claim 10, Lai teaches, in Figure 9 separately, a microelectronic assembly, comprising: a circuit board including a power source (col. 4, lines 50-60);
a package substrate (170), having a first surface (171) and an opposing second surface (173), on the circuit board (col. 4, lines 50-60) and including a first conductive pathway (172, labeled in Fig. 9) electrically coupled to the power source at the first surface of the package substrate (col. 4, lines 50-60);
a first microelectronic component (100 on the right), having a first surface (115) electrically coupled to the second surface of the package substrate and an opposing second surface (112), embedded in an insulating material (130; col. 7, lines 1-10) on the second surface of the package substrate and including a through-substrate via (TSV) (120, labeled in Figs. 8A-8B) electrically coupled to the first conductive pathway (172);
a second microelectronic component (110 on the left), having a first surface (115) electrically coupled to the second surface of the package substrate and an opposing second surface (112), embedded in the insulating material (130);
a redistribution layer (RDL) (140), having a first surface (141) on the insulating material and an opposing second surface (143), including a second conductive pathway (142, labelled in Fig. 6) electrically coupled to the TSV; and
a third microelectronic component (150) at the second surface of the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV and the third microelectronic component (col. 8, lines 5-20), and wherein the third microelectronic component comprises a voltage regulator (col. 8, lines 5-15).
Lai, in Fig. 9 separately, does not explicitly teach that the third microelectronic component has an output electrically coupled to a third conductive pathway in the RDL coupling the output to the second surface of the second microelectronic component.
Lai, in Fig. 8B separately, teaches that the third microelectronic component (150) has an output electrically coupled to a third conductive pathway in the RDL (col. 8; lines 55-65; (portion of 120 extended in layer 140) coupling the output to the second surface of the second microelectronic component (top surface of 110 on the left).
Lai teaches that its embodiments can be combined to provide further embodiments (col. 3, lines 35-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the embodiment of Figure 9 with the third conductive pathway of Figure 8B, since Lai teaches that its embodiments can be combined to provide further embodiments.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Yudanov (US 10529677).
Regarding claim 2, Lai teaches the limitations of claim 1. Lai does not explicitly teach a fourth microelectronic component at the second surface of the third microelectronic component and electrically coupled to the third conductive pathway.
In a similar field of endeavor, Yudanov teaches, in Fig. 8, a fourth microelectronic component (166, labelled in Fig. 1) at the second surface (top surface) of the third microelectronic component (179) (col. 3, lines 45-55) and electrically coupled to the third conductive pathway (col. 3, lines 50-67), “for ultimate supply to the chips” (col. 2, lines 10-15; col. 3, lines 45-55).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectric assembly of Lai with the fourth microelectronic component of Yudanov, in order to deliver power to microelectronic components.
Regarding claim 8, Lai in view of Yudanov teaches the limitations of claim 2. Yudanov further teaches that the fourth microelectronic component (166) is an inductor (col. 3, lines 45-55).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Park et al. (US 11538801 B2).
Regarding claim 4, Lai teaches the limitations of claim 1. Lai further teaches, in Fig. 9, that the surface (173) of the package substrate is a second surface and the package substrate further includes an opposing first surface (171).
Lai does not explicitly teach a capacitive element at the first surface of the package substrate and electrically coupled to the first conductive pathway.
In a similar field of endeavor, Park teaches, in Fig. 2, a capacitive element (150; col. 12, lines 5-10) at the first surface (bottom surface) of the package substrate (1; col. 2, lines 60-67) and electrically coupled to the first conductive pathway (133; col. 3, lines 5-15), in order to “provide semiconductor packages with small thicknesses” (col. 12, lines 5-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Lai in view of Zhai with the capacitive element of Park, in order to provide semiconductor packages with small thicknesses.
Claims 5 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Lee et al. (US 10985154).
Regarding claim 5, Lai teaches the limitations of claim 1, as discussed above. Lai teaches that the first microelectronic component is a “logic/SOC die including an active component(s) such as, but not limited to, a microprocessor, memory, RF transceiver, and mixed-signal component” (col. 5, lines 45-55).
Lai does not explicitly teach that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.
In a similar field of endeavor, Lee teaches wherein the first microelectronic component (326, see Fig. 41B) is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor (col. 208, lines 10-20), in order to “to lower down the barrier for implementing the innovation in the semiconductor IC chips using the advanced and powerful semiconductor technology nodes or generations” (col. 2, lines 1-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first microelectronic component of Lai with the first microelectronic component of Lee, in order to lower the barrier for implementing the innovation in the semiconductor IC chips using the advanced and powerful semiconductor technology nodes or generations.
Regarding claim 12, Lai teaches the limitations of claim 10. Lai further teaches that the first microelectronic component is a “logic/SOC die including an active component(s) such as, but not limited to, a microprocessor, memory, RF transceiver, and mixed-signal component” (col. 5, lines 45-55).
Lai does not explicitly teach that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.
In a similar field of endeavor, Lee teaches wherein the first microelectronic component (326, see Fig. 41B) is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor (col. 208, lines 10-20), in order to “to lower down the barrier for implementing the innovation in the semiconductor IC chips using the advanced and powerful semiconductor technology nodes or generations” (col. 2, lines 1-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first microelectronic component of Lai with the first microelectronic component of Lee, in order to lower the barrier for implementing the innovation in the semiconductor IC chips using the advanced and powerful semiconductor technology nodes or generations.
Regarding claim 13, Lai, as modified by Lee, teaches the limitations of claim 12, as discussed above. Lai further teaches wherein the second microelectronic component (see Fig. 9, 110 on the left) is a die including input/output circuitry (col. 5, lines 45-55).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of DiBene, II et al. (US 7245507).
Regarding claim 7, Lai teaches the limitations of claim 1, as discussed above. Lai does not explicitly teach wherein the voltage regulator is configured to convert a low current high voltage signal to a low voltage high current signal.
In a similar field of endeavor, DiBene, II teaches a voltage regulator (206) configured to convert a low current high voltage signal to a low voltage high current signal (col. 3, lines 30-45), for the purpose of “providing power to a component such as a processor while providing an integrated approach to managing thermal dissipation and electromagnetic interference” (col. 2, lines 25-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator of Lai with the voltage regulator of DiBene, II, in order to provide power to a component such as a processor while providing an integrated approach to managing thermal dissipation and electromagnetic interference.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Yu et al. (US 9831148).
Regarding claim 9, Lai teaches the limitations of claim 1, as discussed above. Lai does not explicitly teach a heat transfer structure at the second surface of the RDL.
In a similar field of endeavor, Yu teaches a heat transfer structure (78; see Fig. 20; col. 7, lines 60-67 – col. 8, lines 1-5) at the second surface of the RDL (48) (see Fig. 20), because “[i]n integrated circuits, some circuit components such as System-On-Chip (SOC) dies and Central Processing Units (CPU) have high requirement to the Input/output (IO) and power consumption,” “a plurality of voltage regulators may be connected to the CPU chip and the SOC dies to provide power,” and a heat spreader would move away the heat from the high power consumption (col. 1, lines 15-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Lai with the heat transfer structure of Yu, because System-On-Chip (SOC) dies and Central Processing Units (CPU) have high requirement to the Input/output (IO) and power consumption, a plurality of voltage regulators may be connected to the CPU chip and the SOC dies to provide power, and a heat spreader would move away the heat from the high power consumption.
Claims 11, 15, 16, 19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Zhai et al. (US 9633974).
Regarding claim 11, Lai teaches the limitations of claim 10. Lai further teaches a fourth microelectronic component (300) at the second surface of the RDL (see Fig. 13).
Lai does not teach that the fourth microelectronic component is electrically coupled to the second conductive pathway.
In a similar field of endeavor, Zhai teaches that the fourth microelectronic component (116; see Fig. 16; col. 5, lines 20-30) is electrically coupled to the second conductive pathway (132, see Figs. 4 and 16), because “the current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces” (col. 1, lines 10-20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the fourth microelectronic component of Lai with the fourth microelectronic component of Zhai, because the current market demand for portable and mobile electronic devices requires the integration of more performance and features into increasingly smaller spaces.
Regarding claim 15, Lai, as modified by Zhai, teaches the limitations of claim 11, as discussed above. Lai further teaches wherein the fourth microelectronic component (300) is an inductor or a capacitive element (col. 7, lines 55-60).
Regarding claim 16, Lai teaches, in Figure 13 separately, a microelectronic assembly, comprising: a package substrate (170), having a surface (171), including a first conductive pathway (172, labelled in Fig. 9) electrically coupled to a power source (col. 4, lines 50-60);
a first microelectronic component (110), having a first surface (115) electrically coupled to the surface of the package substrate and an opposing second surface (112), embedded in an insulating material (130, col. 7, lines 1-10) on the surface of the package substrate and including a through-substrate via (TSV) (120) electrically coupled to the first conductive pathway;
a redistribution layer (RDL) (140), having a first surface (141) on the insulating material and an opposing second surface (143), including a second conductive pathway (142 on the left connecting 110 with 150) electrically coupled to the TSV;
a second microelectronic component (150) at the second surface of the RDL, and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the second surface of the first microelectronic component, wherein the second microelectronic component comprises a voltage regulator (col. 8, lines 5-15) having an output electrically coupled to a third conductive pathway (142 on the right connecting 110 with 150) in the RDL; and
a third microelectronic component (300) at the second surface of the RDL (see Fig. 13).
Lai does not explicitly teach that the third microelectronic component is electrically coupled to the third conductive pathway.
In a similar field of endeavor, Zhai teaches that the third microelectronic component (116; see Fig. 16; col. 5, lines 20-30) is electrically coupled to the third conductive pathway (132, see Figs. 4 and 16), because “the current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces” (col. 1, lines 10-20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the third microelectronic component of Lai with the third microelectronic component and third conductive pathway of Zhai, because the current market demand for portable and mobile electronic devices requires the integration of more performance and features into increasingly smaller spaces.
Regarding claim 19, Lai, as modified by Zhai, teaches the limitations of claim 16. Lai further teaches that the third microelectronic component (300) is an inductor (col. 7, lines 55-60).
Regarding claim 21, Lai, as modified by Zhai, teaches the limitations of claim 16. Lai further teaches that the power source is on the package substrate (col. 4, lines 50-60).
Regarding claim 22, Lai, as modified by Zhai, teaches the limitations of claim 16. Lai further teaches that the surface (173) of the package substrate is a second surface and the package substrate further includes an opposing first surface (171), and further comprising:
a circuit board electrically coupled to the first surface of the package substrate, wherein the power source is on the circuit board (col. 4, lines 50-60).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Zhai et al. (US 9633974), and further in view of Lee et al. (US 10985154).
Regarding claim 17, Lai, as modified by Zhai, teaches the limitations of claim 16, as discussed above. Lai further teaches that the first microelectronic component is a “logic/SOC die including an active component(s) such as, but not limited to, a microprocessor, memory, RF transceiver, and mixed-signal component” (col. 5, lines 45-55).
Lai does not explicitly teach that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor.
In a similar field of endeavor, Lee teaches wherein the first microelectronic component (326, see Fig. 41B) is a central processing unit, a graphics processing unit, a digital signal processor, an application specific integrated circuit, a server processor, or a crypto processor (col. 208, lines 10-20), in order to “to lower down the barrier for implementing the innovation in the semiconductor IC chips using the advanced and powerful semiconductor technology nodes or generations” (col. 2, lines 1-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first microelectronic component of Lai with the first microelectronic component of Lee, in order to lower the barrier for implementing the innovation in the semiconductor IC chips using the advanced and powerful semiconductor technology nodes or generations.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Zhai et al. (US 9633974), and further in view of Yu et al. (US 9831148).
Regarding claim 20, Lai, as modified by Zhai, teaches the limitations of claim 16, as discussed above. Lai does not explicitly teach a heat transfer structure at the second surface of the RDL.
In a similar field of endeavor, Yu teaches a heat transfer structure (78; see Fig. 20; col. 7, lines 60-67 – col. 8, lines 1-5) at the second surface of the RDL (48) (see Fig. 20), because “[i]n integrated circuits, some circuit components such as System-On-Chip (SOC) dies and Central Processing Units (CPU) have high requirement to the Input/output (IO) and power consumption,” “a plurality of voltage regulators may be connected to the CPU chip and the SOC dies to provide power,” and a heat spreader would move away the heat from the high power consumption (col. 1, lines 15-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Lai with the heat transfer structure of Yu, because System-On-Chip (SOC) dies and Central Processing Units (CPU) have high requirement to the Input/output (IO) and power consumption, a plurality of voltage regulators may be connected to the CPU chip and the SOC dies to provide power, and a heat spreader would move away the heat from the high power consumption.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 9679801) in view of Zhai et al. (US 9633974), and further in view of Park et al. (US 11538801 B2).
Regarding claim 23, Lai, as modified by Zhai, teaches the limitations of claim 22. Lai as modified by Zhai does not explicitly teach a capacitive element at the first surface of the package substrate and electrically coupled to the first conductive pathway.
In a similar field of endeavor, Park teaches, in Fig. 2, a capacitive element (150; col. 12, lines 5-10) at the first surface (bottom surface) of the package substrate (1; col. 2, lines 60-67) and electrically coupled to the first conductive pathway (133; col. 3, lines 5-15), in order to “provide semiconductor packages with small thicknesses” (col. 12, lines 5-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the microelectronic assembly of Lai in view of Zhai with the capacitive element of Park, in order to provide semiconductor packages with small thicknesses.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893