DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 14 and 15 have been cancelled; claims 1, 10, 16-17, and 18 have been amended; and claims 1-13 and 16-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 2012/0114340 A1, hereinafter “Sugiyama”) in view of Yamasaki et al. (US 2004/0183187 A1, hereinafter “Yamasaki”).
In regards to claim 1, Sugiyama discloses (See, for example, Fig. 1) package, comprising:
a glass core (FPC10) having a first side (Top Surface of FPC) and a second side (Bottom Surface Of FPC) opposite the first side (Top Surface of FPC);
a first plurality of conductive structures (10S, 10G1, 10G2, MSL) extending through the glass core (FPC10) from the first side to the second side,
wherein a first one of the first plurality of conductive structures comprises a signal trace (10S) and a second one of the first plurality of conductive structures comprises a ground reference (10G1, 10G2, MSL),
Sugiyama is silent about a build-up layer on the glass core, the build-up layer separate and distinct from the glass core; and
a second plurality of conductive structures
Yamasaki while disclosing semiconductor device substrate teaches (See, for example, annotated Fig. 3 included below) a build-up layer (46, See, for example, Figs. 9B and 9C) on the glass core (30), the build-up layer (46, See, for example, Figs. 9B and 9C) separate and distinct from the glass core (30); and
a second plurality of conductive structures (28A, 28B) (46), wherein a first one of the second plurality of conductive structures comprises a signal trace (28B) and a second one of the second plurality of conductive structures comprises a ground reference (28A), the signal trace (28B) in the build-up layer (46) coupled to the signal trace (34B) in the glass core (30), and the ground reference (28A) in the build-up layer (46) coupled to the ground reference (34A) in the glass core (30).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Sugiyama by Yamasaki because this would increase the heat radiation efficiency of the component, and the reliability of the semiconductor device.
In regards to claim 10, Sugiyama discloses (See, for example, Fig. 1) a package comprising: a buildup layer comprising:
a first plurality of conductive vias (10S, 10G1, 10G2, MSL);
wherein one of the conductive vias comprises a signal trace (10S) and another plurality of the conductive vias comprise a ground reference (10G1, 10G2, MSL),
wherein the other plurality of conductive vias that comprise the ground reference (10G1, 10G2, MSL) surround the conductive via that comprise the signal trace (11b, 11e) and controls an impedance of the conductive via that comprise the signal trace (See, for example, Par [0060], and also Fig. 9).
Sugiyama is silent about
a plurality of conductive vias in the buildup layer;
a glass core comprising:
a first side and a second side opposite the first side; a plurality of conductive structures extending through the glass core from the first side
to the second side;
wherein one of the conductive structures comprises a signal trace and another of the conductive structures comprises a ground reference, wherein the conductive structure that comprises the ground reference controls an impedance of the conductive structure that comprises the signal trace; and
wherein a second side of the buildup layer is coupled with the first side of the glass core,
wherein one of the conductive structures of the glass core that comprises the signal trace is electrically coupled with one of the conductive vias of the buildup layer that comprises the signal
trace, and wherein one of the conductive structures of the glass core that comprises the ground
reference is electrically coupled with one of the conductive vias of the buildup layer that comprises the ground reference.
Yamasaki discloses (See, for example, Fig. 9C)
a plurality of conductive vias (28A, 28B, See, for example, annotated Fig. 3 included below) in the buildup layer (46, See for example, annotated Fig. 3 included below); a glass core (30) comprising:
a first side and a second side opposite the first side (Sides facing build-up layers 35/37, and 46, See, for example, Figs. 9A and 9B); a plurality of conductive structures (34A, 34B) extending through the glass core (30) from the first side to the second side;
wherein one of the conductive structures (34A, 34B) comprises a signal trace (34B) and another
of the conductive structures (34A, 34B) comprises a ground reference (34A), wherein the
conductive structure that comprises the ground reference (34A) controls an impedance of the
conductive structure that comprises the signal trace (34B); and
wherein a second side of the buildup layer (46) is coupled with the first side of the glass core (30), wherein one of the conductive structures (34A, 34B) of the glass core (30) that comprises the signal trace (34B) is electrically coupled with one of the conductive
vias of the buildup layer (46) that comprises the signal trace (28B), and wherein one of the
conductive structures (34A, 34B) of the glass core (30) that comprises the ground
reference (34A) is electrically coupled with one of the conductive vias of the buildup layer (46) that comprises the ground reference (28A).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Sugiyama by Yamasaki because this would increase the heat radiation efficiency of the component, and the reliability of the semiconductor device.
In regards to claim 2, Sugiyama as modified above discloses (See, for example, Fig. 9C, Yamasaki) the first one of the first plurality of conductive structures is a conductive via (See, 34A, 34B).
In regards to claim 3, Sugiyama discloses (See, for example, Fig. 1) the conductive via is a selected one of: conformally plated or filled (determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production)
In regards to claim 4, Sugiyama as modified above discloses (See, for example, Fig. 9C, Yamasaki) a shape of the first one of the first plurality conductive structure (34A, 34B) is a selected one of: a circle, a rectangle, a polygon, or an irregular shape.
In regards to claim 5, Sugiyama discloses (See, for example, Fig. 1) the second one of the first plurality of conductive structures (10G1, 10G2, MSL) is located on three sides of the first one of the first plurality of conductive structures.
In regards to claim 6, Sugiyama discloses (See, for example, Fig. 1) that a third one of the first plurality of conductive structure, wherein the third one of the first plurality of conductive structures comprises the ground reference (10G1, 10G2, MSL); and
wherein the second and third ones of the first plurality of conductive structures (See, for example, 10G1 and 10G2) are on opposite sides of the first one of the first plurality of conductive structures (10S).
In regards to claim 7, Sugiyama discloses (See, for example, Fig. 5) that a third one of the first plurality of conductive structure, wherein the third one of the first plurality of conductive structures comprises a signal trace (20Sc2); and wherein the second one of the first plurality of conductive structures (20Gc1, 20Gc2, 20Gc3) at least partially surrounds the first and third ones of the first plurality of conductive structures (20Sc1) (20Sc2).
In regards to claim 8, Sugiyama discloses (See, for example, Fig. 1) the second one of the first plurality of conductive structures (10G1, 10G2, MSL) includes a selected one of: a strip line or a microstrip (MSL).
In regards to claim 9, Sugiyama disclose all limitations of claim 1 above except that the first plurality of conductive structures include copper.
It is readily known in the manufacturing of electrical wirings to use copper for the purpose of achieving low electrical resistance and material cost.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use copper for the conductive structure because it is readily known in the manufacturing of electrical wirings to use copper for the purpose of achieving low electrical resistance and material cost. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regards to claim 11, Sugiyama discloses (See, for example, annotate Fig. 1 attached below) the other plurality of the conductive vias that comprise the ground reference (10G1, 10G2) are coupled with an antipad (100).
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In regards to claim 12, Sugiyama discloses (See, for example, Fig. 1) the antipad (100) is not concentric around the conductive vias.
In regards to claim 13, Sugiyama as modified above discloses (See, for example, Fig. 9C, Yamasaki) the conductive via that comprise the signal trace is a first conductive via the comprises a first signal trace (34B, left side); and further comprising a second conductive via that comprises a second signal trace (34B, right side), the first conductive via and the second conductive via separated by one of the conductive vias that comprise the ground reference (34A), wherein the second conductive via (34B, right side) is isolated from the antipad.
In regards to claim 14, Sugiyama disclose (See, for example, Fig. 1) a glass core comprising: a first side (Top Surface of FPC) and a second side (Bottom Surface of FPC) opposite the first side; a plurality of conductive structures extending through the glass core (FPC10) from the first side (Top Surface of FPC) to the second side (Bottom Surface of FPC); wherein one of the conductive structures comprises a signal trace (10S) and another of the conductive structures comprises a ground reference (10G1, 10G2, MSL), wherein the conductive structure that comprises the ground reference (10G1, 10G2, MSL) controls an impedance of the conductive structure (See, for example, Par [0060], and also Fig. 9) that comprises the signal trace (10S); and wherein a second side of the buildup layer is coupled with the first side of the glass core (the glass core and the buildup layer are the same structure and therefore meets the limitation).
In regards to claim 16, Sugiyama discloses (See, for example, Fig. 1) a shape of the conductive structure that comprises a signal trace (10S) in the glass core is a selected one of: a circle, a rectangle, a polygon, or an irregular shape (comprise rectangle).
In regards to claim 17, Sugiyama discloses (See, for example, Fig. 1) that the conductive structure that comprises the ground reference (10G1, 10G2, MSL) is located on at least two sides of the conductive structure that carries the signal (10S).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama in view of Hareyama (US 2017/0154860 A1, hereinafter “Hareyama”) and Yamasaki.
In regards to claim 18, Sugiyama discloses (See, for example, Fig.1) an integrated circuit package, comprising:
a glass core (FPC10) having a first side (Top Surface of FPC) and a second side (Bottom Surface Of FPC) opposite the first side (Top Surface of FPC);
a first conductive structure (10S) extending through the glass core from the first side (Top Surface of FPC) to the second side (Bottom Surface Of FPC);
a second conductive structure reference (10G1, 10G2, MSL) adjacent to the first conductive structure (10S), the second conductive structure reference (10G1, 10G2, MSL) extending through the glass core (FPC10) from the first side (Top Surface of FPC) to the second side (Bottom Surface Of FPC);
wherein the first conductive structure (10S) has a circular cross section;
the first conductive structure comprising a signal trace (10S);
wherein the second conductive structures (10G1, 10G2, MSL) has a non-circular cross section; and
wherein the second structure conductive structure (10G1, 10G2, MSL) comprises a ground plane.
Sugiyama is silent about the first conductive structure having a circular cross section.
Hareyama while disclosing a semiconductor device teaches (See, for example, Fig. 5) the first conductive structure (23) having a circular cross section (See also, Par [0076]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Sugiyama by Hareyama because this would help achieve impedance control in the semiconductor device using a glass core. Furthermore, it has been held that a configuration of the claimed a circular cross section was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed circular cross section was significant. See, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)
Sugiyama is silent about a build-up layer on the glass core, the build-up layer separate and distinct from the glass core; and
a plurality of conductive structures in the build-up layer, wherein a first one of the plurality of conductive structures comprises a signal trace and a second one of the plurality of conductive structures comprises a ground reference, the signal trace in the build-up layer coupled to the signal trace in the glass core, and the ground reference in the build-up layer coupled to the ground reference in the glass core.
Yamasaki discloses (See, for example, Fig. 9C)
a build-up layer (46, See, for example, Fig. 9B) on the glass core (30), the build-up layer (46) separate and distinct
from the glass core (30); and
a plurality of conductive structures (28A, 28B, See annotated Fig. 3 included below) in the build-up layer (46, See annotated Fig. 3 included below), wherein
a first one of the plurality of conductive structures (28A, 28B) comprises a signal trace (28B) and a second one of the plurality of conductive structures (28A, 28B) comprises a ground
reference (28A), the signal trace (28B) in the build-up layer (46) coupled to the signal trace (34B) in the glass core (30), and the ground reference (28A) in the build-up layer (46) coupled to the ground reference (34A) in the glass core (30).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Sugiyama by Yamasaki because this would increase the heat radiation efficiency of the component, and the reliability of the semiconductor device.
In regards to claim 19, Sugiyama as modified above discloses (See, for example, Fig. 1, Hareyama) the second conductive structure (22-1, 22-2) has one of a rectangular, a polygonal, or an irregular cross section.
In regards to claim 20, Sugiyama as modified above discloses (See, for example, Fig. 5, Sugiyama) that a third conductive structure (20Gc3) in the glass core, wherein the first conductive structure (20SC2) is between the second conductive structure (20GC2) and the third conductive structure (20Gc3), wherein the third conductive structure (20Gc3) has a non-circular cross section, and wherein the third conductive structure comprises a ground plane.
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Response to Arguments
Applicant' s arguments with respect to the new amendment in claims 1, 10 and 18 have been considered and are addressed in the rejection stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893