Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RCE, received 10/29/2025, has been entered.
Claims 1-20 are presented for examination. Claims 8-15 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Misaka et al. (US Pub. No. 2011/0272815 A1), hereafter referred to as Misaka.
As to claim 1, Misaka discloses an integrated circuit structure (fig 6, [0093]), comprising:
a first gate line along a first direction (see annotated fig 6 below);
a second gate line parallel with the first gate line along the first direction (see annotated fig 6 below);
a third gate line extending between and continuous with a midsection of the first gate line and a midsection of the second gate line along a second direction, the second direction orthogonal to the first direction (see annotated fig 6 below); and
a fourth gate line extending between and continuous with the midsection of the first gate line and the midsection of the second gate line along the second direction (see annotated fig 6 below).
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As to claim 3, Misaka discloses the integrated circuit structure of claim 1 (paragraphs above),
wherein a portion of the first gate line is over a semiconductor body (fig 6, portion of the first gate line is over a semiconductor body 100).
As to claim 5, Misaka discloses the integrated circuit structure of claim 1 (paragraphs above),
a fifth gate line non-continuous with the first, second, third and fourth gate lines, the fifth gate line over one or more active semiconductor channel structures (fig 6, gate line adjacent to the first gate line shown in annotated figure 6 above that is over active layer 100, wherein the region directly overlapping with the gate line is considered to be the channel structure).
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. No. 2020/0343364 A1), hereafter referred to as Kim.
As to claim 1, Kim discloses an integrated circuit structure (fig 6A-B, [0018]), comprising:
a first gate line along a first direction (DG5/DG7 in vertical direction);
a second gate line (DG6/DG8) parallel with the first gate line (DG5/DG7) along the first direction (vertical direction);
a third gate line (BR3) extending between and continuous with a midsection of the first gate line (DG5/DG7) and a midsection of the second gate line (DG6/DG8) along a second direction (horizontal direction), the second direction orthogonal to the first direction (horizontal direction is orthogonal to vertical direction); and
a fourth gate line (BR4) extending between and continuous with the midsection of the first gate line (DG5/DG7) and the midsection of the second gate line (DG6/DG8) along the second direction (horizontal direction).
As to claim 2, Kim discloses the integrated circuit structure of claim 1 (paragraphs above),
wherein an entirety of the first gate line, the second gate line, the third gate line and the fourth gate line is on an isolation structure (figs 6A-B, gate lines DG5/DG7, DG6/DG8, BR3, BR4 on isolation structure 105).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 4, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Misaka in view of Kim.
As to claim 2, Misaka discloses the integrated circuit structure of claim 1 (paragraphs above),
Misaka does not disclose wherein an entirety of the first gate line, the second gate line, the third gate line and the fourth gate line is on an isolation structure.
Nonetheless, Kim discloses similar gate lines wherein an entirety of a first gate line, a second gate line, a third gate line and a fourth gate line is on an isolation structure (figs 6A-B, gate lines DG5, DG6, BR3 on isolation structure 105).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the first through fourth gate lines of Misaka entirely on an isolation structure as taught by Kim since this will isolate the dummy gate lines from the active semiconductor regions.
As to claim 4, Misaka discloses the integrated circuit structure of claim 3 (paragraphs above),
Misaka does not disclose wherein the semiconductor body is a semiconductor fin.
Nonetheless, Kim discloses wherein a semiconductor body is a semiconductor fin (fig 6A, F1; [0058]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the active portion of Misaka as a semiconductor fin as taught by Kim since this will improve performance and reduce short-channel effects compared to a planar transistor with the same physical channel length.
As to claim 6, Misaka discloses the integrated circuit structure of claim 1 (paragraphs above),
Misaka does not disclose wherein the first, second, third and fourth gate lines comprise polycrystalline silicon.
Nonetheless, Kim discloses wherein a first, second, third and fourth gate lines comprise polycrystalline silicon ([0062]-[0063]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the gate lines of Misaka with the material as taught by Kim since this will provide good work-function characteristics for the transistors.
As to claim 7, Misaka discloses the integrated circuit structure of claim 1 (paragraphs above),
Misaka does not disclose wherein the first, second, third and fourth gate lines comprise one or more metal-containing layers.
Nonetheless, Kim discloses wherein a first, second, and third gate lines comprise one or more metal-containing layers ([0062]-[0063]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the gate lines of Misaka with the material as taught by Kim since this will provide good work-function characteristics for the transistors.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Crum et al. (US Pub. No. 2020/0105756 A1), hereafter referred to as Crum, in view of Misaka.
As to claim 16, Crum discloses a computing device (fig 10, 1000, 1002, [0126]), comprising:
a board (fig 10, 1000, 1002, [0126]); and
a component coupled to the board (fig 10, 1000, 1002, [0126]), the component including an integrated circuit structure ([0126]).
Crum does not disclose the first through fourth gate lines as claimed.
Nonetheless, Misaka discloses a first gate line along a first direction (see annotated fig 6 above);
a second gate line parallel with the first gate line along the first direction (see annotated fig 6 above);
a third gate line extending between and continuous with a midsection of the first gate line and a midsection of the second gate line along a second direction, the second direction orthogonal to the first direction (see annotated fig 6 above); and
a fourth gate line extending between and continuous with the midsection of the first gate line and the midsection of the second gate line along the second direction (see annotated fig 6 above).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the gate lines of Crum with the structure as taught by Misaka since this will reduce layout variations thus resulting in uniform feature densities.
As to claim 17, Crum in view of Misaka discloses the computing device of claim 16 (paragraphs above).
Crum further discloses a memory coupled to the board (fig 10, 1002 including DRAM and ROM).
As to claim 18, Crum in view of Misaka discloses the computing device of claim 16 (paragraphs above).
Crum further discloses a communication chip coupled to the board (fig 10, communication chip 1006 on motherboard 1002).
As to claim 19, Crum in view of Misaka discloses the computing device of claim 16 (paragraphs above).
Crum further discloses wherein the component is a packaged integrated circuit die (fig 10, processor 1004 and chipset packaged IC die; [0126]-[0127]).
As to claim 20, Crum in view of Misaka discloses the computing device of claim 16 (paragraphs above).
Crum further discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (fig 10, processor 1004, communication chip 1006, [0125]-[0126]).
Response to Arguments
Applicant’s arguments with respect to the 112 rejection are persuasive.
Applicant's arguments filed 9/29/2025 have been fully considered but they are not persuasive.
Applicant argued that the Misaka reference does not anticipate the amended claim limitations to independent claims 1 and 16. Specifically, Misaka does not disclose the fourth gate line.
Examiner disagrees because the Misaka reference does disclose the fourth gate line as recited in claims 1 and 16, as detailed in the detail office action, above.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 9,318,478 B2 .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 12/30/2025