Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RCE, received 7/15/2026, has been entered.
Claims 1-20 are presented for examination. Claims 8-15 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 16 are indefinite because the limitation “the first gate line immediately adjacent to the first gate line such that the first gate line is laterally between the fifth gate line and the second gate line” cannot be understood. It is unclear how the first gate line could be immediately adjacent to the first gate line. Referring to the Applicant’s remarks with respect to these claim amendments, received 7/15/2026, there is no mention as to which elements these additional gate lines in the original disclosure for the newly recited fifth or sixth gate line. Additionally, there is no recitation in the Applicant’s original disclosure for “a fifth gate line” or “a sixth gate line.” However, it appears that the claimed fifth and sixth gate lines are shown as gate lines 106A. Nonetheless, it is still unclear how a first gate line is immediately adjacent to the first gate line in the amended claims 1 and 16. Additionally, claims 2-7 and 17-20 are indefinite because of their dependence from one of claim 1 or 16.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae et al. (US Patent No. 9,318,478 B1), hereafter referred to as Bae.
As to claim 1, Bae discloses an integrated circuit structure (figs 10 and 17, 190), comprising:
a first gate line along a first direction (fig 10/17, 220; Y-direction);
a second gate line (210) parallel with the first gate line (220) along the first direction;
a third gate line (213) extending between and continuous with a midsection of the first gate line (220) and a midsection of the second gate line (210) along a second direction (X-direction, the second direction orthogonal to the first direction (see XY coordinate);
a fourth gate line (214) extending between and continuous with the midsection of the first gate line (220) and the midsection of the second gate line (210) along the second direction (X-direction), wherein the first gate line (220) and the second gate line (210) are continuous between the third gate line (213) and the fourth gate line (214);
a fifth gate line (fig 17, 410) along the first direction (Y-direction), the first gate line (220) immediately adjacent to the first gate line (220) such that the first gate line (220) is laterally between the fifth gate line (410) and the second gate line (210); and
a sixth gate line (420) along the first direction (Y-direction), the sixth gate line (420) immediately adjacent to the fifth gate line (410) such that the fifth gate line (410) is laterally between the first gate line (220) and the sixth gate line (420), wherein there are no gate lines extending between the fifth gate line and the sixth gate line along the second direction (X-direction).
As to claim 3, Bae discloses the integrated circuit structure of claim 1 (paragraphs above),
wherein a portion of the first gate line is over a semiconductor body (semiconductor body 100).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 and 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Kim et al. (US Pub. No. 2020/0343364 A1), hereafter referred to as Kim.
As to claim 2, Bae discloses the integrated circuit structure of claim 1 (paragraphs above).
Bae does not disclose wherein an entirety of the first gate line, the second gate line, the third gate line and the fourth gate line is on an isolation structure.
Nonetheless, Kim discloses similar gate lines wherein an entirety of a first gate line, a second gate line, a third gate line and a fourth gate line is on an isolation structure (figs 6A-B, gate lines DG5, DG6, BR3 on isolation structure 105).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the first through fourth gate lines of Bae entirely on an isolation structure as taught by Kim since this will isolate the dummy gate lines from the active semiconductor regions.
As to claim 4, Bae discloses the integrated circuit structure of claim 3 (paragraphs above),
Bae does not disclose wherein the semiconductor body is a semiconductor fin.
Nonetheless, Kim discloses wherein a semiconductor body is a semiconductor fin (fig 6A, F1; [0058]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the active portion of Bae as a semiconductor fin as taught by Kim since this will improve performance and reduce short-channel effects compared to a planar transistor with the same physical channel length.
As to claim 5, Bae discloses the integrated circuit structure of claim 1 (paragraphs above).
Bae does not disclose a fifth gate line non-continuous with the first, second, third and fourth gate lines, the fifth gate line over one or more active semiconductor channel structures.
Nonetheless, Kim discloses a fifth gate line (fig 6A, RG1) non-continuous with the first, second, third and fourth gate lines (dummy gate lines DG1-DG6), the fifth gate line (RG1) over one or more active semiconductor channel structures (F4).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to include the fifth gate line of Kim in the integrated circuit structure of Bae since this will provide real gate lines that may function in accord with the active fin structure adjacent to the dummy regions such that functional finFETs are accessible.
As to claim 6, Bae discloses the integrated circuit structure of claim 1 (paragraphs above).
Bae does not disclose wherein the first, second, third and fourth gate lines comprise polycrystalline silicon.
Nonetheless, Kim discloses wherein a first, second, third and fourth gate lines comprise polycrystalline silicon ([0062]-[0063]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the gate lines of Bae with the material as taught by Kim since this will provide good work-function characteristics for the transistors.
As to claim 7, Bae discloses the integrated circuit structure of claim 1 (paragraphs above).
Bae does not disclose wherein the first, second, third and fourth gate lines comprise one or more metal-containing layers.
Nonetheless, Kim discloses wherein a first, second, and third gate lines comprise one or more metal-containing layers ([0062]-[0063]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the gate lines of Bae with the material as taught by Kim since this will provide good work-function characteristics for the transistors.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Crum et al. (US Pub. No. 2020/0105756 A1), hereafter referred to as Crum, in view of Bae.
As to claim 16, Crum discloses a computing device (fig 10, 1000, 1002, [0126]), comprising:
a board (fig 10, 1000, 1002, [0126]); and
a component coupled to the board (fig 10, 1000, 1002, [0126]), the component including an integrated circuit structure ([0126]).
Crum does not disclose the first through fourth gate lines as claimed.
Nonetheless, Bae discloses a first gate line (figs 10/17, 220) along a first direction (Y-direction);
a second gate line (210) parallel with the first gate line (220) along the first direction (Y-direction);
a third gate line (213) extending between and continuous with a midsection of the first gate line (220) and a midsection of the second gate line (210) along a second direction (X-direction), the second direction orthogonal to the first direction (XY-directions);
a fourth gate line (214) extending between and continuous with the midsection of the first gate line (220) and the midsection of the second gate line (210) along the second direction (X-direction), wherein the first gate line (220) and the second gate line (210) are continuous between the third gate line (213) and the fourth gate line (214);
a fifth gate line (fig 17, 410) along the first direction (Y-direction), the first gate line (220) immediately adjacent to the first gate line (220) such that the first gate line (220) is laterally between the fifth gate line (410) and the second gate line (210); and
a sixth gate line (420) along the first direction (Y-direction), the sixth gate line (420) immediately adjacent to the fifth gate line (410) such that the fifth gate line (410) is laterally between the first gate line (220) and the sixth gate line (420), wherein there are no gate lines extending between the fifth gate line and the sixth gate line along the second direction (X-direction).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the gate lines of Crum with the structure as taught by Bae since this will reduce layout variations thus resulting in uniform feature densities.
As to claim 17, Crum in view of Bae discloses the computing device of claim 16 (paragraphs above).
Crum further discloses a memory coupled to the board (fig 10, 1002 including DRAM and ROM).
As to claim 18, Crum in view of Bae discloses the computing device of claim 16 (paragraphs above).
Crum further discloses a communication chip coupled to the board (fig 10, communication chip 1006 on motherboard 1002).
As to claim 19, Crum in view of Bae discloses the computing device of claim 16 (paragraphs above).
Crum further discloses wherein the component is a packaged integrated circuit die (fig 10, processor 1004 and chipset packaged IC die; [0126]-[0127]).
As to claim 20, Crum in view of Bae discloses the computing device of claim 16 (paragraphs above).
Crum further discloses wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (fig 10, processor 1004, communication chip 1006, [0125]-[0126]).
Response to Arguments
Applicant's arguments filed 7/15/2026 have been fully considered but they are not persuasive.
Applicant argued that Bae does not teach or suggest the amended claim limitations because fig 20 shows multiple dummy gate line structures 150a each including two parallel lines with bridges therebetween.
Examiner disagrees because element 150a is a fourth mask pattern instead of a dummy gate line structure. Additionally, as detailed in the office action above, Bae’s figure 17 shows the fifth and sixth gate line as claimed.
Pertinent Art
The prior art made of record is considered pertinent to applicant's disclosure. US Patent 9,318,478 B2 .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 8/28/2026
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