Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 1/6/2026, has been entered.
Claims 1, 2, 4 and 6-25 are presented for examination. Claims 10-25 are withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yaung et al. (US Pub. No. 2019/0371780 A1), hereafter referred to as Yaung, in view of Fan et al. (US Pub. No. 2022/0352044 A1), hereafter referred to as Fan, and further in view of Lan et al. (US Pub. No. 2021/0143071 A1), hereafter referred to as Lan.
As to claim 1, Yaung discloses a semiconductor die (fig 7, [0030]), comprising:
a die substrate (fig 7, 222);
a pad layer (238) over the die substrate (222), wherein the pad layer (238) comprises first pads (238) with a first dimension and a first pitch and second pads with a second dimension and a second pitch (fig 7, dimensions and pitches of first pads 238); and
a hybrid bonding layer (fig 7, hybrid bonding layer is considered 226 and 224) over and vertically spaced apart from the pad layer (238; specifically, 224 is over and vertically spaced apart from 238 by element 232), wherein the hybrid bonding layer comprises:
a dielectric layer (226; [0031]); and
an array of hybrid bonding pads (224) in the dielectric layer (226), wherein the hybrid bonding pads comprise a third dimension and a third pitch (fig 7, S2 and W2).
Yaung does not disclose wherein the array of hybrid bonding pads has a bottommost surface at a same level as a bottommost surface of the dielectric layer.
Nonetheless, Fan discloses a similar hybrid bonding pad arrangement (fig 3A, hybrid bonding structure 150 including dielectric layer 151 and pad 152, wherein the dielectric layer 151 includes a first layer 157 which is considered to be the claimed “a dielectric layer”) wherein the hybrid bonding pads has a bottommost surface at a same level as a bottommost surface of the dielectric layer (see figure 8 which shows the details of 150 shown in fig 3A, specifically, pads 152 including a bottommost surface 154 that is at a same level as bottommost surface of dielectric layer 157 of the dual layer 151).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the dielectric layer of Yaung such that the hybrid bonding structure includes the hybrid bonding pads of Yaung in the dielectric layer with the bottommost surface the same as the bottommost surface of the pads as taught by Fan since this will provide for improved patterning and reliability of the conductive and dielectric elements.
Yaung in view of Fan does not disclose wherein individual ones of the first pads are coupled to a corresponding individual one of the hybrid bonding pads and wherein individual ones of the second pads are coupled to a plurality of the hybrid bonding pads.
Nonetheless, Lan discloses a hybrid bonding structure (fig 2) wherein individual ones of first pads are coupled to a corresponding individual one of a hybrid bonding pad and wherein individual ones of second pads are coupled to a plurality of hybrid bonding pads (fig 2, [0032]-[0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to couple individual ones of the metal pad/lines (Yaung, 238 [0032]) to individual ones of the hybrid bonding pads (Yaung, 224), and individual ones of metal pads/lines (Yaung, 238) to a plurality of hybrid bonding pads (Yaung, 224) of Yaung as taught by Lan since electrically routing only one pad to one pad when only one pad to one pad is required would improve routing, and electrically routing one pad (IC layer shown in fig 2 of Lan) to more than one pad (Cu pad shown in fig 2 of Lan) in order to improve electrical routing of the electrical interconnections to the semiconductor elements of the IC within the optimized surface area.
As to claim 2, Yaung in view of Fan and Lan disclose the semiconductor die of claim 1 (paragraphs above).
Yaung further discloses wherein the entire array of hybrid bonding pads have the third dimension and the third pitch ([0033]).
As to claim 9, Yaung in view of Fan and Lan disclose the semiconductor die of claim 1 (paragraphs above).
Yaung further discloses wherein first surfaces of the hybrid bonding pads are substantially coplanar with the first surface of the dielectric layer (fig 7, 224 is coplanar with 226).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yaung in view of Fan and Lan and further in view of Wu et al. (US Pub. No. 2017/0250160 A1), hereafter referred to as Wu.
As to claim 4, Yaung in view of Fan and Lan disclose the semiconductor die of claim 1 (paragraphs above).
Yaung in view of Fan do not disclose wherein the first pads are input/output pads.
Nonetheless, Wu discloses a similar semiconductor device including hybrid bonding and first pads are input/output pads ([0016]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the first pads of Yaung in view of Fan as input/output pads as taught by Wu since this will provide improved control circuitry for the semiconductor components.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yaung in view of Fan and Lan and further in view of Katkar et al. (US Pub. No. 2021/0193625 A1), hereafter referred to as Katkar.
As to claim 6, Yaung in view of Fan and Lan disclose the semiconductor die of claim 1 (paragraphs above).
Yaung in view of Fan do not disclose wherein the second pads are power or ground pads.
Nonetheless, Katkar discloses a similar semiconductor device including hybrid bonding pads that are power or ground pads ([0020]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the pads of Yaung in view of Fan as power or ground pads as taught by Katkar since power and ground pads allow for improved operation of the semiconductor components.
As to claim 7, Yaung in view of Fan and Lan disclose the semiconductor die of claim 1 (paragraphs above).
Yaung in view of Fan do not disclose wherein the third pitch is approximately 40 micron or smaller.
Nonetheless, Katkar discloses a similar semiconductor device including hybrid bonding pads with a pitch that is approximately 40 micron or smaller ([0018]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the pitch of the hybrid bonding pads of Yaung in view of Fan within the range as taught by Katkar since forming the bonding pads at such a pitch allows for improved interconnection of the semiconductor devices.
As to claim 8, Yaung in view of Fan, Lan and Katkar disclose the semiconductor die of claim 7 (paragraphs above).
Yaung in view of Fan do not disclose wherein the third pitch is approximately 10 micron or smaller.
Nonetheless, Katkar discloses a similar semiconductor device including hybrid bonding pads with a pitch that is approximately 10 micron or smaller ([0018]).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the pitch of the hybrid bonding pads of Yaung in view of Fan within the range as taught by Katkar since forming the bonding pads at such a pitch allows for improved interconnection of the semiconductor devices.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4 and 6-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2017/0250160 A1 teaches ones of pads 112 connect to a plurality of hybrid bonding pads 113.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/2/2026
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