Prosecution Insights
Last updated: April 19, 2026
Application No. 17/357,729

FEATURES FOR IMPROVING DIE SIZE AND ORIENTATION DIFFERENTIATION IN HYBRID BONDING SELF ASSEMBLY

Final Rejection §102§103
Filed
Jun 24, 2021
Examiner
OH, JIYOUNG
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
4 (Final)
72%
Grant Probability
Favorable
5-6
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
21 granted / 29 resolved
+4.4% vs TC avg
Strong +33% interview lift
Without
With
+32.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
51 currently pending
Career history
80
Total Applications
across all art units

Statute-Specific Performance

§103
59.0%
+19.0% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 29 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application Acknowledgement is made of the amendment received on 1/14/2026. Claims 1-3, 7-8, 10-11, 13-15, and 17-23 are pending in this application. Claims 1, 7-8, 10-11, 13, 17-18, and 23 are amended. Claims 4-6, 9, 12, 16, and 24-25 are canceled. Claims 1-3, 7-8, 10-11, 13-15, 17-18, and 23 are presented in this Office Action. Claim Objections Claim 11 are objected to because of the following informalities: In claim 11, line 5, “the second has an uppermost surface” should read --the second stub has an uppermost surface -- (emphasis added). Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 11, 13, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morozumi (US 2003/0030151). Regarding claim 11, Morozumi teaches a die (Fig. 6(A), [0148]), comprising: a semiconductor substrate (30, [0149]); a pedestal (21, [0142]) extending up from the semiconductor substrate (30); and a first stub (the left 14; hereinafter ‘14L’) and a second stub (the right 14; hereinafter ‘14R’) adjacent to the pedestal (21), wherein each of the first stub (14L) and the second (14R) has an uppermost surface (the uppermost surfaces of 14) above an uppermost surface of the pedestal (the uppermost surface of 21), wherein the pedestal (21) is between the first stub (14L) and the second stub (14R), the first stub (14L) and the second stub (14R) each laterally spaced apart from a die attach region (22, [0149]) over the pedestal (21), wherein a maximum width of the die attach region (the maximum width of 22) is less than (shown in Fig. 6(A)) a distance (the distance) between the first stub (14L) and the second stub (14R). Regarding claim 13, Morozumi teaches the die of claim 11, further comprising a plateau (13, Fig. 6(A), [0149]) around the pedestal (21), wherein each of the first stub (14L) and the second stub (14R) extends up from the plateau (13). Regarding claim 18, Morozumi teaches the die of claim 11, wherein the uppermost surface of each of the first stub and the second stub id domed, flat, v-grooved, u-grooved, or pointed (the top surfaces of 14L and 14R is flat, Fig. 6(A)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 10, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Sekiya (US 2015/0262971) in view of Morris et al. (US 2010/0139954; hereinafter ‘Morris’). Regarding claim 1, Sekiya teaches a multi-die module (FIG. 7B, [0037]), comprising: a first die (15a, [0038]), wherein the first die comprises: a first pedestal (the upper portion of 15a adjacent to 19a; hereinafter ‘PE1’); and a plateau (the second ridge of grooves 13 between second chip placement regions 15b and the next 15a; hereinafter ‘PL’) around the first pedestal (PE1); a second die (19a, [0040]), wherein the second die comprises: a second pedestal (the lower portion of 19a adjacent to 15a; hereinafter ‘PE2’), wherein the second pedestal (PE2) is attached to the first pedestal (PE1). Sekiya does not teach the multi-die module comprising: the first die comprises a first stub and a second stub extending up from the plateau, wherein each of the first stube and the second stub has an uppermost surface above an uppermost surface of the first pedestal, and wherein the first pedestal is between the first stub and the second stub; and a second die comprises the second pedestal laterally spaced apart from the first stub and laterally spaced apart from the second stub, wherein a maximum width of the second pedestal is less than a distance between the first stub and the second stub. Morris teaches a multi-die module (11, FIG. 2, [0034]) comprising: the first die (1, [0033]) comprises a first stub (the left 5; hereinafter ‘5L’) and a second stub (the right 5; hereinafter ‘5R’) extending up from the plateau (7) wherein each of the first stube (5L) and the second stub (5R) has an uppermost surface (the uppermost surfaces of 5L and 5R) above an uppermost surface of the first pedestal (the uppermost surface of 8), and wherein the first pedestal (8) is between the first stub (5L) and the second stub (5R); and a second die (2) comprises the second pedestal (4, FIG. 3) laterally spaced apart from the first stub (5L) and laterally spaced apart from the second stub (5R), wherein a maximum width of the second pedestal (the maximum width of 4) is less than a distance between the first stub (5L) and the second stub (5R). As taught by Morris, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya to obtain and achieve the multi-die module comprising: the first die comprises a first stub and a second stub extending up from the plateau, wherein each of the first stube and the second stub has an uppermost surface above an uppermost surface of the first pedestal, and wherein the first pedestal is between the first stub and the second stub; and a second die comprises the second pedestal laterally spaced apart from the first stub and laterally spaced apart from the second stub, wherein a maximum width of the second pedestal is less than a distance between the first stub and the second stub as claimed, because it forms an upwardly extending structure disposed around the first pedestal to improve alignment after self-assembly [0037]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morris in combination with Sekiya due to above reason. Regarding claim 10, Sekiya in view of Morris teaches the multi-die module of claim 1, Sekiya does not teach the multi-die module wherein the uppermost surface of each of the first stub and the second stub is domed, flat, v-grooved, u-grooved, or pointed. Morris teaches the multi-die module wherein the uppermost surface of each of the first stub and the second stub is domed, flat, v-grooved, u-grooved, or pointed (the uppermost surface of 5 is flat, FIG. 2) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Morris to include the multi-die module wherein the uppermost surface of each of the first stub and the second stub is domed, flat, v-grooved, u-grooved, or pointed as claimed, because the flat topology is known to minimize unstable mechanical contact, thereby enhancing the precision of lateral and rotational alignment during self-assembly, the specific design would depend on the required alignment accuracy for the intended device application. Regarding claim 23, Sekiya teaches an electronic system ([0004]), FIG. 7B, [0004, 0037-0038, 0040, 0045], comprising: a board (manufacturing a package using a multipackage substrate to facilitate connection to a device, [0004]); a package substrate coupled to the board (package substrate coupled to the board, [0004]); and a multi-die module coupled to the package substrate (plural chips coupled to the package substrate, FIG. 7B, [0037]), wherein the multi-die module comprises: a first die (15a, [0038]) wherein the first die comprises: a first pedestal (the upper portion of 15a adjacent to 19a; hereinafter ‘PE1’); a plateau (the second ridge of grooves 13 between second chip placement regions 15b and the next 15a; hereinafter ‘PL’) around the first pedestal (PE1); and a second die (19a, [0040]), wherein the second die comprises: a second pedestal (the lower portion of 19a adjacent to 15a; hereinafter ‘PE2’), wherein the second pedestal (PE2) is attached to the first pedestal (PE1). Sekiya does not teach the electronic system comprising: the multi-die module comprises: the first die comprises a first stub and a second stub extending up from the plateau, wherein each of the first stub and the second stub has an uppermost surface above an uppermost surface of the first pedestal, and wherein the first pedestal is between the first stub and the second stub; and the second die comprises: the second pedestal laterally spaced apart from the first stub and laterally spaced apart from the second stub, wherein a maximum width of the second pedestal is less than a distance between the first stub sand the second stub. Morris teaches an electronic system [0003] comprising: a multi-die module (11, FIGS. 1 and 2, [0033-0034]) comprises: the first die (1, [0033]) comprises a first stub (the left 5; hereinafter ‘5L’) and a second stub (the right 5; hereinafter ‘5R’) extending up from the plateau (7), wherein each of the first stub (5L) and the second stub (5R) has an uppermost surface (the uppermost surfaces of 5L and 5R) above an uppermost surface of the first pedestal (the uppermost surface of 8), and wherein the first pedestal (8) is between the first stub (5L) and the second stub (5R); and the second die (2) comprises: the second pedestal (4, FIG. 3) laterally spaced apart from the first stub (5L) and laterally spaced apart from the second stub (5R), wherein a maximum width of the second pedestal (the maximum width of 4) is less than a distance between the first stub (5L) and the second stub (5R). As taught by Morris, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya to obtain and achieve the electronic system comprising: the multi-die module comprises: the first die comprises a first stub and a second stub extending up from the plateau, wherein each of the first stub and the second stub has an uppermost surface above an uppermost surface of the first pedestal, and wherein the first pedestal is between the first stub and the second stub; and the second die comprises: the second pedestal laterally spaced apart from the first stub and laterally spaced apart from the second stub, wherein a maximum width of the second pedestal is less than a distance between the first stub sand the second stub as claimed, because it forms an upwardly extending structure disposed around the first pedestal to improve alignment after self-assembly [0037]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morris in combination with Sekiya due to above reason. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiya (US 2015/0262971) in view of Morris (US 2010/0139954), and further in view of Luce et al. (US 2010/0248424; hereinafter ‘Luce’). Regarding claim 2, Sekiya in view of Morris teaches the multi-die module of claim 1, Sekiya does not teach the multi-die module wherein a hydrophilic layer is on the first pedestal and on the second pedestal. Morris teaches the multi-die module wherein a binding parts (4 and 8, FIG. 2) are chemically treated to create regions having hydrophilic or hydrophobic characteristics [0013]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Morris to obtain and achieve the multi-die module wherein a hydrophilic layer or hydrophobic is on the first pedestal and on the second pedestal as claimed, because chemical treatment of binding surfaces enables control of surface energy and wetting behavior, thereby improving selective binding and alignment [0013]. Sekiya in view of Morris does not explicitly the multi-die module wherein a hydrophilic layer is on the first pedestal and on the second pedestal. Luce teaches a multi-die module (FIG. 1A, [0027]), wherein a hydrophilic layer (14 and 24, [0031-0032]) is on the first pedestal (pedestal of first chips 10, [0031]) and on the second pedestal (pedestal of second chips 20, [0032]). As taught by Luce, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya in view of Morris to obtain and achieve the multi-die module wherein a hydrophilic layer is on the first pedestal and on the second pedestal as claimed, because it aids in enhancing the wettability and self-alignment of the semiconductor ships during the assembly process, particularly when they are vertically stacked [0004, 0006]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Luce in combination with Sekiya in view of Morris due to above reason. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiya (US 2015/0262971) in view of Morris (US 2010/0139954), and further in view of Han et al. (KR 2010/0098083; hereinafter ‘Han’) and Solzbacher et al. (US 2011/0192445; hereinafter ‘Solzbacher’). Regarding claim 3, Sekiya in view of Morris teaches the multi-die module of claim 1, but does not teach the multi-die module wherein a hydrophobic layer is on sidewalls of the first pedestal, on a surface of the first die between the first pedestal and the plateau, and on the plateau. Han teaches a multi-die module (FIG. 5e, [0002]), wherein a hydrophobic layer is on sidewalls of the first pedestal and on the plateau (1210 including 1213 and 1211 having a hydrophobic surface, [0054, 0056]). As taught by Han, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya in view of Morris to obtain and achieve the multi-die module wherein a hydrophobic layer is on sidewalls of the first pedestal and on the plateau as claimed, because it facilitates complete matching to the die attach pattern by leveraging differences in surface tension and adhesive forces, which are necessary for proper alignment of the selective part [0048-0049]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Han in combination with Sekiya in view of Morris due to above reason. Sekiya in view of Morris and Han does not teach the multi-die module wherein a hydrophobic layer is on a surface of the first die between the first pedestal and the plateau. Solzbacher teaches a multi-die module (FIG. 3A, [0029]), wherein a hydrophobic layer (hydrophobic surface, [0032]) is on a surface of the first die (remaining surface 40 of the alignment substrate, [0029, 0032]) between the first pedestal (left alignment areas 38, [0029]) and the plateau (right alignment areas 38). As taught by Solzbacher, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya in view of Morris and Han to obtain and achieve the multi-die module wherein a hydrophobic layer is on a surface of the first die between the first pedestal and the plateau as claimed, this precise control of surface properties aids in controlling the die’s surface wettability, ensure adherence only at designated hydrophilic receptor sites, and enhances alignment accuracy [0029-0032]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Solzbacher in combination with Sekiya in view of Morris and Han due to above reason. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiya (US 2015/0262971) in view of Morris (US 2010/0139954), and further in view of Chow et al. (US 2011/0227200; hereinafter ‘Chow’). Regarding claim 7, Sekiya in view of Morris teaches the multi-die module of claim 1, but does not teach the multi-die wherein each of the first stub and the second stub has a height that is approximately 50 μm or less. Chow teaches a multi-die module (MCM, [0002]) wherein each of the first stub and the second stub has a height that is approximately 50 μm or less (alignment features have a height of 10 μm, [0050]). As taught by Chow, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya in view of Morris to obtain and the multi-die wherein each of the first stub and the second stub has a height that is approximately 50 μm or less as claimed, because it aids in maintain precise and uniform alignment across substrates and reducing variations in spacing between dies [0050]. Further, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chow in combination with Sekiya in view of Morris due to above reason. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiya (US 2015/0262971) in view of Morris (US 2010/0139954), and further in view of West et al. (US 2010/0078769; hereinafter ‘West’). Regarding claim 8, Sekiya in view of Morris teaches the multi-die module of claim 1, Sekiya does not teach the multi-die wherein the second pedestal has a chamfered corner that is adjacent to the second stub. Morris teaches the multi-die module wherein the second pedestal (4, FIG. 2) is adjacent to the second stub (5R). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Morris to obtain and achieve the multi-die module wherein the second pedestal is adjacent to the second stub as claimed, because the stub functions as an alignment reference, thereby improving alignment accuracy between the two dies. Sekiya in view of Morris does not teach the multi-die wherein the second pedestal has a chamfered corner. West teaches a multi-die module ([0014]) wherein the second pedestal has a chamfered corner (100 has a chamfered corner, FIG. 4, [0033]). As taught by West, one of ordinary skill in the art would utilize and modify the above teaching into Sekiya in view of Morris to obtain and achieve the multi-die module wherein the second pedestal has a chamfered corner as claimed, because it aids in reducing stress concentration and preventing crack formation compared to conventional die layouts having sharp corners, thereby enhancing the reliability of chip scale packaging [0006-0007]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by West in combination with Sekiya in view of Morris due to above reason. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Morozumi (US 2003/0030151) in view of Han (KR 2010/0098083). Regarding claim 14, Morozumi teaches the die of claim 11, Morozumi does not teach the die further comprising: a hydrophilic layer over the top surface of the pedestal. Han teaches a die (FIG. 5e, [0051]), further comprising: a hydrophilic layer over the top surface of the pedestal (hydrophilic treated portion over 1213, [0054]). As taught by Han, one of ordinary skill in the art would utilize and modify the above teaching into Morozumi to obtain and achieve the die further comprising: a hydrophilic layer over the top surface of the pedestal as claimed, because it aids in the precise application of liquid adhesive by enabling a prior hydrophilic treatment process on the die attach pattern [0050]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Han in combination with Morozumi due to above reason. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Morozumi (US 2003/0030151) in view of Han (KR 2010/0098083), and further in view of Solzbacher (US 2011/0192445). Regarding claim 15, Morozumi in view of Han teaches the die of claim 14, Morozumi does not teach he die further comprising a hydrophobic layer over sidewalls of the pedestal and over surfaces of the semiconductor substrate. Han teaches the die further comprising a hydrophobic layer over sidewalls of the pedestal (hydrophobic surface over 1213, FIG. 5e, [0054]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Han to include the die further comprising a hydrophobic layer over sidewalls of the pedestal as claimed, because it facilitates complete matching to the die attach pattern by leveraging differences in surface tension and adhesive forces, which are necessary for proper alignment of the selective part [0048-0049]. Morozumi in view of Han does not teach the die further comprising a hydrophobic layer over surfaces of the semiconductor substrate. Solzbacher teaches a die (FIG. 3A, [0029]), wherein a hydrophobic layer is on a surface of the first die (hydrophobic surface is on the remaining surface 40 of the alignment substrate, [0029, 0032]). As taught by Solzbacher, one of ordinary skill in the art would utilize and modify the above teaching into Morozumi in view of Han to obtain and achieve the die further comprising a hydrophobic layer over surfaces of the semiconductor substrate as claimed, because this precise control of surface properties aids in controlling the die’s surface wettability, ensure adherence only at designated hydrophilic receptor sites, and enhances alignment accuracy [0029-0032]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Solzbacher in combination with Morozumi in view of Han due to above reason. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Morozumi (US 2003/0030151) in view of Chow (US 2011/0227200). Regarding claim 17, Morozumi teaches the die of claim 11, wherein the top surface of each of the first stub and the second stub is above the top surface of the pedestal (the top surfaces of 14L and 14R are above the top surface of 21, Fig. 6(A)). Morozumi does not teach the die wherein the top surface of the stub is approximately 50 μm or less above the top surface of the pedestal. Chow teaches a die ([0002]) wherein the top surface of the stub is approximately 50 μm or less above the top surface of the pedestal (alignment features has a height of 10 μm, [0050]). As taught by Chow, one of ordinary skill in the art would utilize and modify the above teaching into Morozumi to obtain and achieve the die wherein the top surface of the stub is approximately 50 μm or less above the top surface of the pedestal as claimed, it aids in maintain precise and uniform alignment across substrates and reducing variations in spacing between dies [0050]. Further, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chow in combination with Morozumi due to above reason. Response to Arguments Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection. Applicant submits, in pages 11-12 of Remark, that “Applicant understands Morris as disclosing an entirety of wafer 2 as extending laterally beyond the solder bumps 5. As such, Applicant does not understand Morris as disclosing the wafer 2 as having a pedestal with a maximum lateral width that is less than a distance between the solder bumps 5. Thus, the combination of Sekiya in view of Morris does not disclose … as is required by Applicant's claims. As such, with respect to amended independent claims 1, 11 and 23, the combination of Sekiya in view of Morris fails to disclose each and every feature of Applicant's claims.”. The examiner respectfully disagrees. Applicant’s argument addresses the width of the entire wafer/die 2, whereas the rejection specifically identifies element 4 of Morris as the claimed a second pedestal. The claims recite a limitation on the maximum width of the pedestal, not the maximum width of the die as a whole. As a shown in FIG. 3 of Morris, the second pedestal 4 is positioned between the first stub 5L and the second stub 5R, and the maximum width of the second pedestal 4 is less than the distance between the first stub 5L and the second stub 5R. Accordingly, applicant’s argument does not address the actual mapping relied upon in the rejection and is therefore not persuasive. Details included in the above rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIYOUNG OH/Examiner, Art Unit 2818 /DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/24/26
Read full office action

Prosecution Timeline

Jun 24, 2021
Application Filed
Oct 13, 2021
Response after Non-Final Action
Nov 26, 2024
Non-Final Rejection — §102, §103
Mar 03, 2025
Response Filed
Apr 29, 2025
Final Rejection — §102, §103
Jul 11, 2025
Response after Non-Final Action
Aug 06, 2025
Request for Continued Examination
Aug 08, 2025
Response after Non-Final Action
Oct 05, 2025
Non-Final Rejection — §102, §103
Jan 14, 2026
Response Filed
Feb 23, 2026
Final Rejection — §102, §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+32.9%)
3y 5m
Median Time to Grant
High
PTA Risk
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