DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received 2/5/2026. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 11,075,273).
Re claims 1, 6, 11 & 16, Reznicek teaches, under BRI & based on plurality of devices/transistors, Figs. 1-5, abstract, cols. 1, 3-9, 16 & 17, a computer device (e.g., computer products) (col. 16, last par. & col. 17, 1st par.), comprising: a board (e.g., motherboard), and a component coupled to the board, the component including an integrated circuit structure (e.g., ESD protection devices integrated into integrated circuits), comprising:
-a stack of nanowires (nanosheet stack 140L);
-a plurality of P-type epitaxial structures (510) coupled the stack of nanowires (140L) (within an integrated structure);
-a plurality of N-type epitaxial structures (520) coupled the stack of nanowires (140L) (within an integrated structure),
-a plurality of gate structures (210) over the stack of nanowires, and
-a semiconductor material (120L) between and in contact with vertically adjacent ones of the stack of nanowires, the semiconductor material (120L) in locations beneath and extending laterally beyond locations of the individual ones of gate structures (210), and the semiconductor material in contact with one of the plurality of N-type epitaxial (520) and one of the plurality of the P-type epitaxial structures (510).
Note: contact # direct/physical contact.
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Reznicek does not explicitly teach individually ones of the plurality of N-type epitaxial structures alternating with individual ones of the plurality of P-type epitaxial structures; and individual ones of the plurality of gate structures alternating with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures; and the semiconductor material in contact with the individually ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of P-type epitaxial structures.
Reznicek does teach “semiconductor fin field effect transistors (FinFETs)” (col. 1, 2nd par.), “ESD protection devices are generally integrated into the integrated circuits” (col. 1, 4th par.) & “The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form” (col. 16, last par.).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Reznicek to obtain individually ones of the plurality of N-type epitaxial structures alternating with individual ones of the plurality of P-type epitaxial structures; individual ones of the plurality of gate structures alternating with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures; and the semiconductor material in contact with the individually ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of P-type epitaxial structures as claimed, because, based on lateral arrangement of the chips/structures in a wafer, with undue experimentation, one of ordinary skill in the art would achieve a desired integrated structure having alternative ones of N/P structures and gate structures to enhance protection from ESD events in the formed structure(s). Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Re claims 2 & 12, Reznicek teaches the plurality of P-type epitaxial structures are coupled to ground, and the plurality of N-type epitaxial structures are coupled to one or more signal lines (e.g., based on function/operation of source/drain within a circuit/device).
Re claims 3 & 13, Reznicek teaches the integrated circuit structure is a lateral diode (col. 3, 4th par.).
Re claims 4 & 14, Reznicek teaches the P-type epitaxial structures (510) are boron-doped silicon or boron-doped silicon germanium structures, and wherein the N-type epitaxial structures (520) are phosphorous-doped silicon structures (col. 9, pars. 5-6th).
Re claims 5 & 15, Reznicek teaches, Figs. 6-7, one or more spacings (between 220S) in locations over the stack of nanowires, a corresponding one of the plurality of spacings extending between neighboring ones of the plurality of P-type epitaxial structures (510) and the plurality of N-type epitaxial structures (520), wherein the one or more spacings (between 220S) are one or more locations where a gate structure (e.g., 220 is removed) was removed or blocked from formation.
Re claims 7-10 & 17-20, Reznicek teaches a memory coupled to the board; a communication chip coupled to the board; the component is a packaged integrated die; and the component is selected from group consisting of a processor, a communication chip, and a digital signal processor (e.g., as intended use and basic/typical components in in a computer product, col. 16, last par. & col. 17, 1st par.).
3. Claims 1, 6, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nidhi et al. (US 2021/0183850).
Re claims 1, 6, 11 & 16, Nidhi teaches, under BRI & based on plurality of devices/diodes, Figs. 2A, 4C-4F & 7, [0023, 0047, 0049, 0050, 0054, 0057, 0087-0090, 0093], a computer device (e.g., computing device 700), comprising: a board (e.g., motherboard 702), and a component (706) coupled to the board, the component including an integrated circuit structure (e.g., ESD diodes in the semiconductor substrate), comprising:
-a stack of nanowires (nanowires 410);
-a plurality of P-type epitaxial structures (422) (of ESD diodes) coupled the stack of nanowires;
-a plurality of N-type epitaxial structures (421) (of EDS diodes) coupled the stack of nanowires;
-a plurality of gate structures (453) (of EDS diodes) over the stack of nanowires; and
-a semiconductor material (447) between and in contact with vertically adjacent ones of the stack of nanowires (410), the semiconductor material (447) in locations beneath and extending laterally beyond locations of the individual ones of gate structures (453) (Fig. 4C), and the semiconductor material (447) in contact with one of the plurality of N-type epitaxial (421) and one of the plurality of the P-type epitaxial structures (422) (Figs. 2A, 4F).
Note: contact # direct/physical contact
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Nidhi does not explicitly teach individually ones of the plurality of N-type epitaxial structures alternating with individual ones of the plurality of P-type epitaxial structures; and individual ones of the plurality of gate structures alternating with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures; and the semiconductor material in contact with the individually ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of P-type epitaxial structures.
Nidhi does teach “electrostatic discharge (ESD) diodes are typically formed with N-wells and P-wells in the semiconductor substrate” [0023] & “More complex devices such as …arrays…” [0093].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Nidhi to obtain individually ones of the plurality of N-type epitaxial structures alternating with individual ones of the plurality of P-type epitaxial structures, individual ones of the plurality of gate structures alternating with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures; and the semiconductor material in contact with the individually ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of P-type epitaxial structures as claimed, because it aids in achieving desired structure of EDS diode(s) within a nanoribbon architecture. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
4. Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Fukasaku (US 2021/0167224) in view of Shin et al. (US 2020/0365586).
Re claim 1, Fukasaku teaches, under BRI & based on plurality of diodes, Figs. 1A-B & 3B, [0070, 0076-0082], an integrated circuit structure (e.g., diodes), comprising:
-a stack of nanowires (21);
-a plurality of P-type epitaxial structures (31) over the stack of nanowires;
-a plurality of N-type epitaxial structures (32) over the stack of nanowires,
-a plurality of gate structures (23) over the stack of nanowires (21); and
-a semiconductor material (22) between and in contact with vertically adjacent ones of the stack of nanowires (21), the semiconductor material (22) in locations beneath the individual ones of gate structures (23), and the semiconductor material (22) in contact with one of the plurality of N-type epitaxial (32) and one of the plurality of the P-type epitaxial structures (31) (Fig. 1A).
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Fukasaku further teaches various configurations of the diodes [0048] & “diodes and field effect transistors are arranged depends on the required specifications of a semiconductor circuit” [070], but does not explicitly teach individually ones of N-type the plurality of epitaxial structures alternating with individual ones of the plurality of P-type epitaxial structures; individual ones of the plurality of gate structures alternating with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures; and the semiconductor material in contact with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures.
Shin teaches, Fig. 2A & 5J, [0028, 0030, 0085], integrated circuit device having individually ones of plurality of first epitaxial structures (first 134) alternating with individual ones of second epitaxial structures (second 134); individual ones of the plurality of gate structures (160) alternating with the individual ones of the plurality of first epitaxial structures (first 134) and the individual ones of the plurality of second epitaxial structures (second 134), and the semiconductor material (104) in contact with the individual ones of the plurality of the first epitaxial structures (first 134) and the individual ones of the plurality of the second epitaxial structures (second 134).
As taught by Shin, one of ordinary skill in the art would utilize & modify the above teaching into Fukasaku to obtain individually ones of N-type the plurality of epitaxial structures alternating with individual ones of the plurality of P-type epitaxial structures; individual ones of the plurality of gate structures alternating with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures; and the semiconductor material in contact with the individual ones of the plurality of N-type epitaxial structures and the individual ones of the plurality of the P-type epitaxial structures as claimed, because it aids in achieving desired structure of horizontal nanosheet FET having increased integration density.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shin in combination with Fukasaku due to above reason.
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
The claims amended with newly added limitations, interpretation and rejection under Reznizek and Nidhi & Fukasaku in view of Shin are also changed to meet the currently. Details included in the above rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/18/26