Attorney Docket Number: AD5871-US 111548-262571
Filing Date: 06/24/2021
Claimed Priority Date: none
Inventors: Hasan et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 03/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection mailed on 01/16/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 03/09/2026 has been entered.
Amendment Status
The RCE submission filed on 03/09/2026 as an amendment in reply to the Office action mailed on 01/16/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-6 and 8-25, wherein claims 2, 12-17, and 22 remain withdrawn from consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the package substrate coupled to the board recited in claim 23 must be shown or the features canceled from the claim. No new matter should be entered.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character 231 has been used to designate both a horizontal portion of the barrier in figure 2F and a gap in figure 2G.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters 410 and 411 have both been used to designate the same nanowire in figures 4A-4F.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The specification fails to provide proper antecedent basis for the claimed subject matter in claim 23 reciting a package substrate coupled to a board. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o).
In par.0003/ll.1 of US 2022/0416041, “on solution” should read “one solution”
Appropriate correction is required. No new matter should be entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8-11, 18-21, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek (US 10,170,638) in view of Guha (US 2020/0044087) and Wu (US 2022/0310452).
Regarding claim 1, Reznicek (see, e.g., fig. 8) shows most aspects of the instant invention, including a semiconductor device comprising:
a substrate 10;
a vertical stack of semiconductor channels 14P over the substrate;
a source 26 at a first end of the semiconductor channels;
a drain 26 at a second end of the semiconductor channels;
a barrier 20L, 20S, 30 between a bottommost surface of the source or the drain and the substrate, the barrier in contact with the bottommost surface of the source or the drain, wherein the barrier has an uppermost surface and the substrate has an uppermost surface; and
an oxide 22 between the barrier and the source or the drain, the oxide in contact with the bottommost surface of the source of the drain (see, e.g., col.8/ll.16-17)
Reznicek specifies that the substrate 10 is composed of any semiconducting material (see, e.g., col.3/ll.52-60) and fails to specify that the substrate could be dielectric. Guha, in a similar device to Reznicek, teaches semiconducting and dielectric substrates to be equivalent to each other (see, e.g., Guha: par.044/ll.1-20). Guha further suggests that a dielectric substrate would allow adjustments in the quality of the stack of layers formed on the substrate of Reznicek (see, e.g., Guha: figs. 3A-3B and par.0044/ll.16-20).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the dielectric substrate of Guha in the semiconductor device of Reznicek to achieve a desired quality for the stack of semiconductor channels posited over the substrate.
Furthermore, although Reznicek teaches most aspects of the instant invention, Reznicek fails to explicitly specify that Reznicek’s barrier has an uppermost surface below an uppermost surface of the substrate. Wu, in the same field of endeavor, teaches a semiconductor device 200 having a barrier 226 in contact with a source or drain 240, wherein the barrier has an uppermost surface below an uppermost surface of a substrate 202 (see, e.g., Wu: figs. 8 and 14). Wu further teaches that when a barrier has an uppermost surface below an uppermost surface of a substrate that the structure facilitates the formation of air gaps, which can reduce parasitic capacitance and subsequently improve the performance of the semiconductor device (see, e.g., Wu: pars.0021/ll.25-26, 0022/ll.27-34, and 0032/ll.19-22).
Wu is evidence showing that one of ordinary skill in the art would appreciate that having a barrier with an uppermost surface below an uppermost surface of a substrate would be equivalent to having a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, and that such differences would result in no unexpected changes in the performance of the device of Reznicek. That is, the barrier structures of both Reznicek and Wu would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a barrier with an uppermost surface below an uppermost surface of a substrate, as taught by Wu, or a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, as taught by Reznicek, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Wu is evidence that at the time of filing the invention it would have been obvious to one of ordinary skill in the art to include a barrier whose uppermost surface is below an uppermost surface of a substrate in the device of Reznicek, because such a configuration would facilitate the formation of air gaps, as taught by Wu, thereby reducing parasitic capacitance and improving the performance of Reznicek’s semiconductor device.
Regarding claim 3, Reznicek (see, e.g., fig. 8) shows that the barrier 20L, 20S, 30 has a u-shaped cross-section.
Regarding claim 4, Reznicek (see, e.g., col.7/ll.65-67, col.8/ll.17-18, and col.9/ll.32-33) teaches that the barrier 20L, 20S, 30 may be composed of a dielectric material, such as silicon nitride, and an interlevel dielectric (ILD) material, such as silicon dioxide. Reznicek further shows (see, e.g., col.3/ll.51-60) that this barrier may be composed of a different material than the substrate. However, Reznicek fails to show that the substrate may be dielectric. Guha, on the other hand, shows that the substrate can be dielectric (see paragraph 13 above) and further shows that such a dielectric substrate may be composed of glass (see, e.g., par.0044/ll.16-17).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use Reznicek’s and Guha’s materials respectively when exchanging the semiconductor substrate of Reznicek for the dielectric substrate of Guha, so as to obtain similar results (see paragraphs 11-13 above). Thus, the combined device would compose of the barrier of Reznicek and the substrate of Guha, wherein the barrier is a dielectric material that is a different material than the substrate.
Regarding claim 5, Reznicek (see, e.g., fig. 8) shows a gate stack 32, 34 around a vertical stack of semiconductor channels 14P, wherein edge surfaces of the gate stack are contacted by spacers 20S.
Regarding claim 6, Reznicek (see, e.g., fig. 8 and col.7/ll.49-52) shows that the spacers 20S and the barrier 20L, 20S, 30 comprise the same material.
Regarding claim 8, Reznicek (see, e.g., fig. 8) shows that the bottommost surface of the source or drain 26 is below the uppermost surface of the substrate 10.
Regarding claim 9, Reznicek (see, e.g., fig. 8) shows that a cross-section of the barrier 20L, 20S, 30 is u-shaped with lateral wings 20S.
Regarding claim 10, Reznicek (see, e.g., fig. 8) further shows a semiconductor region 26 contacting the lateral wings 20S.
Regarding claim 11, Reznicek (see, e.g., fig. 8) shows that the lateral wings 20S are on opposite sides of the u-shape 20L, 30.
Regarding claim 18, Reznicek (see, e.g., fig. 8) shows most aspects of the instant invention, including a nanowire device comprising:
a substrate 10;
a stack of nanowire channels 14P surrounded by a gate stack 32, 34;
a source or drain 26 at an end of the nanowire channels, wherein the source extends into the substrate; and
a barrier 20L, 20S, 30 between a bottommost surface of the source or drain and the substrate, the barrier in contact with the bottommost surface of the source or drain, wherein the barrier has an uppermost surface and the substrate has an uppermost surface; and
an oxide 22 between the barrier and the source or the drain, the oxide in contact with the bottommost surface of the source of the drain (see, e.g., col.8/ll.16-17)
Reznicek teaches that the substrate 10 is a semiconducting substrate and fails to teach that the substrate could be dielectric. Guha (see paragraph 13 above) teaches that such a semiconducting substrate may be exchanged for a dielectric substrate. See the comments stated above in paragraphs 13-14, which are considered to be repeated here.
Furthermore, although Reznicek teaches most aspects of the instant invention, Reznicek fails to explicitly specify that Reznicek’s barrier has an uppermost surface below an uppermost surface of the dielectric substrate. Regarding the materials of Reznicek’s substrate, see the comments stated above in paragraphs 13-14, which are considered to be repeated here. Regarding the positioning of the barrier, Wu, in the same field of endeavor, teaches a semiconductor device 200 having a barrier 226 in contact with a source or drain 240, wherein the barrier has an uppermost surface below an uppermost surface of a substrate 202 (see, e.g., Wu: figs. 8 and 14). Wu further teaches that when a barrier has an uppermost surface below an uppermost surface of a substrate that the structure facilitates the formation of air gaps, which can reduce parasitic capacitance and subsequently improve the performance of the semiconductor device (see, e.g., Wu: pars.0021/ll.25-26, 0022/ll.27-34, and 0032/ll.19-22). See the comments stated above in paragraphs 15-18, which are considered to be repeated here.
Regarding claim 19, Reznicek (see, e.g., fig. 8) shows that the barrier 20L, 20S, 30 has a u-shaped cross-section.
Regarding claim 20, Reznicek (see, e.g., fig. 8) shows that vertical arms 30 of the barrier 20L, 20S, 30 directly contact the bottommost surface of the source or drain 26.
Regarding claim 21, Reznicek (see, e.g., fig. 8) shows that the barrier 20L, 20S, 30 further comprises lateral wings 20S extending out from sides of the barrier.
Regarding claim 23, Reznicek (see, e.g., fig. 8) shows most aspects of the instant invention, including a semiconductor device comprising:
a substrate 10;
a vertical stack of semiconductor channels 14P over the substrate;
a source 26 at a first end of the semiconductor channels;
a drain 26 at a second end of the semiconductor channels; and
a barrier 20L, 20S, 30 between a bottommost surface of the source or the drain and the substrate, the barrier in contact with the bottommost surface of the source or the drain, wherein the barrier has an uppermost surface and the substrate has an uppermost surface; and
an oxide 22 between the barrier and the source or the drain, the oxide in contact with the bottommost surface of the source of the drain (see, e.g., col.8/ll.16-17)
Reznicek (see, e.g., col.11/ll.46-54) discloses that the device of Reznicek can include further modifications within the scope of the device, but fails to specify that these modifications may include an electronic system comprising a board, a package substrate coupled to the board, and a die housing the semiconductor device of Reznicek. Guha, possessing a similar structure to Reznicek, teaches that having an electronic system, shown to house a board, and a die housing a semiconductor device substantially similar to that of Reznicek (see, e.g., par.0089/ll.1-6), taught to be coupled to a package substrate (see, e.g., par.0089/ll.1-2 and par.0090/ll.1-2), may facilitate the processing of electronic data from registers and/or memory and the transformation of said electronic data into other electronic data that may also be stored in registers and/or memory (see, e.g., Guha: fig. 15 and pars.0088/ll.1-2, 0089, and 0091).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Reznicek to include the electronic system, package substrate, and inclusive coupled die of Guha, so as to facilitate the processing, storing, and transformation of data from the device of Reznicek.
Reznicek specifies that the substrate 10 is composed of any semiconducting material (see, e.g., col.3/ll.52-60) and fails to specify that the substrate could be dielectric. Guha, in a similar device to Reznicek, teaches semiconducting and dielectric substrates to be equivalent to each other (see, e.g., Guha: par.044/ll.1-20). Guha further suggests that a dielectric substrate would allow adjustments in the quality of the stack of layers formed on the substrate of Reznicek (see, e.g., Guha: figs. 3A-3B and par.0044/ll.16-20).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the dielectric substrate of Guha in the semiconductor device of Reznicek to achieve a desired quality for the stack of semiconductor channels posited over the substrate.
Furthermore, although Reznicek teaches most aspects of the instant invention, Reznicek fails to explicitly specify that Reznicek’s barrier has an uppermost surface below an uppermost surface of the substrate. Wu, in the same field of endeavor, teaches a semiconductor device 200 having a barrier 226 in contact with a source or drain 240, wherein the barrier has an uppermost surface below an uppermost surface of a substrate 202 (see, e.g., Wu: figs. 8 and 14). Wu further teaches that when a barrier has an uppermost surface below an uppermost surface of a substrate that the structure facilitates the formation of air gaps, which can reduce parasitic capacitance and subsequently improve the performance of the semiconductor device (see, e.g., Wu: pars.0021/ll.25-26, 0022/ll.27-34, and 0032/ll.19-22).
Wu is evidence showing that one of ordinary skill in the art would appreciate that having a barrier with an uppermost surface below an uppermost surface of a substrate would be equivalent to having a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, and that such differences would result in no unexpected changes in the performance of the device of Reznicek. That is, the barrier structures of both Reznicek and Wu would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a barrier with an uppermost surface below an uppermost surface of a substrate, as taught by Wu, or a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, as taught by Reznicek, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Wu is evidence that, at the time of filing the invention, it would have been obvious to one of ordinary skill in the art to include a barrier whose uppermost surface is below an uppermost surface of a substrate in the device of Reznicek, because such a configuration would facilitate the formation of air gaps, as taught by Wu, thereby reducing parasitic capacitance and improving the performance of Reznicek’s semiconductor device.
Regarding claim 24, Reznicek (see, e.g., fig. 8) shows that the barrier 20L, 20S, 30 has a u-shaped cross-section. Furthermore, Guha (see, e.g., fig. 11A) also shows that the barrier 350 has a u-shaped cross-section.
Regarding claim 25, Reznicek (see, e.g., fig. 8) shows that the barrier 20L, 20S, 30 further comprises lateral wings 20S. Furthermore, Guha (see, e.g., fig. 11A) also shows that the barrier 350 further comprises lateral wings.
Claims 1, 3-6, 9-11, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Guha in view of Wu and Cheng (US 2020/0227305).
Regarding claim 1, Guha (see, e.g., fig. 11A and par.0044/ll.16-20) shows most aspects of the instant invention, including a semiconductor device comprising:
a substrate 300, wherein the substrate is a dielectric material;
a vertical stack of semiconductor channels 312 over the substrate;
a source 360 at a first end of the semiconductor channels;
a drain 360 at a second end of the semiconductor channels; and
a barrier (350 below 360 and below lowermost 312 closest to 300) between a bottommost surface of the source or the drain and the substrate, the barrier in contact with the bottommost surface of the source or the drain, wherein the barrier has an uppermost surface and the substrate has an uppermost surface
Although Guha teaches most aspects of the instant invention, Guha fails to explicitly specify that Guha’s barrier has an uppermost surface below an uppermost surface of the substrate. Wu, in the same field of endeavor, teaches a semiconductor device 200 having a barrier 226 in contact with a source or drain 240, wherein the barrier has an uppermost surface below an uppermost surface of a substrate 202 (see, e.g., Wu: figs. 8 and 14). Wu further teaches that when a barrier has an uppermost surface below an uppermost surface of a substrate that the structure facilitates the formation of air gaps, which can reduce parasitic capacitance and subsequently improve the performance of the semiconductor device (see, e.g., Wu: pars.0021/ll.25-26, 0022/ll.27-34, and 0032/ll.19-22).
Wu is evidence showing that one of ordinary skill in the art would appreciate that having a barrier with an uppermost surface below an uppermost surface of a substrate would be equivalent to having a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, and that such differences would result in no unexpected changes in the performance of the device of Guha. That is, the barrier structures of both Guha and Wu would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a barrier with an uppermost surface below an uppermost surface of a substrate, as taught by Wu, or a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, as taught by Guha, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Wu is evidence that, at the time of filing the invention, it would have been obvious to one of ordinary skill in the art to include a barrier whose uppermost surface is below an uppermost surface of a substrate in the device of Guha, because such a configuration would facilitate the formation of air gaps, as taught by Wu, thereby reducing parasitic capacitance and improving the performance of Guha’s semiconductor device.
Additionally, Guha teaches most aspects of the instant invention, wherein Guha further teaches that Guha’s device includes adjacent source/drain regions (see, e.g., Guha: fig. 11A). Guha, however, fails to specify that an oxide is between Guha’s barrier and source or drain, wherein the oxide is in contact with the bottommost surface of the source or the drain. Cheng, in the same field of endeavor and in a similar structure to Guha, teaches that the inclusion of an oxide 1002 between a barrier 902 and a source or drain 1104, shown such that the oxide is in contact with a bottommost surface of the source or the drain, prevents parasitic transistor leakage between adjacent source/drain regions and prevents the source/drain regions from growing underneath channel regions (see, e.g., Cheng: fig. 13 and par.0047/ll.1-5).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Guha to include an oxide between the barrier and the source or the drain, the oxide in contact with the bottommost surface of the source or the drain, as taught by Cheng, so as to advantageously prevent parasitic transistor leakage between Guha’s adjacent source/drain regions and Guha’s source/drain regions from growing underneath Guha’s channel regions.
Regarding claim 3, Guha (see, e.g., fig. 11A) shows that the barrier (350 below 360 and below lowermost 312 closest to 300) has a u-shaped cross-section.
Regarding claim 4, Guha (see, e.g., pars.0044/ll.16-17 and 0060/ll.1-3) shows that the barrier (350 below 360 and below lowermost 312 closest to 300) is a dielectric material that is a different material than the substrate 300.
Regarding claim 5, Guha (see, e.g., fig. 11A) shows a gate stack 334/336 around the vertical stack of semiconductor channels 312, wherein edge surfaces of the gate stack are contacted by spacers (332 and all 350 above lowermost 312 closest to 300).
Regarding claim 6, Guha (see, e.g., fig. 11A and par.0060/ll.11-12) shows that the spacers (332 and all 350 above lowermost 312 closest to 300) and the barrier (350 below 360 and below lowermost 312 closest to 300) comprise the same material.
Regarding claim 9, Guha (see, e.g., fig. 11A) shows that a cross-section of the barrier (350 below 360 and below lowermost 312 closest to 300) is u-shaped with lateral wings.
Regarding claim 10, Guha (see, e.g., fig. 11A) further shows a semiconductor region 360 or 312 contacting the lateral wings.
Regarding claim 11, Guha (see, e.g., fig. 11A) shows that the lateral wings are on opposite sides of the u-shape.
Regarding claim 23, Guha (see, e.g., fig. 11A and fig. 15 and par.0044/ll.16-20) shows most aspects of the instant invention, including an electronic system 1000 comprising:
a board 1002;
a package substrate (see, e.g., par.0089/ll.1-2 and par.0090/ll.1-2) coupled to the board; and
a die (see, e.g., par.0089/ll.1-6) coupled to the package substrate;
wherein the die comprises:
a substrate 300, wherein the substrate is a dielectric material;
a vertical stack of semiconductor channels 312 over the substrate;
a source 360 at a first end of the semiconductor channels;
a drain 360 at a second end of the semiconductor channels; and
a barrier 350 between a bottommost surface of the source or the drain and the substrate, the barrier in contact with the bottommost surface of the source or the drain, wherein the barrier has an uppermost surface and the substrate has an uppermost surface
Although Guha teaches most aspects of the instant invention, Guha fails to explicitly specify that Guha’s barrier has an uppermost surface below an uppermost surface of the substrate. Wu, in the same field of endeavor, teaches a semiconductor device 200 having a barrier 226 in contact with a source or drain 240, wherein the barrier has an uppermost surface below an uppermost surface of a substrate 202 (see, e.g., Wu: figs. 8 and 14). Wu further teaches that when a barrier has an uppermost surface below an uppermost surface of a substrate that the structure facilitates the formation of air gaps, which can reduce parasitic capacitance and subsequently improve the performance of the semiconductor device (see, e.g., Wu: pars.0021/ll.25-26, 0022/ll.27-34, and 0032/ll.19-22).
Wu is evidence showing that one of ordinary skill in the art would appreciate that having a barrier with an uppermost surface below an uppermost surface of a substrate would be equivalent to having a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, and that such differences would result in no unexpected changes in the performance of the device of Guha. That is, the barrier structures of both Guha and Wu would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a barrier with an uppermost surface below an uppermost surface of a substrate, as taught by Wu, or a barrier with an uppermost surface possessing another relation to an uppermost surface of a substrate, as taught by Guha, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitably-formed and positioned barricade physically separating a substrate from a source or drain structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Wu is evidence that, at the time of filing the invention, it would have been obvious to one of ordinary skill in the art to include a barrier whose uppermost surface is below an uppermost surface of a substrate in the device of Guha, because such a configuration would facilitate the formation of air gaps, as taught by Wu, thereby reducing parasitic capacitance and improving the performance of Guha’s semiconductor device.
Additionally, Guha teaches most aspects of the instant invention, wherein Guha further teaches that Guha’s device includes adjacent source/drain regions (see, e.g., Guha: fig. 11A). Guha, however, fails to specify that an oxide is between Guha’s barrier and source or drain, wherein the oxide is in contact with the bottommost surface of the source or the drain. Cheng, in the same field of endeavor and in a similar structure to Guha, teaches that the inclusion of an oxide 1002 between a barrier 902 and a source or drain 1104, shown such that the oxide is in contact with a bottommost surface of the source or the drain, prevents parasitic transistor leakage between adjacent source/drain regions and prevents the source/drain regions from growing underneath channel regions (see, e.g., Cheng: fig. 13 and par.0047/ll.1-5).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the structure of Guha to include an oxide between the barrier and the source or the drain, the oxide in contact with the bottommost surface of the source or the drain, as taught by Cheng, so as to advantageously prevent parasitic transistor leakage between Guha’s adjacent source/drain regions and Guha’s source/drain regions from growing underneath Guha’s channel regions.
Regarding claim 24, Guha (see, e.g., fig. 11A) shows that the barrier 350 has a u-shaped cross-section.
Regarding claim 25, Guha (see, e.g., fig. 11A) shows that the barrier 350 further comprises lateral wings.
Response to Arguments
The applicants argue:
Reznicek fails to show an oxide between Reznick’s barrier 20L, 20S, 30 and source or drain 26, wherein the oxide is in contact with a bottommost surface of Reznicek’s source or drain, as Reznicek fails to show that element 22 is in contact with a bottommost surface of the source/drain.
The examiner responds:
Reznicek shows these features of the claimed invention. See, for example, Reznicek’s oxide 22 and barrier 20L, 20S, 30 in figure 8, wherein Reznicek shows that Reznicek’s oxide indirectly contacts a bottommost surface of a source 26 or drain 26.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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