DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
No replacement drawings have been filed, the objection thereof is repeated.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 588, 592, 590, & 596 (all belonging to figs. 6A & 6b). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Request for Rejoinder
The Applicant requests rejoinder for withdrawn claims 12-20 on the basis that they include the limitations added to claims 1 and 7 by amendment. Such reasoning is not sufficient for rejoinder as the Applicant has not obviated the reason for restriction; being that the products which can be made by the method claims are materially different than the products of the apparatus claims.
Response to Arguments
Applicant’s arguments have been fully considered, but are not persuasive.
Applicant submits that the amendments made to the claims place them in condition of allowance, the Examiner disagrees. The terms added to the independent claims by amendment require certain elements to be separate and distinct. Such limitations are satisfied by the primary reference, Pethe. To state it differently, the primary reference can teach that certain elements are separate and distinct without being required to teach that these same elements are tapered, as required by the independent claims.
Additionally, the terms ‘separate’ and ‘distinct’ allow for an element (i.e., the interpretation thereof) of the cited references to be sectioned by drawing arbitrary lines therein as displayed in the rejection of claim 7 below. It is suggested that the Applicant amend the claims to recite a differing material property concerning these elements at issue e.g., differing composition through doping; as these limitations would force the current rejection to be untenable.
Claim Rejections - 35 USC § 112
Claim 7 is amended to obviate the issue of antecedent basis previously present therein. The rejection is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 4, 6-9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20140077305 A1 to Pethe et al. (hereinafter “Pethe”) in view of U.S. Pat. Pub. No. US 20150076708 A1 to Kaneko et al. (hereinafter “Kaneko”).
Regarding claim 1, Pethe teaches an integrated circuit structure (structure of fig. 3F) [0015], comprising:
a gate structure (gate stack structure 308c, fig. 3F) [0043] above a channel structure (semiconductor channel surrounded by gate stack structure 308c, the channel not being pictured) [0034], the gate structure (308c) comprising a gate (gate electrode within gate structure 308c, fig. 3F) [0043] and a gate dielectric (gate dielectric disposed within gate structure 308c) [0043];
a first conductive via (trench contact 311a, fig. 3F) [0048] having a bottom side (bottom thereof) and a top side (top thereof) opposite the bottom side (bottom), the bottom side (bottom) of the first conductive via (311a) electrically coupled (through metal contact structure 340, fig. 3F) [0058] with the gate (308c),
a second conductive via (trench contact via 341a, fig. 3F) [0058] having a bottom side (bottom thereof) and a top side (top thereof) opposite the bottom side (bottom), the bottom side (bottom) of the second conductive via (second via) electrically coupled with the top side (top) of the first conductive via (311a).
the second conductive via (341a) separate and distinct from the first conductive via (311a).
Pethe does not teach:
the first conductive via (311a) having outwardly tapered walls (getting larger from bottom to top) extending from the bottom side (bottom) of the first conductive via (311a) to the top side (top) of the first conductive via (first via).
the second conductive via (341a) having inwardly tapered walls (getting smaller from bottom to top) from the bottom side (bottom) of the second conductive via (341a) to the top side (top) of the second conductive via (341a).
Kaneko, however, teaches a semiconductor device (abstract) in fig. 1 comprising:
the first conductive via (lower contact plug 6, fig. 1) [0073] having outwardly tapered walls (getting larger from bottom to top) extending from the bottom side (bottom) of the first conductive via (6) to the top side (top) of the first conductive via (6).
the second conductive via (upper contact plug 9) [0074] having inwardly tapered walls (getting smaller from bottom to top) from the bottom side (bottom) of the second conductive via (9) to the top side (top) of the second conductive via (9).
It would have been obvious to the POSITA before the effective filing date of the invention, to modify the first and second conductive vias of Pethe to comprise outward taper and an inward taper, respectively, as taught by Kaneko in fig. 1 to reduce parasitic capacitance between the first and second conductive vias as taught by Kaneko in [0088].
Regarding claim 3, Pethe in view of Kaneko teaches an integrated circuit structure (structure of fig. 3F) [0015], according to claim 1 further comprising a metallization layer (through metal contact structure 340, fig. 3F) [0058] electrically coupled with the top side (top) of the second conductive via (341a).
Regarding claim 4, Pethe in view of Kaneko teaches an integrated circuit structure (structure of fig. 3F) [0015], according to claim 1 further comprising a barrier liner (insulating cap layer 324) [0048] between (touching both) the bottom side (bottom) of the second conductive via (341a) and the top side (top) of the first conductive via (311a).
Regarding claim 6, Pethe in view of Kaneko teaches an integrated circuit structure (structure of fig. 3F) [0015], according to claim 1 wherein the first metal via (311a) and the second metal via (341a) include copper [0058]-[0059].
Regarding claim 7, Pethe teaches an integrated circuit structure (structure of fig. 3F) [0015], comprising:
a trench connector (through metal contact structure 340, fig. 3F) [0058] above a source or drain structure (structure of trench contacts 311a or 341c also referred to as “source drain contacts,” see [0026] and fig. 3F), the trench connector (340) comprising a conductive metal [0058];
a first conductive via (trench contact 311a, fig. 3F) [0048] having a bottom side (bottom) and a top side (top) opposite the bottom side (bottom), the bottom side (bottom) of the first conductive via (311a) electrically coupled with the trench connector (340),
a second conductive via (trench contact via 341a, fig. 3F) [0058] having a bottom side (bottom) and a top side (top) opposite the bottom side (bottom), the bottom side (bottom) of the second conductive via (341a) electrically coupled with the top side (top) of the first conductive via (311a),
a third conductive via (gate contact via 342a, fig. 3F) [0058] having a first side (left side in fig. 3F) and a second side (right side in fig. 3F) opposite the first side (left), the bottom side (bottom) of the third conductive via (342a) electrically coupled with a gate structure (gate stack structure 308c, fig. 3F) [0043] above a channel structure (semiconductor channel surrounded by gate stack structure 308c, the channel not being pictured) [0034], the gate structure (308c) comprising a gate (gate electrode within gate structure 308c, fig. 3F) [0043] and a gate dielectric (gate dielectric disposed within gate structure 308c) [0043];
wherein the first conductive via (311a) and the third conductive via (342a) are within a layer (area indicated below between element 330 and the substrate beneath) of the integrated circuit structure.
a fourth conductive via (annotated below as “fourth via”) on the third conductive via (342a annotated below as “third via”), the fourth conductive via (fourth via) separate (located in a different location) and distinct (not overlapping in location) from the third conductive via (third via);
Pethe does not teach:
the first conductive via (311a) having outwardly tapered walls extending from the bottom side of the first conductive via to the top side of the first conductive via;
the second conductive via (341a) having inwardly tapered walls from the bottom side (bottom) of the second conductive via (311a) to the top side (top) of the second conductive via (341a);
wherein the third conductive via (342a) has outwardly tapered walls extending from the bottom side (bottom) of the third conductive via (342a) to the top side (top) of the third conductive via (342a).
Kaneko, however, teaches a semiconductor device (abstract) in fig. 1 comprising:
the first conductive via (lower contact plug 6 in edge position, fig. 1) [0073] having outwardly tapered walls (getting larger from bottom to top) extending from the bottom side (bottom) of the first conductive via (6) to the top side (top) of the first conductive via (6).
the second conductive via (upper contact plug 9 in edge position, fig. 1) [0074] having inwardly tapered walls (getting smaller from bottom to top) from the bottom side (bottom) of the second conductive via (9) to the top side (top) of the second conductive via (9).
wherein the third conductive via (lower contact plug 6 in non-edge position, fig. 1) has outwardly tapered walls (getting larger from bottom to top) extending from the bottom side (bottom) of the third conductive via (6) to the top side (top) of the third conductive via (6).
It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention, to modify the first, second, and third conductive vias of Pethe to comprise outward taper (first and third vias) and an inward taper (second via), as taught by Kaneko in fig. 1 to reduce parasitic capacitance as taught by Kaneko in [0088].
PNG
media_image1.png
572
1154
media_image1.png
Greyscale
Annotated fig. 3F of Pethe
PNG
media_image2.png
373
586
media_image2.png
Greyscale
Annotated fig. 3F of Pethe
Regarding claim 8, Pethe in view of Kaneko teaches an integrated circuit structure (structure of fig. 3F) [0015], according to claim 7 wherein the top side of the second conductive via (341a) is electrically coupled with a metallization layer (340).
Regarding claim 9, Pethe in view of Kaneko teaches an integrated circuit structure (structure of fig. 3F) [0015], according to claim 7 wherein the third conductive via (342a) is electrically coupled with the metallization layer (340).
Regarding claim 11, Pethe in view of Kaneko teaches an integrated circuit structure (structure of fig. 3F) [0015], according to claim 7 wherein the first conductive via (311a), the second conductive via (341a), and the third conductive via (342a) include copper [0058]-[0059].
Claims 2 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Pethe in view of Kaneko as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20140191309 A1 to Eguchi et al. (hereinafter “Eguchi”).
Regarding claim 2, Pethe in view of Kaneko does not teach an integrated circuit structure (structure of fig. 3F) [0015], according to claim 1 wherein the walls (side surfaces) of the first conductive via (311a) have a slope between 90º and 85º and wherein the walls of the second conductive via (341a) have a slope between 90º and 95º.
Eguchi, however, teaches a vertical MOSFET (abstract) in fig. 3 wherein the walls (side surfaces) of the first conductive via (column area llnb, fig. 3) [0130] have a slope between 90º and 85º (taper angle θ comprising an angle between 90º and 89.7º) [0111] and wherein the walls of the second conductive via (epitaxy column area 11nc, fig. 3) [0130] have a slope between 90º and 95º (taper angle θ comprising an angle between 90º and 89.7º) [0111].
It would have been obvious to the POSITA before the effective filing date of the invention, to set the taper angle of the first and second conductive vias of Pethe to an angle between 90º and 95º as taught by Eguchi to prevent an unpredictable breakdown voltage deterioration as taught by Eguchi in [0204].
Regarding claim 10, Pethe in view of Kaneko does not teach an integrated circuit structure (structure of fig. 3F) [0015], according to claim 7 wherein the walls of the first conductive via (311a) have a slope between 90° and 85° and wherein the walls (side surfaces) of the second conductive via (341a) have a slope between 90º and 95°.
Eguchi, however, teaches a vertical MOSFET (abstract) in fig. 3 wherein the walls (side surfaces) of the first conductive via (column area llnb, fig. 3) [0130] have a slope between 90º and 85º (taper angle θ comprising an angle between 90º and 89.7º) [0111] and wherein the walls of the second conductive via (epitaxy column area 11nc, fig. 3) [0130] have a slope between 90º and 95º (taper angle θ comprising an angle between 90º and 89.7º) [0111].
It would have been obvious to the POSITA before the effective filing date of the invention, to set the taper angle of the first and second conductive vias of Pethe to an angle between 90º and 95º as taught by Eguchi to prevent an unpredictable breakdown voltage deterioration as taught by Eguchi in [0204].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pethe in view of Kaneko as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20180269152 A1 to Sengupta et al. (hereinafter “Sengupta”).
Regarding claim 5, Pethe in view of Kaneko do not teach an integrated circuit structure (structure of fig. 3F) [0015], according to claim 1 wherein the bottom side of the first conductive via overlaps with a cut in the gate.
Sengupta, however, teaches an integrated circuit structure (abstract, fig. 1b) [0006], wherein the bottom side (bottom) of the first conductive via (metal stub 102 furthest right) [0003] overlaps with a cut (power supply trace 102) [0003] in the gate (metal stub 102 second from the right) [0003].
It would have been obvious to the POSITA before the effective filing date of the invention, to dispose a gate cut which overlaps the first conductive via and the gate in the substrate of Pethe to supply a connection pathway to a transistor, such as to a terminal thereof as taught by Sengupta in [0003].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892