DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 16 May 2025.
Election/Restrictions
Claims 21 and 22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant elected species 11 in the response dated 15 October 2025, in which the embodiment of the species required the first memory cell or the second memory cell includes a semiconductor material with an average grain size between 0.5 millimeter and 1 millimeter. The embodiment does not include another one of the first memory cell includes a semiconductor material with an average grain size greater than 1 millimeter or smaller than 0.5 millimeter as required by claims 21 and 22, respectively. Therefore claims 21 and 22 are distinct from the elected species and are withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. 2011/0143506) in view of Okumura (U.S. Pub. 2003/0032222).
Claim 1: Lee discloses an integrated circuit (IC) device, in Fig. 37 and in paragraphs 98-110, comprising:
a front end of line (FEOL) layer (30), comprising frontend transistors (310);
a first memory layer (20), comprising a first memory cell (210 and 244) that includes an access transistor (210) and a capacitor (244), coupled to the access transistor (210);
a second memory layer (10), comprising a second memory cell (210 and 244) that includes a selector device (210) and a storage element (244) coupled to the selector device (210), and
wherein the first memory layer (20) is between the FEOL layer (30) and the second memory layer (10).
Examiner notes that the “front end of line” of the front end of line layer and “frontend” of frontend of transistors seems to be referring to the process of manufacturing, particularly the timing of the process, and therefore are product-by-process recitations. A product-by-process recitation is not limited to the manipulations or timing of the recited step, only the structure implied by the step. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966. Therefore, the product-by-process recitations only require a layer comprising transistors.
Lee appears not to explicitly disclose wherein the first memory cell or the second memory cell includes a semiconductor material with an average grain size between 0.5 millimeter and 1 millimeter.
Okumura, however, in paragraph 3, discloses the grain size is a result-affecting parameter because it affects the mobility of carriers.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to optimize, for example by routine experimentation, the grain size of Lee in order to have the desired mobility of carriers according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Claim 2: Lee in view of Okumura discloses the IC device according to claim 1, and Lee, in Fig. 37 and in paragraph 109, further discloses wherein the first memory layer (20) and the second memory layer (10) are parts of a back end of line (BEOL) layer of the IC device.
Examiner notes that the “back end of line” of the back end of line layer seems to be referring to the process of manufacturing, particularly the timing of the process, and therefore is a product-by-process recitation. A product-by-process recitation is not limited to the manipulations or timing of the recited step, only the structure implied by the step. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966. Therefore, the product-by-process recitation only requires a first memory cell that includes an access transistor (210) and a capacitor, coupled to the access transistor; and a second memory layer, comprising a second memory cell that includes a selector device and a storage element coupled to the selector device.
Claim 3: Lee in view of Okumura discloses the IC device according to claim 1, and Lee, in paragraph 108, further discloses wherein at least one of the frontend transistors (310) is coupled to the first memory cell (210 and 244 in 20) and at least one of the frontend transistors (310) is coupled to the second memory cell (210 and 244 in 10).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Okumura as applied to claim 1 above, and further in view of Le et al. (U.S. Pub. 2019/0355725).
Claim 8: Lee in view of Okumura discloses the IC device according to claim 1.
Lee in view of Okumura appears not to explicitly wherein the access transistor is a thin-film transistor.
Le et al., however, in paragraph 20, discloses the access transistor is a thin-film transistor in order to simplify the manufacturing process.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee in view of Okumura with the disclosure of Le et al. to have made the access transistor is a thin-film transistor in order to simplify the manufacturing process (paragraph 20 of Le et al.).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Okumura as applied to claim 1 above, and further in view of Kwon et al. (U.S. Pub. 2018/0285252) and Trinh et al. (U.S. Pub. 2020/0044148).
Claims 9-12: Lee in view of Okumura discloses the IC device according to claim 1.
Lee in view of Okumura appears not to explicitly disclose, wherein:
the selector device includes a first electrode, a second electrode, and a selector material between the first electrode and the second electrode, and
the selector material includes a chalcogenide;
wherein the selector device further includes a getter layer between the second electrode and the selector material.
wherein the getter layer includes tantalum, titanium, hafnium, aluminum, or chromium.
wherein the getter layer further includes nitrogen.
Kwon et al., however, in paragraphs 44 and 122, discloses a memory module having a DRAM and a phase change cross-point memory, and Trinh et al., in Fig. 3B and in paragraphs 23, 25, 36, 40 and 47, discloses a phase change memory comprising the selector device (308) includes a first electrode (114), a second electrode (110), and a selector material (112) between the first electrode (114) and the second electrode (110),
the selector material (112) includes a chalcogenide
the selector device (308) further includes a getter layer (108) between the second electrode (110) and the selector material (112)
the getter layer (108) includes tantalum, titanium, hafnium, aluminum, or chromium.
the getter layer (108) further includes nitrogen.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee in view of Okumura with the disclosure of Kwon et al. to have made the memory module have a DRAM and a phase change cross-point memory. Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the disclosure of Kwon et al. in the same or in a similar field of endeavor with memory module of Lee in view of Okumura before the effective filing date of the claimed invention in order to substitute the phase change cross-point memory of Kwon et al. for the second memory layer (DRAM) of Lee. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the phase change cross-point memory of Kwon et al. for the second memory layer of Lee would have yielded predictable results, namely the memory having a DRAM and a phase change cross-point memory. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Further, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee in view of Okumura in view of Kwon et al. with the disclosure of Trinh et al. to have made the selector device include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode, and
the selector material includes a chalcogenide;
the selector device further includes a getter layer between the second electrode and the selector material.
the getter layer includes tantalum, titanium, hafnium, aluminum, or chromium.
the getter layer further includes nitrogen in order to increase the stability and endurance of the phase change memory (paragraph 23 of Trinh et al.).
Claim(s) 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Okumura as applied to claim 1 above, and further in view of Kwon et al. (U.S. Pub. 2018/0285252).
Claim 13: Lee in view of Okumura discloses the IC device according to claim 1.
Lee in view of Okumura appears not to explicitly disclose wherein the storage element is a resistive random-access memory (RRAM) device, a phase change memory (PCM) device, a metal filament memory device, or a magnetoresistive random-access memory (MRAM) device.
Kwon et al., however, in paragraphs 44 and 122, discloses a memory module having a DRAM and a phase change cross-point memory.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee in view of Okumura with the disclosure of Kwon et al. to have made the storage element a phase change cross-point memory. Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the disclosure of Kwon et al. in the same or in a similar field of endeavor with memory module of Lee in view of Okumura before the effective filing date of the claimed invention in order to substitute the phase change cross-point memory of Kwon et al. for the second memory layer (DRAM) of Lee. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the phase change cross-point memory of Kwon et al. for the second memory layer of Lee would have yielded predictable results, namely the memory having a DRAM and a phase change cross-point memory. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 15: Lee in view of Okumura discloses the IC device according to claim 1, and Lee, in Fig. 37 and in paragraphs 100 and 103, further discloses wherein:
the first memory cell (210 and 244 in 20) is one of a plurality of first memory cells of a memory array in the first memory layer (20),
the second memory cell (210 and 244 in 10) is one of a plurality of second memory cells of a memory array in the second memory layer (10), and
the memory array in the first memory layer (20) is a dynamic random-access memory array.
Examiner notes that a dynamic random-access memory is a memory in which is made up of a transistor and a capacitor. Since Lee discloses the first memory cell is made up of a transistor 210 and a capacitor 244, the memory array in the first memory layer would be a dynamic random-access memory array.
Lee in view of Okumura appears not to explicitly disclose the memory array in the second memory layer is a cross-point memory array.
Kwon et al., however, in paragraphs 44 and 122, discloses a memory module having a DRAM and a phase change cross-point memory.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee in view of Okumura with the disclosure of Kwon et al. to have made the memory array in the second memory layer is a cross-point memory array. Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the disclosure of Kwon et al. in the same or in a similar field of endeavor with memory module of Lee in view of Okumura before the effective filing date of the claimed invention in order to substitute the phase change cross-point memory of Kwon et al. for the second memory layer (DRAM) of Lee. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the phase change cross-point memory of Kwon et al. for the second memory layer of Lee would have yielded predictable results, namely the memory having a DRAM and a phase change cross-point memory. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Okumura as applied to claim 1 above, and further in view of Izumi (U.S. Pub. 2010/0320521).
Claim 14: Lee in view of Okumura discloses the IC device according to claim 1, and in Fig. 37 and in paragraph 85, Lee further discloses comprising:
a first bit-line (224), coupled to a first terminal (212) of the first memory cell (210 and 244 in 20), and
a second bit-line (224), coupled to a first terminal (212) of the second memory cell (210 and 244 in 30).
Lee in view of Okumura appears not to explicitly disclose a first word-line, coupled to a second terminal of the first memory cell,
a second word-line, coupled to a second terminal of the second memory cell.
Izumi, however, in abstract, discloses a word-line (word line) coupled to a terminal (gate electrode) of the memory cell in order to control the storage of information in the memory cell.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee in view of Okumura with the disclosure of Le et al. to have made a first word-line, coupled to a second terminal of the first memory cell,
a second word-line, coupled to a second terminal of the second memory cell in order to control the storage of information in the memory cell (abstract of Izumi).
Response to Arguments
Applicant's arguments filed 15 May 2025 have been fully considered but they are not persuasive.
Applicant contends Okumura is silent as to the grain size of a semiconductor material in a memory cell being between 0.5 millimeter and 1 millimeter.
Examiner notes Okumura is not relied upon for an explicit disclosure of a semiconductor material with a grain size between 0.5 millimeter and 1 millimeter, rather, Okumura is relied upon for the disclosure that the grain size is a result-affecting parameter.
Since Okumura, in paragraph 3, discloses the grain size is a result-affecting parameter because it affects the mobility of carriers, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to optimize, for example by routine experimentation, the grain size of Lee in order to have the desired mobility of carriers according to well-established patent law precedents (see M.P.E.P. § 2144.05).
Applicant contends paragraph 3 of Okumura states relatively small grain size is not desirable for ICs, therefore, a person of ordinary skill in the art would not decide to include a semiconductor material with an average grain size between 0.5 millimeter and 1 millimeter in a first or second memory cells.
Examiner notes paragraph 3 of Okumura does not mention relatively small grain size is not desirable, but states grain size affects mobility of carriers.
Applicant contends neither Lee nor Okumura teaches or suggests stacking multiple memory layers over the FEOL layer using monolithic integration and therefore the combination is improper hindsight.
Examiner notes the claims do not require monolithic integration. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.L/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815