DETAILED ACTION
Claims 1-25 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The replacement abstract of the disclosure is objected to because of the following minor informalities:
In line 2, replace the second instance of “includes” with --including--.
From MPEP 714(II)(B), where the amendments to the abstract are minor in nature, the abstract should be provided as a marked-up version under 37 CFR 1.121(b)(2)(ii) using strike-through and underlining as the methods to show all changes relative to the immediate prior version. The replacement abstract must comply with 37 CFR 1.72(b) regarding the length and placement of the abstract on a separate sheet of paper.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The amended disclosure is objected to because of the following informalities:
In paragraph 369, line 1, replace “one or more” with --at least one--. Currently, “one or more…sub-core” is grammatically incorrect.
In paragraph 385, the examiner questions whether the formula is correct. As the examiner best understands it (and its parameters), applicant provides a base address of the memory (Surface_Base) and an offset of the block to be loaded (block_y). Adding these two together would presumably point to the top row of the matrix to be loaded. Thus, to access a 2nd row, 3rd row, etc., of the matrix, applicant also has a parameter ‘n’. So to access row 0, n is set to 0, and base+offset would point to row 0. To access row 1, n is set to 1, and base+offset+1 would point to row 1, which would be understood if there were not multiple elements per row. Applicant appears to be addressing individual elements in a given row in FIG.29B. Thus, adding 1 to base+offset appears to point to the 2nd element of the row, not the 2nd row (see FIGs.29A-C). As such, the examiner is unclear on how the disclosed formula actually works. The examiner questions if the formula should instead be:
Rowbase[n] = Surface_Base + block_y + n * Surface_Pitch.
Based on the examples, it appears that Surface_Pitch is the number of elements per row (width of memory containing the block) and, thus, to get to a next row, you need to multiply only n by Surface_Pitch. If the current formula is correct, applicant needs to further explain with reference to the examples.
In paragraph 388, applicant states that “GRFs may be part of a register file”. Is this still correct given changes made to paragraphs [00391] and [00394]?
Appropriate correction is required.
Drawings
The large set of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings.
Claim Objections
Claim 22 is objected to because of the following informalities:
Applicant claims the medium further comprises a step of utilizing. However, the medium does not comprise an active step. Instead, the medium comprises instructions that cause the step of utilizing to be performed. Or, the operations of claim 21, line 3, can be claimed to comprise the utilizing.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Per MPEP 2164.01(a), there are many factors to be considered when determining whether there is sufficient evidence to support a determination that a disclosure does not satisfy the enablement requirement and whether any necessary experimentation is “undue.” These factors include, but are not limited to:
(A) The breadth of the claims;
(B) The nature of the invention;
(C) The state of the prior art;
(D) The level of one of ordinary skill;
(E) The level of predictability in the art;
(F) The amount of direction provided by the inventor;
(G) The existence of working examples; and
(H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure.
In re Wands, 858 F.2d 731, 737, 8 USPQ2d 1400, 1404 (Fed. Cir. 1988)
Each of the independent claims sets forth sequentially numbering general register files (GRFs) and causing the sequentially numbered GRFs to be available to processing resources in response to a single load with transpose message (factor A). Thus, taking applicant’s FIG.27 as an example, it appears what is being claimed is one of register files 2715 is numbered N and another one of the register files 2715 is numbered N+1. The nature of the invention is to load an array/matrix from memory into registers in transposed form (factor B). Regarding factors C-D, a register file is understood by one of ordinary skill in the art to be a collection of registers, and multiple previously-cited prior art references set forth sequentially numbering registers for a load with transpose operation (e.g. see at least FIG.3b of Ahmed (d0-d3), and at least column 24, lines 34-67, of Van Hook). The prior art does not explicitly teach numbering register files. A broad interpretation of the prior art could realize such a teaching, but it is not clear applicant is numbering the same way (e.g. applicant never appears to describe a register file including multiple sub-register files). Thus, the prior art generally does not assist one of ordinary skill in the art to make and use the invention as claimed. With respect to factors F-G, there is no direction provided by applicant as to how multiple register files are numbered or why. The working examples of FIGs.28A-30C only show that numbering happens and do not adequately explain how this actually works or is implemented (e.g. the algorithm for assigning numbers, where the numbers are stored and how they would be accessed to perform the operation, etc.). In some cases, the original disclosure adds to the confusion because at least paragraphs 388, 391, and 394 seem to discuss numbering registers and not register files. Also unclear is how register files are caused to be available to the processing resources. Register files are understood by one of ordinary skill in the art as hardware designed to be available to execution units for accessing and storing data (e.g. paragraphs 288, 291, and 370). Applicant hasn’t clearly explained how the load store pipeline return circuitry actually causes the numbered GRFs to be available when they are already available for use. Thus, even though the computer arts are generally predictable (factor E), the totality of evidence suggests that applicant has not enabled one of ordinary skill to make/use, without undue experimentation, the invention of the independent claims that numbers and causes availability of register files.
All dependent claims are rejected due to their dependence on a non-enabled claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eyole et al., U.S. Patent Application Publication No. 2017/0031865 A1 (as previously cited).
Referring to claim 1, Eyole has taught a processor (at least part of FIG.1) comprising:
processing resources (FIG.1, various components); and
load store pipeline hardware circuitry (see FIG.1, at least LSU 40. The load/store unit (LSU) is part of a pipeline (paragraph [0052]) and, thus, is pipeline hardware circuitry) coupled to the processing resources (the LSU is coupled to various resources of the processor), the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources (the message of FIG.3 would be received by the LSU from fetch, decode and issue resources in FIG.1. The message is a 2D block load message that can load any size data elements, including 64-bit elements (paragraph [0071]). Also, from FIGs.4-5, it can be seen that the load transposes data. In the example shown, first elements Rx of each row are re-arranged so as to be in sequential order in a destination register), wherein the load store pipeline hardware circuitry comprises:
a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages (see FIGs.4-5. The message is converted into standard gather/load instructions (step 305) for loading row elements. The gathers are 64-bit instructions when the initial message is a 64-bit message); and
load store pipeline return circuitry to:
sequentially number general register files (GRFs) used for making available elements of the block of memory accessed by the 64-bit standard load messages to the processing resources (from FIG.3 and paragraphs [0062]-[0063], the message indicates a group of N destination registers (FIG.4 shows N=3, where Z0, Z1, and Z2 are indicated). The first register is “numbered” 1 (to obtain the first data), the second register is numbered 2 (to obtain the second data), and so on. A vector register file 70 having a number of vector registers, can be arbitrarily divided into some number of vector sub-register files (which are still register files). For instance, if there are 16 vector registers in register file 70, this can be seen as eight sub-register files having two vector registers each. Thus, Z0-Z2 would span multiple register files, and the Z0-Z1 file (e.g. GRF1) would be numbered 1 and 2 (corresponding to Z0 and Z1) and the Z2-Z3 file (e.g. GRF2) would be numbered 3 (corresponding to Z2). Any number of registers can be loaded and any number of sub-register files can be arbitrarily defined and, thus, many different numbering arrangements can be realized. For instance, if there are two register files (one having Z0-Z7 and another having Z8-Z15), and the load message loads Z6, Z7, Z8, and Z9, then the first file would be numbered 1 and 2 and the second file would be numbered 3 and 4. The values loaded into the registers are ultimately made available to other components, e.g. execution units 30, 36, etc.); and
cause the sequentially numbered GRFs to be available to the processing resources in response to the 64-bit 2D block load message with transpose (again, by loading values into the registers, these values (and the registers they’re in) are caused to be available to other execution units for further processing/operation. In the first example above, once Z0, Z1, and Z2 are loaded, this data (and GRFs 1 and 2) become available to other parts of the system for further operation).
Referring to claim 2, Eyole has taught the processor of claim 1, wherein the load store pipeline sequencer is to utilize a plurality of buffers to map each of the rows of the block of memory to the 64-bit standard load messages (see FIG.1, buffers 60; FIG.5, step 310; and paragraph [0048]).
Referring to claim 3, Eyole has taught the processor of claim 1, wherein the load store pipeline sequencer to map the rows of the block of memory further comprises the load store pipeline sequencer to:
for each row 'n' of the block of memory, determine a rowbase address of the row 'n' of the block of memory (see FIG.4. A base address Xb is provided and Rs*i is added to Xb multiple times to locate the address of each row with addresses S[0], S[1], S[2], etc.); and
map the each row 'n' of the block of memory to the 64-bit standard load messages accessing the rowbase address for the row 'n' (again, from FIGs.4-5 and FIG.2, the rows are mapped to standard loads).
Referring to claim 4, Eyole has taught the processor of claim 1, wherein the block of memory comprises (from paragraph [0071], data elements may be various sizes, including 8 bits. If there is an 8-bit element to be loaded from memory, then the block includes at least 1 element of 8 bits, i.e., an 8 x 1 block)(note that struck through language is not required by the claim).
Referring to claim 5, Eyole has taught the processor of claim 1, wherein the 64-bit standard load messages comprise at least one of a v4 load message with a 4 element block width (see FIG.5, step 305. One standard load (gather) will load, R0, R1, R2, and any others required. For instance, from FIG.4, there is also R3. Thus, the first gather for FIG.4 would load a block of four elements)
Referring to claim 6, Eyole has taught the processor of claim 1, wherein the GRFs are comprised in the processing resources (see FIG.1. Registers 45 may be considered part of the resources to which LSU 40 is coupled).
Referring to claim 7, Eyole has taught the processor of claim 1, wherein the load store pipeline return circuitry is to sequentially number the GRFs in a packed format (from FIGs.2 and 5-6, the destination registers are packed registers where multiple values are packed into a single vector register, as is known. Thus, Z0 is packed with R0, R1, R2, etc. And, as described in the rejection of claim 1, the files are numbered).
Referring to claim 8, Eyole has taught the processor of claim 1, wherein the processor comprises a graphics processing unit (GPU) (from paragraphs [0004], [0075]-[0076], and others, the processing unit is operating on pixels, which are related to graphics. Thus, the processor is a graphics processing unit).
Referring to claim 9, Eyole has taught the processor of claim 1, wherein the processor is at least one of a single instruction multiple data (SIMD) machine (see paragraph [0003]. Having vector registers and the operations of FIG.6-7 are also indicative of a SIMD machine).
Claims 10-15 are rejected for similar reasoning as claims 1-5 and 7, respectively.
Claim 16 is rejected for similar reasoning as claim 1, where the claimed memory is memory 55 and the other components coupled thereto form the claimed processor.
Claims 17-20 are rejected for similar reasoning as claims 2-4 and 7, respectively.
Claim 21 is rejected for similar reasoning as claim 1, where Eyole include a medium with program instructions to carry out the operations of the claim (see paragraph [0009] and claim 25, or alternatively, note that the instruction of FIG.3 is part of a program that must be stored in some memory to be executed).
Claims 22-25 are rejected for similar reasoning as claims 2-5, respectively.
Response to Arguments
On page 11 of applicant’s response, applicant argues that paragraph [00396] of the specification supports how or why multiple register files need to be numbered.
This is not persuasive. The examiner had already considered paragraph [00396] before giving the enablement rejection. Given the Wands factors addressed in the 112 rejection, disclosure in paragraph [00396] does not remedy an overall deficiency in enabling the claimed invention. The examiner still does not understand how the system is numbering register files, nor why multiple register files are even needed for the load.
Conclusion
The following prior art previously made of record and not relied upon is considered pertinent to applicant's disclosure:
Ahmed, 2014/0331032, has taught a streaming memory transpose instruction (e.g. FIGs.2A, 2B, and 3B), that consecutively numbers registers and stores transposed data to those registers through multiple “standard” loads (e.g. FIG.3B, 352).
Jha, 2017/0177340, has taught a load instruction that transposes and stores data into multiple consecutive registers (e.g. FIG.2).
Van Hook, 5,812,147, has taught formatting data while moving data between memory and a vector register file. This includes executing a Load Transposed to Vector Unit (LTV instruction), which writes data to consecutively numbered registers of a register file (e.g. see FIGs.6A-7A).
Bradford, 2019/0042248, has taught a matrix transpose instruction 301 that transposes a source matrix using at least one load buffer before writing (serially or in parallel) to multiple registers (e.g. see FIG.3A).
Stephens, 2023/0289186, has taught a data transfer instruction for on-the-fly transposition when transferring data between memory and register storage.
Heinecke, 2020/0201640, has taught transposing vectors on the fly while loading from memory.
Sade, 2019/0042202, has taught a TileTranRect instruction that transposes data from a source to destination, each of which may be memory or collection of registers (e.g. see FIGs.21-24).
Jha, 2014/0013083, has taught a single transpose instruction performed by a coprocessing unit 470 to transpose data before storage into a register. This reduces instructions executed and saves resources in the execution engine 415 (paragraph 79).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights