Prosecution Insights
Last updated: April 19, 2026
Application No. 17/360,986

ULTRA-LOW-POWER AND LOW-AREA SOLUTION OF BINARY MULTIPLY-ACCUMULATE SYSTEM AND METHOD

Non-Final OA §101§112
Filed
Jun 28, 2021
Examiner
VICARY, KEITH E
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
STMicroelectronics
OA Round
5 (Non-Final)
58%
Grant Probability
Moderate
5-6
OA Rounds
3y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allow Rate
393 granted / 683 resolved
+2.5% vs TC avg
Strong +41% interview lift
Without
With
+41.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
41 currently pending
Career history
724
Total Applications
across all art units

Statute-Specific Performance

§101
8.7%
-31.3% vs TC avg
§103
34.0%
-6.0% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
37.6%
-2.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 683 resolved cases

Office Action

§101 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 19, 2025, has been entered. Claims 1-5, 8-12, and 15-19 are pending in this office action and presented for examination. Claims 1, 8, and 15 are newly amended, and claims 6, 13, and 20 are newly canceled, by the RCE received October 9, 2025. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 5, 8-12, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation “the selected subset of input bits” in line 5. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether this limitation is intended to have antecedent basis to the selected subset of input bits of the limitation “selecting, using the source-register location, a subset of the plurality of input bits” in claim 1, line 11, or whether this limitation is intended to have antecedent basis in some manner to one or more instances of a selected “another subset of the plurality of input bits” in claim 1, line 24. For example, this limitation does not appear to have antecedent basis in view of the lack of “the plurality of” language. For the purposes of this office action, Examiner is interpreting this limitation as “the corresponding selected subset of the plurality of input bits”. Claim 8 recites the limitation “the subset of weight bits” in line 10. However, there is insufficient antecedent basis for this limitation in the claims. For the purposes of prior art analysis, Examiner is interpreting this limitation as “the subset of the plurality of weight bits”. Claim 8 recites the limitation “the size of the subset of the plurality of weight bits” in lines 12-13. However, there is insufficient antecedent basis for this limitation in the claims. Claim 8 recites the limitation “a microprocessor coupled to the memory, wherein the microprocessor, in operation: copies a subset of the plurality of weight bits in the weight register a select plurality of number of times, wherein a size of the subset of weight bits is based on a filter index value; and selects a subset of the plurality of input bits from the source register based on the size of the subset of the plurality of weight bits; processes a copy of the subset of the plurality of weight bits, the processing comprising: performing …” in lines 8-16. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite (at least in part due to the “and” in claim 8, line 11, which is recited before “selects” in claim 8, line 12, rather than “processes” in claim 8, line 14) as to what entity of the recited system of claim 8, line 1, performs the recited processing. For the purposes of this office action, Examiner is taking the recited microprocessor to perform the recited processing. Claims 9-12 are rejected for failing to alleviate the rejections of claim 8 above. Claim 12 recites the limitation “the selected subset of input bits” in line 6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether this limitation is intended to have antecedent basis to the selected subset of input bits of the limitation “selects a subset of the plurality of input bits” in claim 8, line 12, or whether this limitation is intended to have antecedent basis in some manner to one or more instances of a selected “another subset of the plurality of input bits” in claim 8, line 25. For example, this limitation does not appear to have antecedent basis in view of the lack of “the plurality of” language. For the purposes of this office action, Examiner is interpreting this limitation as “the corresponding selected subset of the plurality of input bits”. Claim 19 recites the limitation “the selected subset of input bits” in line 6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether this limitation is intended to have antecedent basis to the selected subset of input bits of the limitation “selecting, using the source-register location, a subset of the plurality of input bits” in claim 15, line 12, or whether this limitation is intended to have antecedent basis in some manner to one or more instances of a selected “another subset of the plurality of input bits” in claim 15, line 25. For example, this limitation does not appear to have antecedent basis in view of the lack of “the plurality of” language. For the purposes of this office action, Examiner is interpreting this limitation as “the corresponding selected subset of the plurality of input bits”. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-5, 8-12, and 15-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. See MPEP 2106. Regarding Eligibility Step 1, each of the claims is directed to a process, machine, manufacture, or composition of matter. Regarding Eligibility Step 2A, Prong One, each of the claims recites abstract ideas, which is a judicial exception. Specifically, each of the claims recites mathematical concepts such as mathematical calculations and/or mental processes that can be performed in the human mind, or by a human using a pen and paper. For example, independent claim 1 recites “a weight length of the plurality of weight bits is equal to an input length of the plurality of input bits; copying a subset of the plurality of weight bits a select plurality of number of times, wherein a size of the subset of the plurality of weight bits is based on a filter index value; selecting a subset of the plurality of input bits based on the size of the subset of the plurality of weight bits; and processing a copy of the subset of the plurality of weight bits, the processing comprising: performing an XOR operation on each corresponding bit in the copy of the subset of the plurality of weight bits with each corresponding bit in the subset of the plurality of input bits; aggregating an output of each XOR operation with each other and with a current value; and determining whether another copy of the subset of the plurality of weight bits remains not processed, wherein if it is determined that the other copy of the subset of the plurality of weight bits remains not processed; selecting another subset of the plurality of input bits shifted one bit from the subset of the plurality of input bits, for processing the other copy of the subset of the plurality of weight bits.” Examiner notes that the aforementioned subject matter reflects a binary multiply-accumulate operation; see page 1, lines 7-8 of the original disclosure. Regarding the remaining recited limitations “receiving a destination-register location configured to store accumulation results, wherein the destination-register location includes a plurality of destination sub-locations”, “receiving a source-register location configured to store a plurality of input bits”, “receiving a weight-register location configured to store a plurality of weight bits”, “using the weight-register location” [to perform the aforementioned copying], using the source-register location [to perform the aforementioned selecting], [aggregating] “in a corresponding destination sub-location of the plurality of destination sub-locations”, and [a current value] “of the corresponding destination sub-location”, Examiner submits that these limitations merely reflect usage of register operands and registers to store input and output data, and submits that register operands and registers to store input and output data are generic computer components that are part of a generic computer and/or a computer environment. Examiner notes that performing a mental process on a generic computer, performing a mental process in a computer environment, and using a computer as a tool to perform a mental process is still an abstract idea. Regarding Eligibility Step 2A, Prong Two, the claim as a whole does not integrate the judicial exception into a practical application. In other words, the claim does not recite additional elements that integrate the judicial exception into a practical application. Regarding the remaining recited limitations “receiving a destination-register location configured to store accumulation results, wherein the destination-register location includes a plurality of destination sub-locations”, “receiving a source-register location configured to store a plurality of input bits”, “receiving a weight-register location configured to store a plurality of weight bits”, “using the weight-register location” [to perform the aforementioned copying], using the source-register location [to perform the aforementioned selecting], [aggregating] “in a corresponding destination sub-location of the plurality of destination sub-locations”, and [a current value] “of the corresponding destination sub-location”, Examiner submits that these elements are recited at a high level of generality and merely reflect usage of register operands and registers to store input and output data, and submits that register operands and registers to store input and output data are well-known generic computer components that are part of a generic computer and/or a computer environment. Examiner notes that merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, or generally linking the use of a judicial exception to a particular technological environment or field of use, does not integrate a judicial exception into a practical application. Examiner further submits that the aforementioned use of register operands and registers to store input and output data merely reflect insignificant extra-solution activities (e.g., data gathering and outputting). The aforementioned additional elements do not impose any meaningful limits on practicing the abstract idea. Therefore, the claim is directed to the judicial exception. Regarding Eligibility Step 2B, the claim does not recite additional elements that amount to an inventive concept. In other words, the claim does not recite additional elements that, individually or in combination, amount to significantly more than the judicial exception itself. Regarding the remaining recited limitations “receiving a destination-register location configured to store accumulation results, wherein the destination-register location includes a plurality of destination sub-locations”, “receiving a source-register location configured to store a plurality of input bits”, “receiving a weight-register location configured to store a plurality of weight bits”, “using the weight-register location” [to perform the aforementioned copying], using the source-register location [to perform the aforementioned selecting], [aggregating] “in a corresponding destination sub-location of the plurality of destination sub-locations”, and [a current value] “of the corresponding destination sub-location”, Examiner notes that merely adding the words "apply it" (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, or generally linking the use of a judicial exception to a particular technological environment or field of use, are not enough to qualify as "significantly more" when recited in a claim with a judicial exception. Examiner also notes that the courts have recognized receiving or transmitting data over a network, performing repetitive calculations, and storing and retrieving information in memory, as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. Dependent claims 2-5 do not add limitations that integrate the judicial exception into a practical application or amount to significantly more than the judicial exception recited in the independent claim. For example, claim 2 merely limits the filter index value to a particular range and explicitly recites receiving the filter index value (note that receiving input values was addressed above); as such, claim 2 does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Similarly, claim 3 merely limits the filter index value to a particular value and therefore does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Similarly, claim 4 merely limits the number of times to a particular number, and therefore does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claim 5 additionally recites “for each copy of the subset of the plurality of weight bits: performing a one's count operation on outputs from the XOR operations on each corresponding bit in the copy of the subset of the plurality of weight bits with each corresponding bit in the selected subset of input bits”; however, this limitation merely reflects further mathematical concepts such as mathematical calculations and/or mental processes that can be performed in the human mind, or by a human using a pen and paper, and, for the same reasons as addressed with respect to claim 1, does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself. Claims 8-12 and 15-19 are not patent eligible for analogous reasons as set forth above. Examiner notes that claim 8 further recites a memory and a microprocessor and claim 15 further recites a microcontroller; however, Examiner submits that a memory, microprocessor, and microcontroller are likewise well-known generic computer components that are part of a generic computer and/or a computer environment, and are not elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself Response to Arguments Applicant on page 8 argues: “Applicant has amended independent claims 1, 8, and 15 and canceled dependent claims 6, 13, and 20, to more clearly define the subject matter for which Applicant seeks protection”. All previously presented rejections of the claims under 35 U.S.C. §112(a) and various previously presented rejections of the claims under 35 U.S.C. §112(b) are withdrawn in view of the amendments to the claims. However, other previously presented rejections of the claims under 35 U.S.C. §112(b) remain applicable, and in various cases the amendments to the claims introduce additional issues under 35 U.S.C. §112(b) — see the Claim Rejections - 35 USC § 112 section above. Conclusion Examiner spoke to Applicant’s representative on November 10, 2025, and left voicemails on November 18, 2025, and December 2, 2025, regarding the possibility of an examiner-initiated interview; however, no examiner-initiated interview was held. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH E VICARY/ Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Jun 28, 2021
Application Filed
Sep 12, 2024
Non-Final Rejection — §101, §112
Nov 26, 2024
Interview Requested
Dec 09, 2024
Examiner Interview Summary
Dec 09, 2024
Applicant Interview (Telephonic)
Dec 12, 2024
Response Filed
Jan 02, 2025
Final Rejection — §101, §112
Feb 06, 2025
Interview Requested
Feb 24, 2025
Examiner Interview Summary
Feb 24, 2025
Applicant Interview (Telephonic)
Feb 28, 2025
Response after Non-Final Action
Mar 26, 2025
Request for Continued Examination
Mar 31, 2025
Response after Non-Final Action
May 05, 2025
Non-Final Rejection — §101, §112
Jun 18, 2025
Interview Requested
Jul 01, 2025
Applicant Interview (Telephonic)
Jul 01, 2025
Examiner Interview Summary
Jul 03, 2025
Response Filed
Jul 24, 2025
Final Rejection — §101, §112
Sep 11, 2025
Interview Requested
Sep 18, 2025
Applicant Interview (Telephonic)
Sep 18, 2025
Examiner Interview Summary
Sep 19, 2025
Response after Non-Final Action
Oct 09, 2025
Request for Continued Examination
Oct 16, 2025
Response after Non-Final Action
Dec 03, 2025
Non-Final Rejection — §101, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12602349
HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS
2y 5m to grant Granted Apr 14, 2026
Patent 12572360
Cache Preload Operations Using Streaming Engine
2y 5m to grant Granted Mar 10, 2026
Patent 12554507
SYSTEMS AND METHODS FOR PROCESSING FORMATTED DATA IN COMPUTATIONAL STORAGE
2y 5m to grant Granted Feb 17, 2026
Patent 12554494
APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE
2y 5m to grant Granted Feb 17, 2026
Patent 12547401
Load Instruction Fusion
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

5-6
Expected OA Rounds
58%
Grant Probability
99%
With Interview (+41.2%)
3y 8m
Median Time to Grant
High
PTA Risk
Based on 683 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month