Tech Center 2100 • Art Units: 2100 2182 2183 2199
This examiner grants 58% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18660925 | Multi-Instruction Packing In Single Instruction Slot | Final Rejection | Google LLC |
| 18550566 | System and Method for Power and Latency Reduction by Inserting Instruction Hints in Processing Thread Execution Code in a Multithreaded Architecture | Final Rejection | QUALCOMM Incorporated |
| 18661103 | APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION | Final Rejection | Intel Corporation |
| 18478882 | MEMORY SAFETY USING TAG CHECKING INSTRUCTIONS AND ISLANDS OF TAGS IN LINE WITH BUCKETED DATA | Non-Final OA | Intel Corporation |
| 17957969 | DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF PROCESSOR OPERATION BASED ON PAGE TABLE METADATA | Non-Final OA | Intel Corporation |
| 17712118 | SYNCHRONOUS MICROTHREADING | Non-Final OA | Intel Corporation |
| 17708933 | CONTROL REGISTER SET TO FACILITATE PROCESSOR EVENT BASED SAMPLING | Final Rejection | Intel Corporation |
| 17530040 | METHOD AND APPARATUS FOR MINIMALLY INTRUSIVE INSTRUCTION POINTER-AWARE PROCESSING RESOURCE ACTIVITY PROFILING | Non-Final OA | Intel Corporation |
| 17484840 | CIRCUITRY AND METHODS FOR ACCELERATING STREAMING DATA-TRANSFORMATION OPERATIONS | Non-Final OA | Intel Corporation |
| 17463390 | BFLOAT16 CLASSIFICATION AND MANIPULATION INSTRUCTIONS | Final Rejection | Intel Corporation |
| 18096115 | Sorting Method and Control for Partially Ordered Data Arrays in Embedded Systems | Non-Final OA | SK hynix Inc. |
| 19206182 | SECURING REGISTERS ACROSS SECURITY ZONES | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 19049097 | PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE RESULTS | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 19016487 | EXIT HISTORY BASED BRANCH PREDICTION | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 17876706 | STORING A RESULT OF A FIRST INSTRUCTION OF AM EXECUTE PACKET IN A HOLDING REGISTER PRIOR TO COMPLETION OF A SECOND INSTRUCTION OF THE EXECUTE PACKET | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 16422754 | VECTOR FLOATING-POINT SCALE | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18326202 | DEVICE AND METHOD OF DETECTING STRIDE ACCESS BASED ON PREDICTED ADDRESS FOR HARDWARE PREFETCH USED FOR CACHE MEMORY | Final Rejection | Fujitsu Limited |
| 18926133 | GATHER ACCELERATED ADDRESS SPACE | Final Rejection | NVIDIA Corporation |
| 18789957 | PROCESSING DATA USING ACCELERATORS IN A SYSTEM ON A CHIP | Non-Final OA | NVIDIA Corporation |
| 18733046 | EVENT TRACING | Non-Final OA | SiFive, Inc. |
| 18757922 | Instruction Deltas For Processing-In-Memory Divergence | Final Rejection | Advanced Micro Devices, Inc. |
| 18754873 | DISPATCH FOR A CONFIGURABLE DATA-FLOW COMPUTE ARRAY AND DATA-PARALLEL COMPUTE UNITS | Non-Final OA | ADVANCED MICRO DEVICES, INC. |
| 18619392 | WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS | Non-Final OA | Advanced Micro Devices, Inc. |
| 18390821 | ACCUMULATION APERTURES | Final Rejection | Advanced Micro Devices, Inc. |
| 18680032 | PHYSICAL REGISTER DEALLOCATION IN A PROCESSING SYSTEM | Non-Final OA | International Business Machines Corporation |
| 19203556 | BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES | Non-Final OA | Neslako Innovation Technology Limited |
| 18562398 | METHOD, MICROARCHITECTURE AND COMPUTING APPARATUS FOR ENCODING AND COMPUTATION ON DISTRIBUTIONS OF DATA REPRESENTING DISTRIBUTIONS THAT ARE UNCERTAINTY REPRESENTATIONS | Non-Final OA | CAMBRIDGE ENTERPRISE LIMITED |
| 18812889 | ENERGY-EFFICIENT INDIRECT PREFETCHER | Non-Final OA | Ampere Computing LLC |
| 18731006 | UNALIGNED LOAD AND STORE IN A CORE | Non-Final OA | XILINX, INC. |
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