DETAILED ACTION
This office action addresses Applicant’s response filed on 10 November 2025. Claims 1-5, 7-9, 11-22 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5, 7-9, 11-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 12, and 17 have been amended to recite, “wherein the first step size parameter and the second step size parameter are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions”, which is not supported by the originally-filed disclosure. Applicant points to ¶¶34-42 and 47-50 of the Specification as support for the latest-filed claim amendments. Whether in the cited portions or elsewhere, the Specification at best discloses performing higher-accuracy extraction in critical regions, and lower-accuracy extraction elsewhere, the higher-accuracy extraction using a smaller step size than the lower-accuracy extraction. The Specification does not disclose any actual process for automatically determining what the step size parameters are, let alone performing said determination based on the respective criticalities of the regions. See MPEP § 2161.01(I): “When examining computer-implemented functional claims, examiners should determine whether the specification discloses the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. It is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement” (emphasis added).
Notably, Applicant has introduced these limitations because Applicant believes that the combination of cited prior art references fail to teach them. Remarks 13. The claims already recites first and second capacitance extractions on critical and non-critical regions using larger and smaller step sizes, respectively. Thus, Applicant appears to interpret “wherein … step size parameter[s] are automatically determined based on respective criticalities” to mean something beyond simply using a smaller step size in critical regions than in other regions, which is already covered by other limitations, and also disclosed by the cited art. However, while the Specification discloses the use of smaller step sizes in critical regions and larger step sizes in other regions, the Specification does not explain how to actually calculate the smaller or larger step sizes, or how the respective criticalities of regions are factored into the calculation. In short, Applicant has not demonstrated possession of any interaction between step size and region criticality except the general idea that critical regions use smaller step sizes than other regions, and is not entitled to claim subject matter beyond that.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 7, 8, 17-19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuh (US 2014/0019930) in view of Yu (“Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors”), Garcia (“Monte Carlo Fixed-Radius Floating Random Walk Solution for Potential Problems”), Szekely (“SUNRED, a new field solving approach”), Shang (US 2007/0244676), Su (8,984,468), Yu-Tseng (US 2013/0320555), Dewey (US 2017/0177776), Fu (US 2015/0234964), Bishop (US 2017/0256466), and Chapman (US 2009/0307640).
Regarding claim 1, Yuh discloses a method for capacitance extraction, comprising:
performing, using a three-dimensional (3D) capacitance determination process, a first capacitance extraction on one or more first regions comprising critical circuit areas that comprise one or more functional circuits of a semiconductor layout (Figs. 2 and 3; ¶¶12, 23, 36, 38, 56), the performing the first capacitance extraction including:
calculating a first capacitance parameter associated with first portions within the same first region (¶12);
performing a second capacitance extraction on one or more second regions comprising non-critical areas that comprise a plurality of signal pads of the semiconductor layout (¶¶12, 23, 26, 30, 36, 56), the performing the second capacitance extraction including:
calculating a second capacitance parameter associated with second portions within the same second region and additional second capacitance parameters each associated with one of the first portions of the first region and one of the portions of the second region (Fig. 4B, C5; ¶¶12, 43, 44);
constructing a netlist for the semiconductor layout based on results of the first capacitance extraction and of the second capacitance extraction (¶¶19, 46); and
modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used to fabricate an integrated circuit (¶¶13, 20, 22),
wherein the one or more first regions are identified partially by user-defined settings and partially automatically by a design system (¶37);
wherein the accuracy of the first and second capacitance extractions are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions (¶¶23, 26, 36).
Yuh does not appear to explicitly disclose that the first capacitance extraction is performed with a first resolution and based on a first step size parameter selected for a random walk method of capacitance extraction, that the second capacitance extraction is performed using the same 3D capacitance determination process with a second resolution lower than the first resolution, based on a second step size parameter larger than the first step size parameter selected for the random walk method, and that the step sizes are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions. However, these limitations are merely an obvious variant of Yuh. As discussed above, Yuh discloses that the first capacitance extraction uses any higher-accuracy technique, and the second capacitance extraction uses any lower-accuracy technique (¶23). It is known that extracting capacitance parameters use a random walk method, as taught by Yu (p. 22, par. 1), and step sizes for the random walk are set based on desired tradeoff between accuracy and speed, as taught by Garcia (p. 89, item 1). In particular, larger steps sizes improve speed and reduce accuracy, and those step sizes are automatically determined based on how accuracy-critical the evaluation region is, as taught by Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45).
Since Yuh discloses performing a higher-accuracy capacitance calculation on critical regions, and a lower-accuracy capacitance calculation on other regions, the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggests performing a higher-accuracy capacitance calculation on accuracy-critical regions by a random walk using one step size for higher accuracy, and performing a lower-accuracy capacitance calculation on other regions by random walk using another step size for lower accuracy, based on the criticalities of the regions. Specifically, Yuh already discloses capacitance extraction using a field solver with higher accuracy in critical regions and lower accuracy in other regions. Field solvers using random walk methods are known (Yu), and it is also known that smaller step size results in higher accuracy and should be used in critical regions, while larger step size results in lower accuracy and should be used in other regions (Garcia, Szekely, Shang, and Su). So the prior art combination clearly suggests using a known random walk field solver with smaller step size as Yuh’s high-accuracy solver in critical regions, and with a larger step size as Yuh’s lower-accuracy solver in other regions.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, and Su, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine substitution of one element for a known equivalent, to produce merely the predictable results of extracting capacitance efficiently using known random walk techniques with higher and lower accuracy as necessary. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Yuh discloses capacitance extraction using higher accuracy on critical regions and lower accuracy on other regions. Yu teaches that capacitance extraction is performed by random walk, and Garcia teaches that the chosen step size for the random walk is based on the accuracy, where larger steps sizes have lower accuracy, as taught by Szekely, Shang, and Su. The teachings of Yu, Garcia, Szekely, Shang, and Su are directly applicable to Yuh in the same way, so that Yuh would similarly perform higher- and lower-accuracy capacitance extraction using the known random walk technique, using smaller step size to achieve higher accuracy and larger step size for lower accuracy but better speed.
Yuh does not appear to explicitly disclose calculating a total capacitance value associated with a first structure and a second structure of the semiconductor layout, respective ones of the first portions of the first and second structures within the first region and respective ones of the second portions of the first and second structures within the second region, the calculating the total capacitance value including calculating a sum of the calculated capacitance parameter associated with the respective first portions of the first structure and the second structure, the calculated second capacitance parameter associated with the respective second portions of the first and second structures, and the calculated additional capacitance parameters. However, these limitations are strongly implied, if not inherent, in Yuh. Yuh discloses that when calculating capacitance between shapes that are not completely within the first region, the shapes that are not completely within the first region are decomposed into segments within the first region and segments that are not (Fig. 4B, shape 231 decomposed into 441 within region 301, and 442 outside of the region; ¶50), and then capacitances are calculated between the segments, where one technique is used if the segments are within the first region (Fig. 4B, C4 between 441 and 226’ in the first region; ¶¶38, 50), and another technique is used if a segment is not within the first region (Fig. 4B, C5 between 442 not in the first region and 226’; ¶43).
Yuh’s capacitance calculation technique thus determines a plurality of capacitance associated with different portions of first and second structures, wherein one of the capacitances (when the segments are within the first region) is calculated one way, and the remaining ones of the plurality of capacitances (when a segment is not within the first region) is calculated a different way. As discussed above, the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su teaches using the first step size parameter for capacitance calculation within the first region, and the second step size parameter for capacitance calculation outside of the first region; so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su teaches that one of the plurality of capacitance is calculated based on the first step size parameter and the remaining ones of the plurality of capacitance are calculated based on the second step size parameter.
Furthermore, while the specific example illustrated in Fig. 4B of Yuh involves a structure that is fully within the first region, persons having ordinary skill in the art would recognize that Yuh’s technique is not limited to being applied to only the illustrated case, but is readily applicable to many different structures found in circuit designs. For example, if Yuh’s technique was used to calculate capacitance between two structures like 231 in Fig. 4B, each structure would have a portion within region 301, and a portion outside of region 301, and capacitance would be calculated in one way between portions inside region 301, and another way if a portion is outside region 301. Similarly, calculating the capacitance between 231 and 331 of Fig. 3B, which both have portions inside and outside of the region 301, would use one calculation method for the portions inside of region 301, and another calculation method for portions outside of the region. Many other such arrangements of structures are known in the art, for example as seen in Yu-Tseng (Figs. 8G, 10A/B, 11A/B); applying Yuh’s technique as illustrated in Fig. 4B to structures similar to Yu-Tseng’s Fig. 8G, for instance, would result in both structures being decomposed into a portion within the first region and a portion outside the first region, like Yuh’s 231, with the capacitance between the portions within the first region calculated with the first step size, and the capacitance between portions outside the first region calculated with the second step size in the manner discussed above.
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, and Yu-Tseng, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of obeying designated accuracy-speed tradeoffs in capacitance extraction on varying structures that are partially within specified high-accuracy regions. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Yuh discloses a capacitance extraction technique in which a region is specified and structures within the region are treated using a first extraction method and structures outside of the region are treated using a second extraction method, where structures partially within the region are first decomposed into a portion that is within the region and a portion that is outside of the region. Yu, Garcia, Szekely, Shang, and Su teach that the first extraction method uses a first step size and the second extraction method uses a second step size, as discussed above. Yu-Tseng provides examples of various structures for which capacitance is extracted, similar to the structures in Yuh. The example structures in Yu-Tseng are directly applicable to the techniques of Yuh, Yu, Garcia, Szekely, Shang, and Su in the same way, so that capacitance extraction using first or second step sizes could similarly be applied to various structures known in the art to correctly obey trade-offs between accuracy and speed for those structures.
Furthermore, persons having ordinary skill in the art would know that the capacitance for structures that have been decomposed into segments is simply the sum of the capacitances for the segments, as taught by Dewey (¶54). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, and Dewey, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of speeding up capacitance calculation with segmented structures. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Yuh discloses capacitance calculation for segments of a structure. Dewey teaches that capacitance calculation for a structure can be sped up by calculating capacitances for segments of the structure and then adding up the segment capacitances. The teachings of Dewey are directly applicable to Yuh in the same way, so that Yuh’s segment capacitance calculations would similarly be used to speed up calculation of the structure.
Yuh does not appear to explicitly disclose recording coordinates identifying the one or more first regions in a header of the netlist. However, Yuh discloses defining coordinates identifying the one or more first regions (¶34) in a design, and the netlist (¶¶14, 19), and persons having ordinary skill in the art would recognize that netlists include region definitions, as taught by Fu (¶32) and Bishop (¶84). Persons having ordinary skill in the art would further recognize that region definitions would be stored in headers, which are typically used to include additional design information, such as region definitions, as taught by Chapman (¶¶151, 583). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, and Chapman, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way, or choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success, to achieve the predictable results of providing extraction information together with design netlists. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Yuh discloses a capacitance extraction process that defines coordinates of regions to perform an extraction technique on a design, and a netlist specifying the design information. Persons having ordinary skill in the art would recognize that design information such as Yuh’s defined regions would be included in the netlist, which typically specifies region information as taught by Fu and Bishop. Persons having ordinary skill in the art would further recognize that the region information would be stored in a header of the netlist, because headers are typically used for such additional information, as taught by Chapman. The teachings of Fu, Bishop, and Chapman are directly applicable to Yuh in the same way, so that Yuh’s netlist would similarly store Yuh’s defined region coordinates in a header, in accordance with typical practice/knowledge, so that the region information could be provided with the other design information specified in the netlist.
Regarding claims 2 and 18, Yuh discloses that the performing the first capacitance extraction comprises: applying the three-dimensional (3D) capacitance determination process to generate the netlist to include one or more of the first capacitance parameters associated with the one or more first regions (¶¶31, 38, 46). Yuh does not appear to explicitly disclose the first step size parameter, but as discussed above with regard to claim 1, this limitation is taught by Garcia (p. 89, item 1). Motivation to combine remains consistent with claim 1.
Regarding claims 4 and 19, Yuh discloses that performing the second capacitance extraction comprises: applying the capacitance determination process to generate the netlist to include one or more of the second capacitance parameters associated with the one or more second regions (¶¶12, 38, 46). Yuh does not appear to explicitly disclose the capacitance determination process is the 3D extraction applied based on the second step size parameter, but as discussed above with regard to claim 1, Yuh teaches 3D capacitance extraction (¶31), and capacitance extraction having different accuracy (¶¶12, 23), Yu teaches capacitance extraction using random walks (p. 22, par. 1), Garcia discloses that the step size for random walks is based on accuracy (p. 89, item 1), and Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45) that larger step sizes have lower accuracy, and so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggest higher- and lower-accuracy 3D capacitance extractions using larger and smaller step sizes. Motivation to combine remains consistent with claim 1.
Regarding claim 5, Yuh discloses identifying an area comprising the one or more functional circuits in the semiconductor layout as the one or more first region (¶56).
Regarding claim 7, Yuh discloses that the calculating the first capacitance parameter further comprises calculating a first capacitance parameter associated with the first portion of the first structure and the first portion of the second structure, the first portion of the first structure and the first portion of the second structure being within the one or more first regions; and that calculating the second capacitance parameter further comprises calculating a second capacitance parameter associated with a second portion of the first structure and a second portion of the second structure, the second portion of the first structure and the second portion of the second structure being within the one or more second regions (¶¶12, 33-36; Figs. 3A-3C). Yuh does not appear to explicitly disclose the first and second step size parameters, but as discussed above, Yuh teaches capacitance extraction having different accuracy (¶¶12, 23), Yu teaches capacitance extraction using random walks (p. 22, par. 1), Garcia discloses that the step size for random walks is based on accuracy (p. 89, item 1), and Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45) that larger step sizes have lower accuracy, and so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggest higher- and lower-accuracy capacitance extractions using larger and smaller step sizes. Motivation to combine remains consistent with claim 1.
Regarding claim 8, Yuh discloses calculating, included in the additional capacitance parameters, a third capacitance parameter associated with the first portion of the first structure and the second portion of the second structure; calculating, included in the additional capacitance parameters, a fourth capacitance parameter associated with the second portion of the first structure and the first portion of the second structure; and calculating the total capacitance value associated with the first structure and the second structure to include the sum of the first capacitance parameter, the second capacitance parameter, the third capacitance parameter, and the fourth capacitance parameter (¶¶43, 45, 48), in the manner discussed above with regard to claim 1. Furthermore, as discussed above, persons having ordinary skill in the art would know that the capacitance for structures that have been decomposed into segments is simply the sum of the capacitances for the segments, as taught by Dewey (¶54). Motivation to combine remains consistent with claim 1.
Yuh does not appear to explicitly disclose the second step size parameter, but as discussed above, Yuh teaches capacitance extraction having different accuracy (¶¶12, 23), Yu teaches capacitance extraction using random walks (p. 22, par. 1), and Garcia discloses that the step size for random walks is based on accuracy (p. 89, item 1), so the combination of Yuh, Yu, and Garcia suggest higher- and lower-accuracy capacitance extractions using different step sizes. Motivation to combine remains consistent with claim 1.
Regarding claim 17, Yuh discloses a non-transitory computer-readable storage medium storing a set of instructions that are executable by one or more processors of a device to cause the device to perform a method (¶75), the method comprising:
performing a first capacitance extraction using a three-dimensional (3D) capacitance determination process, on one or more first regions comprising critical circuit areas that comprise one or more functional circuits of a semiconductor layout (Figs. 2 and 3; ¶¶12, 23, 36, 38, 56), the performing the first capacitance extraction including:
calculating a first capacitance parameter associated with first portions within the same first region (¶12);
performing a second capacitance extraction on one or more second regions comprising non-critical areas that comprise a plurality of signal pads outside of the one or more first regions (¶¶12, 23, 26, 30, 36, 47, 56), the performing the second capacitance extraction including:
calculating a second capacitance parameter associated with second portions within the same second region and additional second capacitance parameters each associated with one of the first portions of the first region and one of the portions of the second region (Fig. 4B, C5; ¶¶12, 43, 44);
constructing a netlist for the semiconductor layout based on results of the first capacitance extraction and of the second capacitance extraction (¶¶19, 46); and
modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used to fabricate an integrated circuit (¶¶13, 20, 22),
wherein the one or more first regions are identified partially by user-defined settings and partially automatically by a design system (¶37);
wherein the accuracy of the first and second capacitance extractions are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions (¶¶23, 26, 36).
Yuh does not appear to explicitly disclose that the first capacitance extraction is performed with a first resolution and based on a first step size parameter selected for a random walk method of capacitance extraction, that the second capacitance extraction is performed using the same 3D capacitance determination process with a second resolution lower than the first resolution, based on a second step size parameter larger than the first step size parameter selected for the random walk method, and that the step sizes are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions. However, these limitations are merely an obvious variant of Yuh. As discussed above, Yuh discloses that the first capacitance extraction uses any higher-accuracy technique, and the second capacitance extraction uses any lower-accuracy technique (¶23). It is known that extracting capacitance parameters use a random walk method, as taught by Yu (p. 22, par. 1), and step sizes for the random walk are set based on desired tradeoff between accuracy and speed, as taught by Garcia (p. 89, item 1). In particular, larger steps sizes improve speed and reduce accuracy, and those step sizes are automatically determined based on how accuracy-critical the evaluation region is, as taught by Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45).
Since Yuh discloses performing a higher-accuracy capacitance calculation on critical regions, and a lower-accuracy capacitance calculation on other regions, the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggests performing a higher-accuracy capacitance calculation on accuracy-critical regions by a random walk using one step size for higher accuracy, and performing a lower-accuracy capacitance calculation on other regions by random walk using another step size for lower accuracy, based on the criticalities of the regions. Specifically, Yuh already discloses capacitance extraction using a field solver with higher accuracy in critical regions and lower accuracy in other regions. Field solvers using random walk methods are known (Yu), and it is also known that smaller step size results in higher accuracy and should be used in critical regions, while larger step size results in lower accuracy and should be used in other regions (Garcia, Szekely, Shang, and Su). So the prior art combination clearly suggests using a known random walk field solver with smaller step size as Yuh’s high-accuracy solver in critical regions, and with a larger step size as Yuh’s lower-accuracy solver in other regions. Motivation to combine remains consistent with claim 1.
Yuh does not appear to explicitly disclose calculating a total capacitance value associated with a first structure and a second structure of the semiconductor layout, respective ones of the first portions of the first and second structures within the first region and respective ones of the second portions of the first and second structures within the second region, the calculating the total capacitance value including calculating a sum of the calculated capacitance parameter associated with the respective first portions of the first structure and the second structure, the calculated second capacitance parameter associated with the respective second portions of the first and second structures, and the calculated additional capacitance parameters. However, these limitations are strongly implied, if not inherent, in Yuh. Yuh discloses that when calculating capacitance between shapes that are not completely within the first region, the shapes that are not completely within the first region are decomposed into segments within the first region and segments that are not (Fig. 4B, shape 231 decomposed into 441 within region 301, and 442 outside of the region; ¶50), and then capacitances are calculated between the segments, where one technique is used if the segments are within the first region (Fig. 4B, C4 between 441 and 226’ in the first region; ¶¶38, 50), and another technique is used if a segment is not within the first region (Fig. 4B, C5 between 442 not in the first region and 226’; ¶43).
Yuh’s capacitance calculation technique thus determines a plurality of capacitance associated with different portions of first and second structures, wherein one of the capacitances (when the segments are within the first region) is calculated one way, and the remaining ones of the plurality of capacitances (when a segment is not within the first region) is calculated a different way. As discussed above, the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su teaches using the first step size parameter for capacitance calculation within the first region, and the second step size parameter for capacitance calculation outside of the first region; so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su teaches that one of the plurality of capacitance is calculated based on the first step size parameter and the remaining ones of the plurality of capacitance are calculated based on the second step size parameter.
Furthermore, while the specific example illustrated in Fig. 4B of Yuh involves a structure that is fully within the first region, persons having ordinary skill in the art would recognize that Yuh’s technique is not limited to being applied to only the illustrated case, but is readily applicable to many different structures found in circuit designs. For example, if Yuh’s technique was used to calculate capacitance between two structures like 231 in Fig. 4B, each structure would have a portion within region 301, and a portion outside of region 301, and capacitance would be calculated in one way between portions inside region 301, and another way if a portion is outside region 301. Similarly, calculating the capacitance between 231 and 331 of Fig. 3B, which both have portions inside and outside of the region 301, would use one calculation method for the portions inside of region 301, and another calculation method for portions outside of the region. Many other such arrangements of structures are known in the art, for example as seen in Yu-Tseng (Figs. 8G, 10A/B, 11A/B); applying Yuh’s technique as illustrated in Fig. 4B to structures similar to Yu-Tseng’s Fig. 8G, for instance, would result in both structures being decomposed into a portion within the first region and a portion outside the first region, like Yuh’s 231, with the capacitance between the portions within the first region calculated with the first step size, and the capacitance between portions outside the first region calculated with the second step size in the manner discussed above. Motivation to combine remains consistent with claim 1.
Furthermore, persons having ordinary skill in the art would know that the capacitance for structures that have been decomposed into segments is simply the sum of the capacitances for the segments, as taught by Dewey (¶54). Motivation to combine remains consistent with claim 1.
Yuh does not appear to explicitly disclose recording coordinates identifying the one or more first regions in a header of the netlist. However, Yuh discloses defining coordinates identifying the one or more first regions (¶34) in a design, and the netlist (¶¶14, 19), and persons having ordinary skill in the art would recognize that netlists include region definitions, as taught by Fu (¶32) and Bishop (¶84). Persons having ordinary skill in the art would further recognize that region definitions would be stored in headers, which are typically used to include additional design information, such as region definitions, as taught by Chapman (¶¶151, 583). Motivation to combine remains consistent with claim 1.
Regarding claim 21, Yuh discloses that performing the second capacitance extraction further comprises: applying the capacitance determination process to generate the netlist to include one or more of the second capacitance parameters associated with the one or more second regions (¶12, 38, 61), but does not appear to explicitly disclose the three-dimensional capacitance determination process based on the second step size parameter being greater than the first step size parameter. However, as discussed above, Yuh discloses a capacitance determination process using different accuracy for different regions, Yu discloses a 3D random walk process for capacitance determination (p. 32, section 5, par. 1), Garcia discloses that the step size parameter for random walk is based on accuracy (p. 89, item 1), and Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and Su (col. 2, lines 37-45) that larger step sizes have lower accuracy. The combination of Yuh, Yu, Garcia, Szekely, Shang, and Su thus suggests capacitance determination using 3D random walk with different accuracies for different regions using larger and smaller step sizes. Motivation to combine remains consistent with claim 1.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuh in view of Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and Ramakrishnan (US 10,235,482).
Regarding claim 3, Yuh discloses that the netlist comprises a first netlist and a second netlist, the first netlist including one or more of the first capacitance parameters associated with the one or more regions, and the second netlist including one or more of the second capacitance parameters associated with the one or more second regions (¶46). If Yuh is found to be unclear regarding the netlist comprising first and second netlists, Ramakrishnan discloses the same (col. 10, lines 27-31). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, and Chapman, and Ramakrishnan, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of generating netlists include region sub-netlists. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Yuh discloses performing capacitance extraction on different regions and including the results in a netlist. Persons having ordinary skill in the art would recognize that such a netlist would have sub-netlists corresponding to the regions, as taught by Ramakrishnan. The teachings of Ramakrishnan are directly applicable to Yuh in the same way, so that Yuh would similarly include extraction results for each region in a netlist having sub-netlists for the regions.
Claim(s) 9 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuh in view of Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and McConaghy (US 2003/0131323).
Regarding claims 9 and 22, Yuh discloses corresponding accuracy parameters associated with a plurality of capacitance components in the semiconductor layout (¶¶12, 30), but does not appear to explicitly disclose recording those parameters in the netlist. However, recording parameters in a netlist is well-known; for example, McConaghy discloses that the netlist includes parameters, schematic, and layout information (¶34). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and McConaghy, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of recording accuracy parameters in a netlist. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Yuh discloses accuracy parameters for RC extraction to generate netlists. McConaghy discloses that netlists include various parameters. The teachings of McConaghy are directly applicable to Yuh in the same way, so that Yuh’s accuracy parameters would similarly be included in the netlist.
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuh in view of Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and Bachtold (“A System for Full-Chip and Critical Net Parasitic Extraction for ULSI Interconnects using a Fast 3-D Field Solver”).
Regarding claim 11 and 20, Yuh discloses the three-dimensional (3D) capacitance determination process (¶31), but does not appear to explicitly disclose determining an accuracy configuration associated with a signal of the semiconductor layout; and applying the three-dimensional (3D) capacitance determination process based on the accuracy configuration to calculate a capacitance value between at least two components associated with the signal. Bachtold discloses these limitations (p. 328, col. 1, par. 1; Figs. 4-6). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and Bachtold, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using higher-accuracy capacitance extraction on critical signals. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Yuh discloses higher- and lower-accuracy capacitance extraction for different regions. Bachtold teaches that higher-accuracy extraction should be used on critical signals. The teachings of Bachtold are directly applicable to Yuh in the same way, so that Yuh’s higher-accuracy capacitance extraction would similarly be performed for critical signals.
Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuh in view of Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and Yu (US 6,829,754, hereinafter “Ratchkov”).
Regarding claim 12, Yuh discloses a system, comprising: a processing unit; and one or more memory units storing instructions for one or more programs executable by the processing unit to perform operations (Fig. 7; ¶70) comprising:
receiving a semiconductor layout that comprises a plurality of signal pads and a mesh network including one or more functional circuits (Figs. 1-3; ¶¶19, 26);
identifying a plurality of regions within the semiconductor layout, the plurality of regions including one or more first regions comprising critical circuit areas and one or more second regions comprising non-critical areas (¶¶12, 33-36), wherein the plurality of regions are identified partially by user-defined settings and partially automatically by the system (¶37);
performing capacitance extractions, using a three-dimensional (3D0 capacitance determination process (¶38), the performing the capacitance extractions including: calculating a first capacitance parameter associated with first portions within the same first region and calculating a second capacitance parameter associated with second portions within the same second region (¶12) and additional second capacitance parameters each associated with one of the first portions of the first region and one of the portions of the second region (Fig. 4B, C5; ¶¶12, 43, 44);
constructing a netlist for the semiconductor layout based on results of the capacitance extractions (¶19); and
modifying the semiconductor layout based on the netlist, the modified semiconductor layout being used to fabricate an integrated circuit (¶¶13, 20, 22).
Yuh does not appear to explicitly disclose performing capacitance extractions with a first resolution a second resolution lower than the first resolution, that calculating the first capacitance parameter is based on a first step size parameter selected for a random walk method of capacitance extraction, and that calculating the second capacitance parameter is based on a second step size parameter larger than the first step size parameter selected for the random walk method, the larger second step size providing the lower second resolution, and that the step sizes are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions. However, these limitations are merely an obvious variant of Yuh. As discussed above, Yuh discloses that the first capacitance extraction uses any higher-accuracy technique, and the second capacitance extraction uses any lower-accuracy technique (¶23). It is known that extracting capacitance parameters use a random walk method, as taught by Yu (p. 22, par. 1), and step sizes for the random walk are set based on desired tradeoff between accuracy and speed, as taught by Garcia (p. 89, item 1). In particular, larger steps sizes improve speed and reduce accuracy, and those step sizes are automatically determined based on how accuracy-critical the evaluation region is, as taught by Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45).
Since Yuh discloses performing a higher-accuracy capacitance calculation on critical regions, and a lower-accuracy capacitance calculation on other regions, the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggests performing a higher-accuracy capacitance calculation on accuracy-critical regions by a random walk using one step size for higher accuracy, and performing a lower-accuracy capacitance calculation on other regions by random walk using another step size for lower accuracy, based on the criticalities of the regions. Specifically, Yuh already discloses capacitance extraction using a field solver with higher accuracy in critical regions and lower accuracy in other regions. Field solvers using random walk methods are known (Yu), and it is also known that smaller step size results in higher accuracy and should be used in critical regions, while larger step size results in lower accuracy and should be used in other regions (Garcia, Szekely, Shang, and Su). So the prior art combination clearly suggests using a known random walk field solver with smaller step size as Yuh’s high-accuracy solver in critical regions, and with a larger step size as Yuh’s lower-accuracy solver in other regions. Motivation to combine remains consistent with claim 1.
Yuh does not appear to explicitly disclose calculating a total capacitance value associated with a first structure and a second structure of the semiconductor layout, respective ones of the first portions of the first and second structures within the first region and respective ones of the second portions of the first and second structures within the second region, the calculating the total capacitance value including calculating a sum of the calculated capacitance parameter associated with the respective first portions of the first structure and the second structure, the calculated second capacitance parameter associated with the respective second portions of the first and second structures, and the calculated additional capacitance parameters. However, these limitations are strongly implied, if not inherent, in Yuh. Yuh discloses that when calculating capacitance between shapes that are not completely within the first region, the shapes that are not completely within the first region are decomposed into segments within the first region and segments that are not (Fig. 4B, shape 231 decomposed into 441 within region 301, and 442 outside of the region; ¶50), and then capacitances are calculated between the segments, where one technique is used if the segments are within the first region (Fig. 4B, C4 between 441 and 226’ in the first region; ¶¶38, 50), and another technique is used if a segment is not within the first region (Fig. 4B, C5 between 442 not in the first region and 226’; ¶43).
Yuh’s capacitance calculation technique thus determines a plurality of capacitance associated with different portions of first and second structures, wherein one of the capacitances (when the segments are within the first region) is calculated one way, and the remaining ones of the plurality of capacitances (when a segment is not within the first region) is calculated a different way. As discussed above, the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su teaches using the first step size parameter for capacitance calculation within the first region, and the second step size parameter for capacitance calculation outside of the first region; so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su teaches that one of the plurality of capacitance is calculated based on the first step size parameter and the remaining ones of the plurality of capacitance are calculated based on the second step size parameter.
Furthermore, while the specific example illustrated in Fig. 4B of Yuh involves a structure that is fully within the first region, persons having ordinary skill in the art would recognize that Yuh’s technique is not limited to being applied to only the illustrated case, but is readily applicable to many different structures found in circuit designs. For example, if Yuh’s technique was used to calculate capacitance between two structures like 231 in Fig. 4B, each structure would have a portion within region 301, and a portion outside of region 301, and capacitance would be calculated in one way between portions inside region 301, and another way if a portion is outside region 301. Similarly, calculating the capacitance between 231 and 331 of Fig. 3B, which both have portions inside and outside of the region 301, would use one calculation method for the portions inside of region 301, and another calculation method for portions outside of the region. Many other such arrangements of structures are known in the art, for example as seen in Yu-Tseng (Figs. 8G, 10A/B, 11A/B); applying Yuh’s technique as illustrated in Fig. 4B to structures similar to Yu-Tseng’s Fig. 8G, for instance, would result in both structures being decomposed into a portion within the first region and a portion outside the first region, like Yuh’s 231, with the capacitance between the portions within the first region calculated with the first step size, and the capacitance between portions outside the first region calculated with the second step size in the manner discussed above. Motivation to combine remains consistent with claim 1.
Furthermore, persons having ordinary skill in the art would know that the capacitance for structures that have been decomposed into segments is simply the sum of the capacitances for the segments, as taught by Dewey (¶54). Motivation to combine remains consistent with claim 1.
Yuh does not appear to explicitly disclose recording coordinates identifying the one or more first regions in a header of the netlist. However, Yuh discloses defining coordinates identifying the one or more first regions (¶34) in a design, and the netlist (¶¶14, 19), and persons having ordinary skill in the art would recognize that netlists include region definitions, as taught by Fu (¶32) and Bishop (¶84). Persons having ordinary skill in the art would further recognize that region definitions would be stored in headers, which are typically used to include additional design information, such as region definitions, as taught by Chapman (¶¶151, 583). Motivation to combine remains consistent with claim 1.
If Yuh is found to be unclear regarding the mesh network, Ratchkov discloses the same (Fig. 2). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, and Ratchkov, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of analyzing electrical properties of conventional circuits having mesh networks for delivering signals to circuit elements. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Yuh discloses electrical analysis of circuits including functional circuit elements (e.g. transistors), signal pads, and a conductor network that carry signals to the circuit elements. Persons having ordinary skill in the art, reading Yuh, would understand that Yuh’s circuits having the functional circuit elements connected by conductor networks constitute mesh networks, as taught by Ratchkov. The teachings of Ratchkov are directly applicable to Yuh to perform Yuh’s electrical analysis on conventional circuits having mesh networks of functional circuit elements interconnected by conductors.
Regarding claim 13, Yuh discloses that the performing the first capacitance extraction comprises: applying the three-dimensional (3D) capacitance determination process to generate the netlist to include one or more of the first capacitance parameters associated with the one or more first regions (¶¶31, 38, 46). Yuh does not appear to explicitly disclose the first step size parameter, but as discussed above with regard to claim 1, this limitation is taught by Garcia (p. 89, item 1). Motivation to combine remains consistent with claims 1 and 12.
Regarding claim 14, Yuh discloses applying the capacitance determination process to generate the netlist to include one or more of the second capacitance parameters associated with the one or more regions different from the one or more first regions (¶¶12, 38, 46). Yuh does not appear to explicitly disclose the 3D process applied with the second step size parameter greater than the first step size parameter, but as discussed above with regard to claim 1, Yuh teaches 3D capacitance extraction (¶31), and capacitance extraction having different accuracy (¶¶12, 23), Yu teaches capacitance extraction using random walks (p. 22, par. 1), Garcia discloses that the step size for random walks is based on accuracy (p. 89, item 1), and Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45) that larger step sizes have lower accuracy, and so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggest higher- and lower-accuracy 3D capacitance extractions using larger and smaller step sizes. Motivation to combine remains consistent with claims 1 and 12.
Regarding claim 15, Yuh discloses applying a 3D field solver to perform the three-dimensional capacitance determination process to calculate the capacitance value between at least two components (¶¶12, 30, 38, 61), but does not appear to explicitly disclose that the 3D process is performed on components within the one or more second regions different from the one or more first regions. However, as discussed above with regard to claim 1, Yuh teaches capacitance extraction having different accuracy (¶¶12, 23), Yu teaches capacitance extraction using random walks (p. 22, par. 1), Garcia discloses that the step size for random walks is based on accuracy (p. 89, item 1), and Szekely (p. 278, last paragraph; p. 284, first paragraph), Shang (¶124), and/or Su (col. 2, lines 37-45) that larger step sizes have lower accuracy, and so the combination of Yuh, Yu, Garcia, Szekely, Shang, and Su suggest higher- and lower-accuracy 3D capacitance extractions using larger and smaller step sizes. Motivation to combine remains consistent with claim 1 and 12.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuh in view of Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, Ratchkov, and Bachtold.
Regarding claim 16, Yuh discloses the three-dimensional (3D) capacitance determination process (¶31), but does not appear to explicitly disclose determining an accuracy configuration associated with a signal of the semiconductor layout; and applying the three-dimensional (3D) capacitance determination process based on the accuracy configuration to calculate a capacitance value between at least two components associated with the signal. Bachtold discloses these limitations (p. 328, col. 1, par. 1; Figs. 4-6). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Yuh, Yu, Garcia, Szekely, Shang, Su, Yu-Tseng, Dewey, Fu, Bishop, Chapman, Ratchkov, and Bachtold, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using higher-accuracy capacitance extraction on critical signals. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Yuh discloses higher- and lower-accuracy capacitance extraction for different regions. Bachtold teaches that higher-accuracy extraction should be used on critical signals. The teachings of Bachtold are directly applicable to Yuh in the same way, so that Yuh’s higher-accuracy capacitance extraction would similarly be performed for critical signals.
Response to Arguments
Applicant's arguments filed 10 November 2025 have been fully considered but they are not persuasive.
Applicant asserts that the prior art fails to teach the new limitation of “the first step size parameter and the second step size parameter are automatically determined based on respective criticalities of the one or more first regions and the one or more second regions”. Remarks 13. These limitations have been addressed above in the new grounds of rejection. Applicant further asserts that Szekely does not mention step size. Remarks 14. The examiner disagrees. Szekely discloses the accuracy vs speed tradeoff of resolution, and in particular using denser resolutions where detailed computation is required. Considered with Garcia, which discloses determining step size based on speed and accuracy, Szekely clearly teaches smaller step sizes (denser resolutions) for higher accuracy but more compute time.
Applicant asserts that persons having ordinary skill in the art would not have modified Yuh in the manner suggested by the examiner, and that such modification would “change the principle of operation of Yuh and thereby frustrate the purpose of Yuh, and thus be improper”. Remarks 15. The examiner fundamentally disagrees with Applicant’s characterization of the references and the combination. Yuh teaches a capacitance extraction method that uses a higher-accuracy extraction method in regions where accuracy is important, and a lower-accuracy method in other regions (¶23). Yuh is not limited to using methods of different dimensions, such as 3D or 2.5D, as suggested by Applicant, and it is not the “principle of operation” or “purpose” of Yuh to use different-dimensioned extraction methods. Yuh seeks to use a higher-accuracy method on important regions, and lower-accuracy methods elsewhere, in order to balance the known tradeoff between accuracy and speed. Thus, Yuh’s teachings are readily applicable to any known higher-accuracy and lower-accuracy methods. As discussed in the rejection, 3D field solvers using random walk methods are known, as taught by Yu. It is further known that the accuracy and speed of the random walk method depends on step size, as taught by Garcia, with larger step sizes improving speed but reducing accuracy, as taught by Szekely, Shang, and Su. Thus, it would be immediately apparent to persons having ordinary skill in the art that a random walk method with smaller step sizes (and thus higher accuracy) could be used as the higher-accuracy method in Yuh, and a random walk method with larger step sizes (and thus lower accuracy) could be used as the lower-accuracy method in Yuh.
Separately, Applicant also highlights an error in referring to US 6,829,754 as “Ratchkov” instead of “Yu”. Remarks 11, footnote 2. “Ratchkov” is the second-named inventor on the cited patent, and is referenced to avoid confusion with another cited reference “Yu” (“Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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17 December 2025
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851