DETAILED ACTION
In the response filed 16 April 2026, claim 1 was amended, claims 1, 3-13, 21-23, and 25-33 remain pending. Claims 21-23 and 25-29 remain allowable. Claims 1, 3, 7-8, 13, and 30-31 remain rejected. Claims 4-6, 9-12, and 32-33 remain objected to.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7-8, 13, 30, and 31 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Qin, US Patent No. 11,394,382.
In reference to claim 1, Qin teaches an apparatus (Figures 3, 4, 5) comprising:
a driver circuit (Figure 5, 3022) having a power terminal (Figure 5, input from VS through MP1), a driver input (Figure 5, VS_NT), a reference terminal (Figure 5, U1), and a driver output (Figure 5, 11);
a transistor (Figure 5, MP4) having a control terminal (Figure 5, input from 11) and a current terminal (Figure 5, section of 3022 connected to VOUT), the control terminal coupled to the driver output; and
a circuit coupled between the current terminal and the power terminal (Figure 3, 303, Figure 4, 303, Figure 5, MN3), the circuit configurable to transfer charge from the current terminal (Figures 3-5 VS) to the power terminal (Figures 3-5, VOUT).
In reference to claim 3, Qin teaches wherein the transistor is a first transistor, the control terminal is a first control terminal, and the circuit includes a second transistor (Figure 5, MP3) coupled between the current terminal and the power terminal (Figure 5, MP3 is between VS and VOUT indirectly), the second transistor having a second control terminal coupled to the reference terminal (Figure 5, control for MP3).
In reference to claim 7, Qin teaches a diode between the current terminal and power terminal (Figure 5, ZD3 is between VS and VOUT indirectly).
In reference to claim 8, Qin teaches wherein the drain-derived supply circuitry includes a diode (Figure 5, Diode ZD3) with an anode and a cathode, the anode is coupled to the second current terminal, the cathode is coupled to the first switch terminal (Figure 5 shows the anode of ZD3 indirectly coupled to drain of MP2 and the cathode indirectly coupled to the output terminal of the load switch circuit).
In reference to claim 13, Qin teaches wherein the transistor includes a field-effect transistor or a bipolar transistor (Column 4, lines 53-61).
In reference to claim 30, Qin teaches wherein the circuit is configurable to transfer the charge responsive to at least one of: a voltage drop across the transistor, a voltage increase of the reference terminal, or a voltage transient at the control terminal (Column 8, lines 49-59).
In reference to claim 31, Qin teaches wherein the circuit is configurable to maintain a voltage across the power terminal and the reference terminal within a range when the transistor is to be turned on (column 8, lines 30-40).
Allowable Subject Matter
Claims 21-23 and 25-29 are allowed.
Claims 4-6, 9-12, and 32-33 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: In reference to claims 4-6, in an apparatus (Figures 3, 4, 5) comprising:
a driver circuit (Figure 5, 3022) having a power terminal (Figure 5, section of 3022 connected to VOUT), a driver input (Figure 5, VS_NT), a reference terminal (Figure 5, U1), and a driver output (Figure 5, 11);
a transistor (Figure 5, MP4) having a control terminal (Figure 5, input from 11) and a current terminal (Figure 5, input from VS through MP1), the control terminal coupled to the driver output; and
a circuit coupled between the current terminal and the power terminal (Figure 3, 303, Figure 4, 303, Figure 5, MN3), the circuit configurable to transfer charge from the current terminal (Figures 3-5 VS) to the power terminal (Figures 3-5, VOUT);
prior art or record does not teach or clearly suggest wherein the current terminal is a first current terminal, the second transistor has a second current terminal coupled to the first current terminal, the second transistor has a third current terminal, and the circuit includes: a resistor having first and second resistor terminals, wherein the first resistor terminal is coupled to the third current terminal; and a third transistor having a fourth current terminal and a third control terminal, wherein the fourth current terminal is coupled to the first resistor terminal and the third current terminal, and the third control terminal is coupled to the second resistor terminal.
In reference to claims 9-12, in an apparatus (Figures 3, 4, 5) comprising:
a driver circuit (Figure 5, 3022) having a power terminal (Figure 5, section of 3022 connected to VOUT), a driver input (Figure 5, VS_NT), a reference terminal (Figure 5, U1), and a driver output (Figure 5, 11);
a transistor (Figure 5, MP4) having a control terminal (Figure 5, input from 11) and a current terminal (Figure 5, input from VS through MP1), the control terminal coupled to the driver output; and
a circuit coupled between the current terminal and the power terminal (Figure 3, 303, Figure 4, 303, Figure 5, MN3), the circuit configurable to transfer charge from the current terminal (Figures 3-5 VS) to the power terminal (Figures 3-5, VOUT);
prior art or record does not teach or clearly suggest wherein the switch has a switch control terminal, the driver circuit is a first driver circuit, the driver input 1s a first driver input, the driver output is a first driver output, and the apparatus further comprises: a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the switch control terminal, and the first driver input coupled to the second driver input.
In reference to claims 32-33, in an apparatus (Figures 3, 4, 5) comprising:
a driver circuit (Figure 5, 3022) having a power terminal (Figure 5, section of 3022 connected to VOUT), a driver input (Figure 5, VS_NT), a reference terminal (Figure 5, U1), and a driver output (Figure 5, 11);
a transistor (Figure 5, MP4) having a control terminal (Figure 5, input from 11) and a current terminal (Figure 5, input from VS through MP1), the control terminal coupled to the driver output; and
a circuit coupled between the current terminal and the power terminal (Figure 3, 303, Figure 4, 303, Figure 5, MN3), the circuit configurable to transfer charge from the current terminal (Figures 3-5 VS) to the power terminal (Figures 3-5, VOUT);
prior art or record does not teach or clearly suggest a diode bridge coupled between the power terminal and the reference terminal, the diode bridge coupled to a first capacitor terminal and a second capacitor terminal.
The following is an examiner’s statement of reasons for allowance:
In reference to claims 21-23 and 25-29, prior art of record does not teach or clearly suggest a system comprising: relay circuitry coupled to a battery charging terminal;
relay driver circuitry coupled to the relay circuitry; and switch circuitry coupled to the relay driver circuitry, the switch circuitry including: a driver circuit having a power terminal, a reference terminal, a driver input, and a driver output; a capacitor coupled between the power terminal and the reference terminal: a transistor having a control terminal and a current terminal, the control terminal coupled to the driver output; and a circuit coupled between the current terminal and the power terminal, the circuit configurable to transfer charge from the current terminal to the capacitor.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicants’ arguments filed 16 April 2026 have been fully considered but they are not persuasive. As described above, Qin still teaches the circuit of claim 1 despite the additional limitation. The terminology of the current terminal and power terminal in the previous office action can be swapped and still anticipate the circuit of claim 1. The circuit of Qin having the power terminal be voltage in and the current terminal be voltage out still reads on the claim.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no case, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
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/B.B/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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