DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/25 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The rejection of claim(s) 1 and 8-12 under 35 U.S.C. 103 as being unpatentable over Konno (US PGPub 2018/0102341, hereinafter referred to as “Konno”) in view of Morita et al. (US PGPub 2019/0181113, hereinafter referred to as “Morita”) has been maintained for reasons of record.
Konno discloses the semiconductor device substantially as claimed. See figure 1 and corresponding text, where Konno shows, in claim 1, a semiconductor device comprising:
Substrate (101) (figure 1; [0018])
an electrode (103) provided on the substrate (101); (figure 1; [0018])
a bonding layer (105) provided on the electrode (103) and made of a sintered body of metal particles having an average particle size of nano-order; (figure 1; [0027-0045]) and
a semiconductor element (107) bonded to the electrode (103) via the bonding layer (105),
Konno teaches, in claim 1, overlapping thickness of 50 to 500 μm thick, 80 to 300 μm thick, and 100 to 200 μm thick (figure 1; [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to incorporate wherein a layer thickness of the bonding layer is greater than or equal to 290 μm and less than or equal to 700 μm, in the method of Konno, according, where the prior art ranges are overlapping, a prima facie case of obviousness exists. (see MPEP 2144.05I)
Konno fails to explicitly show, in claim 1, an insulation board; wherein a layer thickness of the bonding layer (105) is greater than or equal to 290 μm and less than or equal to 700 μm.
Morita teaches, in claim 1, a similar device that includes a wiring board (6), (figure 4; [0068]). In addition, Morita provides the advantages of preventing partial fracture of the back surface of a semiconductor chip ([0014]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate an insulation board, in the device of Konno, according to the teachings of Morita, with the motivation of preventing partial fracture on the back surface of the semiconductor chip.
Konno in view of Morita fails to explicitly show, in claim 2, wherein a side surface of the bonding layer has a stair-like step in cross-sectional view. However, the applicant fails to provide in criticality regarding the shape.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein a side surface of the bonding layer has a stair-like step in cross-sectional view, into the device of Konno in view of Morita, with the motivation of it being a matter of design choice (See MPEP 2144.04)
Konno shows, in claim 3, wherein the bonding layer includes a first bonding layer (105) provided on the electrode (103). (figure 1; [0027])
Konno fails to show, in claim 3, a second bonding layer provided on the first bonding layer, and a third bonding layer provided on the second bonding layer, and a layer thickness of the second bonding layer is larger than a layer thickness of each of the first bonding layer and the third bonding layer.
Morita teaches, in claim 3, a similar device that includes adhesive layer can by a laminate of two or more layers (figure 1; [0066]). In addition, Morita provides the advantages of preventing partial fracture of the back surface of a semiconductor chip ([0014]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a second bonding layer provided on the first bonding layer, and a third bonding layer provided on the second bonding layer, and a layer thickness of the second bonding layer is larger than a layer thickness of each of the first bonding layer and the third bonding layer, in the device of Konno, according to the teachings of Morita, with the motivation of preventing partial fracture on the back surface of the semiconductor chip.
Konno in view of Morita shows, in claim 4, wherein the layer thickness of the second bonding layer is greater than or equal to 200 μm and less than or equal to 500 μm.
Therefore, It would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein the layer thickness of the second bonding layer is greater than or equal to 200 μm and less than or equal to 500 μm. In the device of Konno in view of Morita, with the motivation of preventing partial fracture of the back surface of a semiconductor chip. a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation.
Konno in view of Morita shows, in claim 5, wherein the layer thickness of each of the first bonding layer and the third bonding layer is greater than or equal to 10 μm and less than or equal to 100 μm. with the motivation of preventing partial fracture of the back surface of a semiconductor chip. With regards to the thickness of the bonding layer, Konno teaches overlapping ranges thus the obviousness exists especially since no criticality has been shown. (See MPEP 2144.05)
.
Konno in view of Morita fails to explicitly show, in claim 5, wherein the layer thickness of each of the first bonding layer and the third bonding layer is greater than or equal to 10 μm and less than or equal to 100 μm
Konno teaches, in claim 5, overlapping thickness of 50 to 500 μm thick, 80 to 300 μm thick, and 100 to 200 μm thick (figure 1; [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to incorporate wherein the layer thickness of each of the first bonding layer and the third bonding layer is greater than or equal to 10 μm and less than or equal to 100 μm, in the method of Konno in view Morita, according, where the prior art ranges are overlapping, a prima facie case of obviousness exists. (see MPEP 2144.05I)
Konno in view of Morita fails to show, in claim 6, wherein areas of the first bonding layer, the second bonding layer, and the third bonding layer in plane view satisfy the following expression, area of first bonding layer area of second bonding layer area of third bonding layer, area of first bonding layer > area of second bonding layer > area of third bonding layer.
However, Applicant fails to provide criticality for the dimensions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate , wherein areas of the first bonding layer, the second bonding layer, and the third bonding layer in plane view satisfy the following expression, area of first bonding layer area of second bonding layer area of third bonding layer, area of first bonding layer > area of second bonding layer > area of third bonding layer, into the device of Konno in view of Morita, with the motivation of it being a matter of design choice, Applicant fails to provide criticality for the dimensions (See MPEP 2144.04)
Konno in view of Morita fails to show, in claim 7, wherein side surfaces of the first bonding layer, the second bonding layer, and the third bonding layer have stair-like steps in cross-sectional view.
However, Applicant fails to provide criticality for the dimensions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein a side surface of the bonding layer has a stair-like step in cross-sectional view, into the device of Konno in view of Morita, with the motivation of it being a matter of design choice Applicant fails to provide criticality for the dimensions (See MPEP 2144.04), choice Applicant fails to provide criticality for the dimensions.
Konno in view of Morita fail shows, in claim 8, wherein the average particle size of the metal particles is greater than or equal to 10 nm and less than or equal to 100 nm
Konno teaches, in claim 8, overlapping thickness of 50 to 500 μm thick, 80 to 300 μm thick, and 100 to 200 μm thick (figure 1; [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to incorporate wherein the layer thickness of each of the first bonding layer and the third bonding layer is greater than or equal to 10 μm and less than or equal to 100 μm, in the method of Konno in view Morita, according, where the prior art ranges are overlapping, a prima facie case of obviousness exists. (see MPEP 2144.05I)
Konno in view of Morita shows, in claim 9, wherein a material of the metal particles is Ag. ([0029], Konno)
Konno in view of Morita shows, in claim 10, wherein a material of the electrode is Cu or Al. ([0018], Konno)
Konno in view of Morita shows, in claim 11, wherein a metal layer including a material different from a metal material of the electrode is provided on the electrode, and the material of the metal layer is any of Au, Pt, Pd, Ag, Cu, Ti and Ni.([0022], Konno)
Konno in view of Morita shows, in claim 12, wherein a material of the semiconductor element is any of silicon carbide, gallium nitride, gallium arsenide and diamond. ([0021], Konno)
Response to Arguments
Applicant's arguments filed 12/17/25 have been fully considered but they are not persuasive. Applicant raises the clear issue as to whether Konna alone or in combination with Morita suggests greater than or equal to 290 μm and less than or equal to 700 μm.
The examiner views that the combination of both Konno in view of Morita does suggest the above limitation and/or and or statements. Specifically, Konno teaches the ranges of 50-500 μm, 80-300 μm and 100-200 μm for the bonding layer (105), thus meets the limitation (figure 1; [0019]). Specifically, in paragraph [0058], Konno states that the first metal powder performs the function of promoting the sintering and bonding between the metals at low temperature in the conductive paste. Therefore, the sintering of the sintered body of metal particles have been met, especially since the claim calls for the layer thickness of the “bonding layer” not the sintered layer. Lastly, it appears that the applicant is arguing the process of the film, however the claim is drawn to the final product.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 January 10, 2026