DETAILED ACTION
Claims 1-32 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-12, 14-20, 22-28 and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Fahs et al. (US 2011/0078417 A1) in further view of Glanville et al. (US 9,195,460 B1).
Regarding claim 1, Fahs teaches the invention substantially as claimed including one or more processors ([0022] the parallel processing subsystem 112 incorporates circuitry… In yet another embodiment, the parallel processing subsystem 112 may be integrated with one or more other system elements, such as the memory bridge 105, CPU 102, and I/O bridge 107 to form a system on chip (SoC).), comprising:
circuitry to;
use each bit of one or more mask data structures to indicate a completion of a plurality of thread groups of a processor pipeline, wherein each thread group of the plurality of thread groups is associated with a corresponding individual bit of the one or more mask data structures that is to indicate that each thread of the corresponding thread group has arrived at a synchronization barrier ([0037-38] processor pipeline and pipelined instructions; [0069] The wait/go registers 508 keep track of which thread groups have reached the barrier point set by a barrier synchronization instruction or barrier aggregation instruction and are waiting for one or more other thread groups to synchronize at that barrier point. In one embodiment, the wait/go registers 508 are implemented using a single bit corresponding to each thread group. Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point.; [0080] The wait/go registers 538 keep track of which thread groups have reached which barrier points and are waiting for synchronization to be achieved. In one embodiment, the wait/go registers 538 include a wait/go bit and a BarID field for each of the G thread groups that can concurrently execute in the SPM 310. The wait/go bit is set to the wait state (e.g., logic high) when the corresponding thread group is waiting at one of the barrier points to synchronize with one or more other thread groups of the CTA and to the go state (e.g., logic low) when the corresponding thread group is not waiting at any barrier point. The BarID field for each thread group whose wait/go bit is in the wait state is populated with the barrier identifier of the barrier point at which the thread group is waiting.).
Fahs teaches a wait/go register comprised of bits used to indicate whether a thread group has reached a synchronization barrier, the wait/go register reasonably encompasses the data structure as it is a structure including status bit for each thread group. Fahs does not explicitly recite the data structure as being a mask.
However, Glanville teaches mask data structures (Col. 11, line 61 through Col. 12, line 8: Thread state unit 525 is configured to maintain an active mask and an active program counter for each of the thread groups processed by multithreaded processing unit 500…Thus, when all bits in the active mask are set, multithreaded processing unit 500 is operating in fully synchronized mode for execution of the thread group associated with the active mask.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of a mask as taught by Glanville with the wait/go registers as taught by Fahs as they both are structures that store bit indicating status of a thread group. The modification would have been motivated by the desire of performing a simple substitution of one known element masks for another such as registers to obtain predictable results of mask structures containing bits indicating status of thread groups.
Regarding claim 2, Fahs teaches wherein the one or more mask data structures stores synchronization information for the plurality of thread groups in a single addressable memory location ([0069] The wait/go registers 508 keep track of which thread groups have reached the barrier point set by a barrier synchronization instruction or barrier aggregation instruction and are waiting for one or more other thread groups to synchronize at that barrier point. In one embodiment, the wait/go registers 508 are implemented using a single bit corresponding to each thread group. Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point.).
In addition, Glanville teaches mask data structures (Col. 11, line 61 through Col. 12, line 8: Thread state unit 525 is configured to maintain an active mask and an active program counter for each of the thread groups processed by multithreaded processing unit 500…Thus, when all bits in the active mask are set, multithreaded processing unit 500 is operating in fully synchronized mode for execution of the thread group associated with the active mask.).
Regarding claim 3, Fahs teaches wherein the synchronization information is stored as a bit field with distinct bits, each bit indicating synchronization of an individual group of threads ([0069] Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point.).
Regarding claim 4, Fahs teaches wherein individual bits of the bit field represent a subgroup of threads capable of being executed in parallel on a symmetric multiprocessor ([0039] The series of instructions transmitted to a particular GPC 208 constitutes a thread, as previously defined herein, and the collection of a certain number of concurrently executing threads across the parallel processing engines (not shown) within an SPM 310 is referred to herein as a "warp" or "thread group." As used herein, a "thread group" refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different processing engine within an SPM 310. A thread group may include fewer threads than the number of processing engines within the SPM 310, in which case some processing engines will be idle during cycles when that thread group is being processed. A thread group may also include more threads than the number of processing engines within the SPM 310, in which case processing will take place over consecutive clock cycles. Since each SPM 310 can support up to G thread groups concurrently, it follows that up to G*M thread groups can be executing in GPC 208 at any given time.; [0065] a subset of a CTA; [0069]).
Regarding claim 6, Glanville teaches wherein the one or more mask data structures indicate a state of one or more of the plurality of thread groups (Col. 11, line 61 through Col. 12, line 8: Thread state unit 525 is configured to maintain an active mask and an active program counter for each of the thread groups processed by multithreaded processing unit 500…Thus, when all bits in the active mask are set, multithreaded processing unit 500 is operating in fully synchronized mode for execution of the thread group associated with the active mask.).
Regarding claim 7, Fahs teaches wherein each of the plurality of thread groups is a cooperative thread group ([0040] Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SPM 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array.").
Regarding claim 8, Fahs teaches wherein the cooperative thread group spans a plurality of warps ([0040] Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SPM 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array.").
Regarding claim 9, it is a method type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above.
Regarding claim 10, it is a method type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 11, it is a method type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 12, it is a method type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Regarding claim 14, it is a method type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 15, it is a method type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 16, it is a method type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Regarding claim 17, it is a system type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above. Further the additional limitations of a computer system comprising one or more processors and memory storing executable instructions that, as a result of being executed by the one or more processors, cause the computer system to perform are taught by Fahs in at least Claim 12 “A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform an aggregation operation across multiple threads, by performing the steps of”.
Regarding claim 18, it is a system type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 19, it is a system type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 20, it is a system type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Regarding claim 22, it is a system type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 23, it is a system type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 24, it is a system type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Regarding claim 25, it is a media/product type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above. Further the additional limitations of A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to perform are taught by Fahs in at least Claim 12 “A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform an aggregation operation across multiple threads, by performing the steps of”.
Regarding claim 26, it is a media/product type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 27, it is a media/product type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 28, it is a media/product type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Regarding claim 30, it is a media/product type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 31, it is a media/product type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 32, it is a media/product type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Claims 5, 13, 21, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Fahs and Glanville, as applied to claim 2 above, in further view of Russell (US 7,519,967 B1).
Regarding claim 5, Fahs nor Glanville expressly teach wherein the synchronization information is manipulated using an atomic logical operation.
However, Russell teaches wherein the synchronization information is manipulated using an atomic logical operation (Col. 1, lines 60-67: if the synchronization information indicates that the lock is biasable and the lock is presently unbiased, the system uses an atomic operation to attempt to update the synchronization information to indicate that the lock is biased toward the current thread. If this atomic operation succeeds and the lock is biased toward the current thread, the system allows the current thread to acquire the lock.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Russell with the teachings of Fahs and Glanville to utilize atomic operations to update the synchronization information. The modification would have been motivated by the desire of indicating that the lock is biased toward the current thread.
Regarding claim 13, it is a method type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale above.
Regarding claim 21, it is a system type claim having similar limitations as claim 5 above.
Therefore, it is rejected under the same rationale above.
Regarding claim 29, it is a media/product type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale above.
Response to Arguments
Applicant’s arguments with respect to claims 1-32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE A CHU JOY-DAVILA whose telephone number is (571)270-0692. The examiner can normally be reached Monday-Friday, 6:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J Li can be reached at (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JORGE A CHU JOY-DAVILA/ Primary Examiner, Art Unit 2195
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