DETAILED ACTION
Claims 1-32 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-12, 14-20, 22-28 and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Fahs et al. (US 2011/0078417 A1).
Fahs was cited in the previous Office Action.
Regarding claim 1, Fahs teaches the invention as claimed including one or more processors ([0022] the parallel processing subsystem 112 incorporates circuitry… In yet another embodiment, the parallel processing subsystem 112 may be integrated with one or more other system elements, such as the memory bridge 105, CPU 102, and I/O bridge 107 to form a system on chip (SoC).), comprising:
circuitry to:
use each bit of one or more barrier data structures to indicate that a corresponding thread group of a plurality of thread groups of a processor pipeline has arrived at a synchronization barrier corresponding to the one or more barrier data structures ([0050] A sequence of per-thread instructions may include at least one instruction that defines a cooperative behavior between the representative thread and one or more other threads of the thread array. For example, the sequence of per-thread instructions might include an instruction to suspend execution of operations for the representative thread at a particular point in the sequence until such time as one or more of the other threads reach that particular point, [0069] The wait/go registers 508 keep track of which thread groups have reached the barrier point set by a barrier synchronization instruction or barrier aggregation instruction and are waiting for one or more other thread groups to synchronize at that barrier point; wherein the registers 508 correspond to the claimed barrier data structures);
determine, based on values of bits corresponding to the plurality of thread groups in the one or more barrier data structures, that a thread group of the plurality of thread groups is last to arrive at the synchronization barrier ([0058] In one embodiment, execution of barrier arrival and barrier synchronization instructions, i.e., arrival of thread groups at barrier points is detected by the warp scheduler and instruction unit 312 of FIG. 4, which can suspend the issue of instructions to any execution unit 302 allocated to execute a thread group that is waiting at a barrier point while continuing to issue instructions to other execution units 302 that are allocated to execute other thread groups that are not at a barrier synchronization point. (i.e., have not arrived/last to arrive); [0069] The wait/go registers 508 keep track of which thread groups have reached the barrier point set by a barrier synchronization instruction or barrier aggregation instruction and are waiting for one or more other thread groups to synchronize at that barrier point. (i.e., last to arrive). Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point.); and
in response to determining that the thread group is last to arrive, cause each of the plurality of thread groups to be released from the synchronization barrier ([0069] In response to a barrier arrival instruction for a thread group, barrier instruction execution unit 500 (or 550) increments the counter 504 (or 534) but does not set the bit corresponding to the thread group in the wait/go registers 508 (or 538) to the wait state, thus, the thread group can continue to execute.; once that the missing group(s) arrive, execution may continue since it/they are the last to arrive; [0058] Eventually, all participating thread groups reach the barrier synchronization point, and execution of the waiting thread group(s) resumes.).
Fahs does not explicitly recite a pipeline, but in at least [0050] discusses a sequence of instructions that are arranged in a sequence requiring subsequent instructions to wait for other instructions which reasonably constitutes a pipeline. Therefore, it would have been obvious to one of ordinary skill in the art to read Fahs’ sequence of instructions as a pipeline.
Regarding claim 2, Fahs teaches wherein the one or more barrier data structures stores synchronization information for the plurality of thread groups in a single addressable memory location ([0069] The wait/go registers 508 keep track of which thread groups have reached the barrier point set by a barrier synchronization instruction or barrier aggregation instruction and are waiting for one or more other thread groups to synchronize at that barrier point. In one embodiment, the wait/go registers 508 are implemented using a single bit corresponding to each thread group. Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point.).
Regarding claim 3, Fahs teaches wherein the synchronization information is stored as a bit field with distinct bits, each bit indicating synchronization of an individual group of threads ([0069] Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point.).
Regarding claim 4, Fahs teaches wherein individual bits of the bit field represent a subgroup of threads capable of being executed in parallel on a symmetric multiprocessor ([0039] The series of instructions transmitted to a particular GPC 208 constitutes a thread, as previously defined herein, and the collection of a certain number of concurrently executing threads across the parallel processing engines (not shown) within an SPM 310 is referred to herein as a "warp" or "thread group." As used herein, a "thread group" refers to a group of threads concurrently executing the same program on different input data, with one thread of the group being assigned to a different processing engine within an SPM 310. A thread group may include fewer threads than the number of processing engines within the SPM 310, in which case some processing engines will be idle during cycles when that thread group is being processed. A thread group may also include more threads than the number of processing engines within the SPM 310, in which case processing will take place over consecutive clock cycles. Since each SPM 310 can support up to G thread groups concurrently, it follows that up to G*M thread groups can be executing in GPC 208 at any given time.; [0065] a subset of a CTA; [0069]).
Regarding claim 6, Fahs teaches wherein the one or more barrier data structures indicate a state of one or more of the plurality of thread groups (Col. 11, line 61 through Col. 12, line 8: Thread state unit 525 is configured to maintain an active mask and an active program counter for each of the thread groups processed by multithreaded processing unit 500…Thus, when all bits in the active mask are set, multithreaded processing unit 500 is operating in fully synchronized mode for execution of the thread group associated with the active mask.).
Regarding claim 7, Fahs teaches wherein each of the plurality of thread groups is a cooperative thread group ([0040] Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SPM 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array.").
Regarding claim 8, Fahs teaches wherein the cooperative thread group spans a plurality of warps ([0040] Additionally, a plurality of related thread groups may be active (in different phases of execution) at the same time within an SPM 310. This collection of thread groups is referred to herein as a "cooperative thread array" ("CTA") or "thread array.").
Regarding claim 9, it is a method type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above.
Regarding claim 10, it is a method type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 11, it is a method type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 12, it is a method type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Regarding claim 14, it is a method type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 15, it is a method type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 16, it is a method type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Regarding claim 17, it is a system type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above. Further the additional limitations of a computer system comprising one or more processors and memory storing executable instructions that, as a result of being executed by the one or more processors, cause the computer system to perform are taught by Fahs in at least Claim 12 “A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform an aggregation operation across multiple threads, by performing the steps of”.
Regarding claim 18, it is a system type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 19, it is a system type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 20, it is a system type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Regarding claim 22, it is a system type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 23, it is a system type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 24, it is a system type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Regarding claim 25, it is a media/product type claim having similar limitations as claim 1 above. Therefore, it is rejected under the same rationale above. Further the additional limitations of A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to perform are taught by Fahs in at least Claim 12 “A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform an aggregation operation across multiple threads, by performing the steps of”.
Regarding claim 26, it is a media/product type claim having similar limitations as claim 2 above. Therefore, it is rejected under the same rationale above.
Regarding claim 27, it is a media/product type claim having similar limitations as claim 3 above. Therefore, it is rejected under the same rationale above.
Regarding claim 28, it is a media/product type claim having similar limitations as claim 4 above. Therefore, it is rejected under the same rationale above.
Regarding claim 30, it is a media/product type claim having similar limitations as claim 6 above. Therefore, it is rejected under the same rationale above.
Regarding claim 31, it is a media/product type claim having similar limitations as claim 7 above. Therefore, it is rejected under the same rationale above.
Regarding claim 32, it is a media/product type claim having similar limitations as claim 8 above. Therefore, it is rejected under the same rationale above.
Claims 5, 13, 21, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Fahs, as applied to claim 2 above, in further view of Russell (US 7,519,967 B1).
Regarding claim 5, Fahs does not expressly teach wherein the synchronization information is manipulated using an atomic logical operation.
However, Russell teaches wherein the synchronization information is manipulated using an atomic logical operation (Col. 1, lines 60-67: if the synchronization information indicates that the lock is biasable and the lock is presently unbiased, the system uses an atomic operation to attempt to update the synchronization information to indicate that the lock is biased toward the current thread. If this atomic operation succeeds and the lock is biased toward the current thread, the system allows the current thread to acquire the lock.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Russell with the teachings of Fahs to utilize atomic operations to update the synchronization information. The modification would have been motivated by the desire of indicating that the lock is biased toward the current thread.
Regarding claim 13, it is a method type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale above.
Regarding claim 21, it is a system type claim having similar limitations as claim 5 above.
Therefore, it is rejected under the same rationale above.
Regarding claim 29, it is a media/product type claim having similar limitations as claim 5 above. Therefore, it is rejected under the same rationale above.
Response to Arguments
Applicant's arguments filed on 06/30/2026 have been fully considered but they are not persuasive.
In Remarks Applicant argues:
(I) The combination of Fahs and Glanville fails to teach or suggest "determine, based on values of bits corresponding to the plurality of thread groups in the barrier data structure, that a thread group of the plurality of thread groups is last to arrive at the synchronization barrier; and in response to determining that the thread group is last to arrive, cause each of the plurality of thread groups to be released from the synchronization barrier."
That is, Fahs teaches a register in which each bit indicates whether a corresponding thread group is waiting at a barrier. The register is used to assign instructions to thread groups that are not currently active. Further, as indicated in the Office Action, Fahs does not describe a barrier data structure. It also doesn't disclose "determine, based on values of bits corresponding to the plurality of thread groups in the barrier data structure, that a thread group of the plurality of thread groups is last to arrive at the synchronization barrier; and in response to determining that the thread group is last to arrive, cause each of the plurality of thread groups to be released from the synchronization barrier."
In view of the above, examiner submits the following:
As to point (I)
Examiner respectfully disagrees with the Applicant for at least the following reasons. Upon further review of the amended claims and review of the prior art, examiner finds Fahs to teach the invention as claimed. Fahs teaches:
[0057] In some embodiments of the present invention, a barrier synchronization technique is advantageously used to support fast synchronization of any number of CTA thread groups. More specifically, barrier synchronization instructions are inserted into the CTA program at points (referred to herein as "barrier synchronization points") where thread synchronization is desired. A thread executes a barrier synchronization instruction to indicate that the thread group has arrived at a barrier point and waits at that point until all other participating thread groups have also arrived at that point, thus synchronizing the participating thread groups before resuming execution of a program.
[0058] In one embodiment, execution of barrier arrival and barrier synchronization instructions, i.e., arrival of thread groups at barrier points is detected by the warp scheduler and instruction unit 312 of FIG. 4, which can suspend the issue of instructions to any execution unit 302 allocated to execute a thread group that is waiting at a barrier point while continuing to issue instructions to other execution units 302 that are allocated to execute other thread groups that are not at a barrier synchronization point. Eventually, all participating thread groups reach the barrier synchronization point, and execution of the waiting thread group(s) resumes.
[0069] The wait/go registers 508 keep track of which thread groups have reached the barrier point set by a barrier synchronization instruction or barrier aggregation instruction and are waiting for one or more other thread groups to synchronize at that barrier point. In one embodiment, the wait/go registers 508 are implemented using a single bit corresponding to each thread group. Each bit is set to a "wait" state (e.g., logic high) when the corresponding thread group is waiting at the barrier point to synchronize with one or more other thread groups and to a "go" state (e.g., logic low) when the corresponding thread group is not waiting at (has not yet reached) the barrier point. In response to a barrier arrival instruction for a thread group, barrier instruction execution unit 500 (or 550) increments the counter 504 (or 534) but does not set the bit corresponding to the thread group in the wait/go registers 508 (or 538) to the wait state; thus, the thread group can continue to execute.
As highlighted above, Fahs explicitly teach "determine, based on values of bits corresponding to the plurality of thread groups in the barrier data structure, that a thread group of the plurality of thread groups is last to arrive at the synchronization barrier” In [0069], Fahs discuss the usage of bits highs and lows to identify whether a thread group is waiting, due to it arriving at the barrier and low when it is still executing i.e., last group(s) to arrive.
“and in response to determining that the thread group is last to arrive, cause each of the plurality of thread groups to be released from the synchronization barrier." Fahs teaches in at least [0057] and [0058] that once all thread groups reach the barrier execution of the program is resumed. Accordingly, Applicant’s arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE A CHU JOY-DAVILA whose telephone number is (571)270-0692. The examiner can normally be reached Monday-Friday, 6:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J Li can be reached at (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JORGE A CHU JOY-DAVILA/Primary Examiner, Art Unit 2195
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