DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/29/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (U.S. PG Pub No US2020/0176552A1) (of record).
Regarding claim 11, Chang teaches a semiconductor arrangement (2200) fig. 22 [0092] (see annotated fig. 22 of Chang below), comprising:
a first conductive layer (lower 114) fig. 22 [0028, 0094] (formed of electrically conductive material such as doped polysilicon or titanium nitride) [0028];
a first dielectric layer (lower 112) fig. 22 [0090] over the first conductive layer (lower 114) (see annotated fig. 22 of Chang below);
a second conductive layer (upper 114) fig. 22 [0028, 0094] (formed of electrically conductive material such as doped polysilicon or titanium nitride) [0028] over a portion of the first dielectric layer (lower 112) and having a sidewall surface (left sidewall of upper 114) (see annotated fig. 22 of Chang below);
a second dielectric layer (upper 112) fig. 22 [0090] over the second conductive layer (upper 114) and having a sidewall surface (left sidewall of upper 112);
a spacer (portion of 1010b) fig. 22 [0091] (see annotated fig. 22 of Chang below) over (partially above) a portion of the sidewall surface of the second conductive layer (left sidewall of upper 114), over a portion of the sidewall surface of the second dielectric layer (left sidewall of upper 112), and covering an interface (partially covering left portions of interface) between the second conductive layer (upper 114) and the first dielectric layer (lower 112),
wherein:
the first conductive layer (lower 114), the first dielectric layer (lower 112), and the second conductive layer (upper 114) define a capacitor (are capacitor dielectric layers and electrodes [0090]),
the spacer (portion on 1010b) comprises a first (inner, right sidewall) sidewall surface facing (towards) the second conductive layer (upper 114) and the second dielectric layer (upper 112) and a second (outer, left) sidewall surface facing opposite the first (inner, right) sidewall surface; and
a third dielectric layer (1020a) fig. 22 [0094] in direct physical contact with the second (outer, left) sidewall surface and overlying an uppermost surface of the spacer (uppermost surface of 1010b portion) such that a line (LINE; annotated fig. 22 below) perpendicular to a top surface of the first conductive layer (lower 114) intersects the third dielectric layer (1020a) and the spacer (1010b portion) (see annotated fig. 22 of Chang below), and
[AltContent: textbox (LINE)][AltContent: textbox (LINE)]a second spacer (1010a) fig. 22 [0065] interfacing with a sidewall of the first conductive layer (lower 114), wherein the spacer (1010b) and the second spacer (1010a) are formed of different materials (1010a and 1010b [0065] may be formed of different layers of different materials [0065] – 1010a may be a silicon oxide layer while 1010b is a silicon nitride layer [0065]). [AltContent: textbox (1010a)][AltContent: textbox (1010b)][AltContent: arrow][AltContent: arrow]
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t.[AltContent: arrow][AltContent: textbox (Interconnect 304c)]
Annotated fig. 22 of Chang for independent claim 11 and dependents
Regarding claim 12, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. Chang also teaches wherein a bottom surface of the second dielectric layer (upper 112) fig. 22 [0090] is in direct physical contact with a top surface of the second conductive layer (upper 114) fig. 22 [0028, 0094].
Regarding claim 14, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. Chang also teaches comprising:
an interconnect structure (left 304c) fig. 22 [0094] physically contacting the first conductive layer (lower 114) fig. 22 [0028, 0094], wherein the third dielectric layer (1020a) fig. 22 [0094] is laterally between the second (outer) sidewall surface of the spacer (portion of 1010b) annotated fig. 22 above [0091] and a sidewall surface of the interconnect structure (left 304c) such that the interconnect structure (left 304c) is spaced apart from the spacer (portion of 1010b) by the third dielectric layer (1020a).
Regarding claim 15, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. Chang also teaches wherein the second conductive layer (upper 114) fig. 22 [0028, 0094] and the second dielectric layer (upper 112) fig. 22 [0090] are (vertically) spaced apart from the third dielectric layer (1020a) fig. 22 [0094] by the spacer (portion of 1010b) annotated fig. 22 above [0091].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) (of record), as applied in claim 11 above, in view of Kim (U.S. PG Pub No US2019/0131367A1) (of record).
Regarding claim 13, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. However, Chang does not explicitly disclose wherein the spacer (portion of 1010b) fig. 22 [0091] comprises a metal halide (possibly silicon nitride SiN instead [0091]).
Kim teaches a semiconductor arrangement (comprising a capacitor) [0045-0046, 0109] wherein the spacer (comprising I-INS, O-INS, and BR) fig. 1 [0062] comprises a metal halide (such as titanium fluoride [0065]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have annotated the spacer material in the semiconductor structure comprising a capacitor of Chang to include a titanium-fluoride comprising barrier layer interfacing the metal layer and insulating material [0062-0065] in order to provide etch protection to the spacer layer [0069] as well as protect metal material in the semiconductor structure from corrosion and diffusion [0066-0068], as taught by Kim.
8. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (U.S. PG Pub No US2020/0176552A1) (of record), as applied in claim 11 above, in view of Chou (U.S. PG Pub No US2018/0076276A1) (of record).
Regarding claim 16, Chang teaches the semiconductor arrangement (2200) fig. 22 [0092] of claim 11. However, Chang does not explicitly disclose comprising:
an interconnect structure contacting the second conductive layer (upper 114) fig. 22 [0028, 0094].
Chou teaches a semiconductor arrangement (1) fig. 1 [0009], comprising:
an interconnect structure (13b) fig. 1 [0009] (physically) contacting the second conductive layer (12b) fig. 1 [0009].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor arrangement of Chang such that an additional interconnect structure is disposed in direct physical contact with the claimed second conductive layer [0009] in order to enhance the integration density of electrical interconnects with the capacitor layers [0002], as taught by Chou.
Allowable Subject Matter
Claims 17, 19-23, and 25-32 allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 17 is allowed because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “and a second spacer interfacing with a sidewall of the first metal layer, wherein the spacer and the second spacer are formed of different materials” in the context of claim 17. Claims 19-20 and 32 are also allowed by virtue of their dependency on claim 17.
Claim 21 is allowed because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “and a second spacer interfacing with a sidewall of the first metal layer, wherein the spacer and the second spacer are formed of different materials” in the context of claim 21. Claims 19-20 and 32 are also allowed by virtue of their dependency on claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 11 have been fully considered but are not found persuasive because they have not specifically addressed consideration of element 1010a of Chou as the claimed second spacer – as presented in the 35 U.S.C. 102 rejection above. However, if Applicant were to amend claim 11 to further require that the other “spacer” / “first spacer” is also in “direct contact” with and/or “interfaces” with a sidewall surface of, for example, the claimed “second conductive layer” – in a manner analogous to what is also required of claims 17 and claim 21 – claim 11 would also be brought into condition for allowance in a manner consistent with the allowable subject matter of the context of claims 17 and 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kuo (U.S. PG Pub No US2020/0098855A1) (of record) teaches another example of a deep trench capacitor with additional dielectric layers in direct contact with the claimed first dielectric layer.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 09/23/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
