Prosecution Insights
Last updated: October 26, 2026

Sean Ayers Winters, USPTO Patent Examiner

Listed by the USPTO as WINTERS, SEAN AYERS

Tech Center 2800 • Art Units: 2892 2898

This examiner grants 89% of resolved cases

Analysis

WINTERS, SEAN AYERS has resolved 159 cases in tech center 2800 and art unit 2892. The allowance rate is 88.7%, and the median time to allowance is 1223 days. The interview lift is 17.9%, indicating a positive interview association.

The listed companies are Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and Samsung Display Co., Ltd. The listed firms are Cooper Legal Group LLC, CANTOR COLBURN LLP, and Eschweiler & Potashnik, LLC (TSMC). The allowance rate is high, but the median timeline is extended, so practitioners should pair positive outcome expectations with deliberate pendency planning.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

88.7%
Allow Rate
+20.7% vs TC avg
229
Total Applications
+17.9%
Interview Lift
1223
Avg Prosecution Days
Based on 159 resolved cases, 2023–2026

Rejection Statute Breakdown

0%
§101 Eligibility
31.3%
§102 Novelty
58.1%
§103 Obviousness
10.3%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18740580 SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME Non-Final OA Samsung Electronics Co., Ltd.
18665984 SEMICONDUCTOR DEVICE HAVING LANDING PAD STRUCTURE Non-Final OA Samsung Electronics Co., Ltd.
18422513 DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE Non-Final OA Samsung Display Co., LTD.
18539529 DISPLAY DEVICE Non-Final OA Samsung Display Co., Ltd.
18832489 SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE Non-Final OA Mitsubishi Electric Corporation
18035397 SINGLE PHASE HIGH ENTROPY INTERMETALLICS AND METHOD FOR MANUFACTURING Non-Final OA THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
18556509 SUBSTRATE, PACKAGE, ELECTRONIC COMPONENT, AND LIGHT EMITTING DEVICE Non-Final OA KYOCERA Corporation
18035159 SEMICONDUCTOR ELECTRONIC DEVICES INCLUDING SIDEWALL BARRIER LAYERS AND METHODS OF FABRICATING THE SAME Final Rejection CORNING INCORPORATED
18152790 TRANSISTOR GATE STACK Non-Final OA INTERNATIONAL BUSINESS MACHINES CORPORATION
18191617 FORMING OF TRENCHES IN A SUBSTRATE Non-Final OA STMicroelectronics (Crolles 2) SAS
18731465 DEVICE WITH EPITAXIAL SOURCE/DRAIN REGION Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18406238 METHODS AND COMPUTER-READABLE MEDIUM RELATED TO FERROELECTRIC MEMORY Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
18395841 IMAGE SENSORS AND METHODS OF MANUFACTURE Final Rejection Taiwan Semiconductor Manufacturing Company, Ltd.
18784624 INTEGRATED CIRCUIT WITH NANOSHEET TRANSISTORS WITH METAL GATE PASSIVATION Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18787593 SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
18515320 MULTI-TIER SEMICONDUCTOR DIE STACKS USING METAL-TO-METAL BONDING AND METHODS OF FORMING THE SAME Final Rejection Taiwan Semiconductor Manufacturing Company Limited
17738169 TRANSISTOR STRUCTURE HAVING REDUCED CONTACT RESISTANCE AND METHODS OF FORMING THE SAME Non-Final OA Taiwan Semiconductor Manufacturing Company Limited
17367698 SEMICONDUCTOR ARRANGEMENT INCLUDING A SPACER ADJACENT A CONDUCTIVE LAYER AND METHOD OF MAKING Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

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Frequently Asked Questions

What is examiner Sean Ayers Winters's allowance rate?

88.7% of resolved applications examined by Sean Ayers Winters were allowed (159 resolved cases), compared with 71.9% across Art Unit 2892 over the last five years.

Does an interview help with examiner Sean Ayers Winters?

This examiner's interview lift is +17.9 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Sean Ayers Winters take to allow a patent?

Applications allowed by Sean Ayers Winters took 1,223 days on average from filing to allowance.

Which art unit does examiner Sean Ayers Winters work in?

Sean Ayers Winters examines applications in Art Unit 2892 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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