Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 7/24/2025 has been entered. Claim 1, 9, 14, 20, 21 are amended. Claims 11, 15 are canceled without prejudice. Claims 1 – 10, 12 – 14, 16 – 21 are pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 10, 12 – 14, 16 – 17, 19 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ( Pub. No. KR 100849993 B1 ), hereinafter Kim, in view of Ganguly ( Pub. No. 20110281429 A1 ), hereinafter Ganguly.
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Regarding ( Currently Amended ) Independent Claim 1, Kim teaches ( Kim, Drawing 1 ) a neuromorphic synaptic device comprising:
a body layer ( Kim, Drawing 1, area between channel 19 and substrate 10 ) formed on a semiconductor substrate ( Kim, Drawing 1, substrate 10 );
a source and a drain ( Kim, Drawing 1, source 12 and drain 14 ) formed at a left side and a right side, or an upper side and a lower side of the body layer;
a contact metal ( Kim, Drawing 3, metal film 32 ) configured to form a schottky junction ( Kim, page 1, flash memory device using asymmetric Schottky barrier ) with the source ( Kim, Drawing 1, source 12 and drain 14 ), the source having a light doping concentration sufficient for a schottky tunneling current to flow ( Kim, page 10, an asymmetric SB NOR-type flash memory devices exhibit significantly higher current than conventional NOR-type flash memory devices and symmetric SB NOR-type flash memory devices ) during a transition region of the neuromorphic device, the contact metal in contact with the source and the drain ( Kim, claim 1, using an asymmetric Schottky barrier characterized by different junction depths of the source region and the drain region; Kim, page 1, flash memory device using asymmetric Schottky barrier; a high doping concentration is induced around the Schottky barrier of the drain; Kim’s disclosure inherently suggests varying doping concentration strategies at source and drain to optimize device characteristics. Therefore, forming a Schottky junction at a source with lighter doping concentration to facilitate tunneling currents would be inherent or obvious based on Kim’s disclosure );
a gate insulating layer ( Kim, Drawing 1, gate oxide layer 17 + gate 16 + tunnel oxide film 15 ) formed on the body layer, and including an oxide layer ( Kim, Drawing 1, gate oxide layer 17 or tunnel oxide film 15 ) and a charge storage layer ( Kim, Drawing 1, gate 16 ) forming a charge trap ( Kim, FIG. 8, charge stored in a floating gate 16 ); and
a gate ( Kim, Drawing 1, control gate 18 ) formed on the gate insulating layer ( Kim, Drawing 1, gate oxide layer 17 + gate 16 + tunnel oxide film 15 )
wherein the source and the drain form an asymmetric ( Kim, page 1, flash memory device using asymmetric Schottky barrier; Kim, page 10, an asymmetric SB NOR-type flash memory devices exhibit significantly higher current than conventional NOR-type flash memory devices and symmetric SB NOR-type flash memory devices ) structure in a concentration blocking a sneaky path of a neuron and a synapse array ( Kim, page 5, line 6 counted from bottom, In addition, the present invention induces a high doping concentration around the Schottky barrier of the drain, thereby increasing the hot electron effect, thereby improving the NOR performance; Kim, page 11, As in this embodiment, when a Schottky barrier is used in the drain, a high doping concentration is induced around the Schottky barrier, which increases the hot electron effect, thereby improving the write speed of the NOR flash structure ).
Kim fails to disclose:
wherein the charge storage layer includes a silicon nitride and:
a first region of a first silicon nitride composition having a first characteristic and a second region of a second silicon nitride composition having a second different characteristic, wherein a composition ratio of silicon (Si) and nitrogen (N) is different for the first and second silicon nitride compositions, the first silicon nitride composition has a composition ratio of silicon (Si) higher than nitrogen (N), the second silicon nitride composition has a composition ratio of nitrogen (N) higher than silicon (Si), and
wherein the first region is adjacent to the body layer, and the second region is further from the body layer than the first region,
wherein a characteristic of the neuromorphic synaptic device is adjusted and optimized, depending on positions of the first and second regions having the different characteristics,
However, Ganguly teaches:
wherein the charge storage layer includes a silicon nitride and:
a first region of a first silicon nitride composition ( Ganguly, [0022], In detailed embodiments, the second trapping sub-layer is engineered to provide a low charge trap generation and minimize endurance degradation of the device. In some embodiments, the second trapping sub-layer has a high charge trap density for improved memory window ) having a first characteristic and a second region of a second silicon nitride composition ( Ganguly, [0014], Nitrogen-rich nitride can produce satisfactory retention but enhanced endurance memory window degradation ) having a second different characteristic, wherein a composition ratio of silicon (Si) and nitrogen (N) is different for the first and second silicon nitride compositions, the first silicon nitride composition ( Ganguly [0022], the second trapping sub-layer comprises a silicon-rich silicon nitride compound containing more silicon on a atomic percentage basis than is present in stoichiometric silicon nitride ) has a composition ratio of silicon (Si) higher than nitrogen (N), the second silicon nitride composition ( Ganguly, [0021], the first trapping sub-layer comprises a nitrogen-rich silicon nitride compound containing about the same as or more nitrogen on an atomic percentage basis than is present in stoichiometric silicon nitride ) has a composition ratio of nitrogen (N) higher than silicon (Si), and
wherein the first region is adjacent to the body layer, and the second region is further from the body layer than the first region ( Ganguly, [0023], In one or more embodiments, the charge trapping layer is a graded layer having a variable composition and a thickness in the range of about 1 nm to 20 nm. The charge trapping layer comprises nitrogen-rich SixNy adjacent to the tunnel layer and silicon-rich SixNy adjacent to the interface region ),
wherein a characteristic of the neuromorphic synaptic device is adjusted and optimized, depending on positions of the first and second regions having the different characteristics ( Ganguly, [0050], By utilizing the graded charge trapping layer 18, the abruptness of the interface is reduced, the scattering is reduced or even avoided, and performance of the device 10 is improved ),
Kim and Ganguly are both considered to be analogous to the claimed invention because they are forming a flash memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified A ( asymmetric Schottky barrier ), to incorporate the teachings of Ganguly ( multi-Layer charge trap silicon nitride/oxynitride layer engineering with interface region control ), to implement the charge trap flash memory device having asymmetric Schottky barrier and multi-Layer charge trap silicon nitride/oxynitride layer engineering with interface region control. Doing so would provide specific structures for charge trap flash memory device, and therefore to improve the performances ( i.e. “ tunneling currents ” and “ optimization for both retention and potentiation ” ).
Regarding ( Original ) claim 2, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the semiconductor substrate ( Kim, Drawing 1, substrate 10 ) and the body layer ( Kim, Drawing 1, area between channel 19 and substrate 10 ) include:
one of silicon (Si) ( Kim, page 7, The substrate 10 is a material used to form the source 12 and drain 14, and is mostly made of silicon (Si) ), silicon germanium (SiGe), strained Si, silicon carbide (SiC), and a group III-V compound semiconductor ( Kim, page 8, line 1, The source 12 and drain 14 regions can use an N(source)-P(channel)-N(drain) structure formed by injecting phosphorus (P) or arsenic (As) to form an N-type. In the case of a P-type, an N-type substrate 10 is used, and the source 12 and drain 14 regions can use a PNP structure formed by injecting boron (B) or BF2 to form a P-type ).
Regarding ( Original ) claim 3, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the semiconductor substrate ( Drawing 1, substrate 10 ) includes:
a barrier material layer including one of a buried oxide ( Kim, page 8, line 7, Although not shown, a SiO2 thin film can be deposited first on a p-type Si substrate 10 ), a buried n-well when the body layer is in a p type, a buried p-well when the body layer is in an n type, buried SiC, and buried SiGe ( Kim, page 8, The source 12 and drain 14 regions can use an N(source)-P(channel)-N(drain) structure formed by injecting phosphorus (P) or arsenic (As) to form an N-type. In the case of a P-type, an N-type substrate 10 is used, and the source 12 and drain 14 regions can use a PNP structure formed by injecting boron (B) or BF2 to form a P-type ).
Regarding ( Original ) claim 4, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the semiconductor substrate ( Kim, Drawing 1, substrate 10 ) functions as a back gate to apply a voltage bias ( Kim, page 10, line 11, the write voltage is 6 to 11V is applied between the control gate 18 (VG) and the substrate 10 Vsub. In this case, a voltage is generated in the inversion layer on the substrate 10 of the device ).
Regarding ( Original ) claim 5, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the body layer ( Kim, Drawing 1, area between channel 19 and substrate 10 ) is formed in one of structures of a planar-type body layer ( Kim, Drawing 1 ), a trench-type body layer, a fin-type body layer, a nanowire-type body layer, or nanosheet-type body layer.
Regarding ( Original ) claim 6, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches:, wherein the source and the drain ( Kim, Drawing 1, source 12 and drain 14 ) have one of a horizontal structure in which a channel is formed in a horizontal direction ( Kim, Drawing 1, channel 19 ) to the semiconductor substrate ( Kim, Drawing 1, substrate 10 ), as the source and the drain ( Kim, Drawing 1, source 12 and drain 14 ) are formed at the left side and the right side of the body layer, and a vertical pillar structure in which the channel is formed in a direction perpendicular to the semiconductor substrate, as the source and the drain are formed at the upper side and the lower side of the body layer.
Regarding ( Original ) claim 7, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the source and the drain include:
one of n-type silicon, p-type silicon ( Kim, claim 1, forming a source region by injecting impurities into a semiconductor substrate ), and metal silicide ( Kim, claim 1, forming a drain region separated from the source region and having metal silicided on the semiconductor substrate ).
Regarding ( Original ) claim 8, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 7 on which this claim is dependent, Kim further teaches: wherein the source and the drain including the n-type silicon or the p-type silicon are formed through at least one of a diffusion process, a solid-phase diffusion process ( Kim, page 8, line 14, a method that implants solid or gaseous atoms by thermal diffusion ), an epitaxial growth process, a selective epitaxial growth process, an ion implantation process ( Kim, page 8, The doping process of these impurities can be performed using an ion implantation method that accelerates ionized atoms and forcibly implants them into silicon ), and the subsequent heat treatment process ( Kim, page 8, Afterwards, the impurities implanted into the silicon by the ion implantation method must go through a heat treatment process for electrical activation, and the vapor or solid-state thermal diffusion method also requires a heat treatment process for the diffusion of the impurities into the silicon ).
Regarding ( Currently Amended ) claim 9, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 7 on which this claim is dependent, Kim further teaches: wherein the source and the drain ( Kim, claim 1, using an asymmetric Schottky barrier characterized by different junction depths of the source region and the drain region ) including the n-type silicon or the p-type silicon are formed to have a specific doping concentration that forms to form the schottky junction ( Kim, claim 1, using an asymmetric Schottky barrier characterized by different junction depths of the source region and the drain region; Kim, page 1, flash memory device using asymmetric Schottky barrier; a high doping concentration is induced around the Schottky barrier of the drain; Kim’s disclosure inherently suggests varying doping concentration strategies at source and drain to optimize device characteristics. Therefore, forming a Schottky junction at a source with lighter doping concentration to facilitate tunneling currents would be inherent or obvious based on Kim’s disclosure ) with the contact metal.
Regarding ( Original ) claim 10, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the source and drain ( Kim, Drawing 1, source 12 and drain 14 ) including the metal silicide ( Kim, claim1, forming a drain region separated from the source region and having metal silicided on the semiconductor substrate ) includes:
one of tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadollium (Gd), turbul (Tb), cerium (Ce), platinum (Pt), iridium (Ir), and any combination thereof ( Kim, claim 4, The above metal is selected from the group consisting of cobalt, tungsten, nickel, palladium, platinum and titanium ).
Regarding ( Original ) claim 12, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the contact metal include:
one of aluminum (Al), molybdenum (Mo), chromium (Cr), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), gold (Au), tantalum (Ta), tungsten (W), silver (Ag), titanium nitride (TiN), tantalum nitride (TaN), and a combination thereof ( Kim, claim 12, The above metal is selected from the group consisting of cobalt, tungsten, nickel, palladium, platinum and titanium; page 8, Next, a metal film 32 doped with impurities such as As, for example, a titanium (Ti) film, is deposited on the PR and drain 14 regions; page 8, line 6 counted from bottom, Here, the metal may be cobalt, tungsten, nickel, palladium or platinum in addition to titanium ).
Regarding ( Original ) claim 13, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the gate insulating layer includes:
two oxide layers ( Kim, Drawing 1, tunnel oxide film 15 and gate oxide film 17 ) formed at opposite sides of the charge storage layer ( Kim, Drawing 1, floating gate 16 ); or
the charge storage layer ( Kim, Drawing 1, floating gate 16 ) and one oxide layer.
Regarding ( Currently Amended ) claim 14, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 13 on which this claim is dependent, Kim further teaches: wherein the charge storage layer ( Kim, Drawing 1, floating gate 16 ) includes:
one of poly-silicon, amorphous silicon, a metal oxide, the silicon nitride, a silicon nano-crystal material, a metal oxide nano-crystal material, and a combination thereof ( Kim, claim 7 of Kim, The above floating gate and the above control gate are characterized by being made of highly doped polycrystalline silicon or amorphous silicon ).
Regarding ( Original ) claim 16, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the oxide layer ( Kim, Drawing 1, gate oxide layer 17 or tunnel oxide film 15 ) include:
one of a silicon oxide ( Kim, claim 10 of Kim, The above tunnel oxide film and the above gate oxide film are composed of a silicon oxide film ), silicon oxynitride, an aluminum oxide, a hafnium oxide, a hafnium oxynitride, a zinc oxide, a zirconium oxide, and a combination thereof.
Regarding ( Original ) claim 17, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the gate includes:
one of n-type polysilicon, p-type polysilicon ( Kim, claim 7 of Kim, The above floating gate and the above control gate are characterized by being made of highly doped polycrystalline silicon or amorphous silicon ), aluminum (Al) ( Kim, page 9, line 6, The gate region is formed by etching. Then, aluminum (Al) is used to form the source (12), drain (14), and gate electrodes using a thermal evaporation method ), molybdenum (Mo), chromium (Cr), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), gold (Au), tantalum (Ta), tungsten (W), silver (Ag), titanium nitride (TiN), tantalum nitride (TaN), and a combination thereof ( Kim, claim 4, The above metal is selected from the group consisting of cobalt, tungsten, nickel, palladium, platinum and titanium ).
Regarding ( Original ) claim 19, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the neuromorphic synaptic device shows a synpatic weight and a conductance through an amount of charges stored in the charge storage layer ( Kim, Drawing 8 is a graph comparing the amount of charge stored in a floating gate 16 over time of an asymmetric SB NOR type flash memory device ), and potentiates ( Kim, Drawing 9, when the floating gate 16 is empty ('1'), … According to the operation of the NOR type flash memory device, data writing (program) is accomplished by injecting hot electrons from the channel 19 region adjacent to the drain 14 region into the floating gate 16 and capturing the electrons inside the floating gate 16 ) or depress ( Kim, Drawing 10, when electrons are stored ('0') in the floating gate 16, … The tunneling occurs into the silicon (Si) substrate 10. Therefore, the device is restored to the initial state '1' ) the synpatic weight and the conductance by changing the amount of charges stored in the charge storage layer ( Kim, Drawing 8 is a graph comparing the amount of charge stored in a floating gate 16 over time of an asymmetric SB NOR type flash memory device ) by applying a voltage signal to the gate ( Kim, page 10, Here, the hot electron injection method is a method of applying a high voltage to the control gate 18 electrode ).
Regarding ( Currently Amended ) Independent Claim 20, Kim teaches ( Kim, Drawing 1 ) a neuromorphic system comprising:
a neuromorphic synaptic device including a charge trap ( Kim, FIG. 8, charge stored in a floating gate 16 ) formed from a charge storage layer ( Kim, Drawing 1, gate 16 ) including a silicon nitride, a body layer ( Kim, Drawing 1, area between channel 19 and substrate 10 ) and a schottky junction ( Kim, page 1, flash memory device using asymmetric Schottky barrier ) formed between a source ( Kim, Drawing 1, source 12 and drain 14 ) and contact metal ( Kim, Drawing 3, metal film 32 ),
wherein the schottky junction ( Kim, page 1, flash memory device using asymmetric Schottky barrier ) is formed by a light doping concentration of the source ( Kim, Drawing 1, source 12 and drain 14 ) sufficient for a schottky tunneling current to flow ( Kim, page 10, an asymmetric SB NOR-type flash memory devices exhibit significantly higher current than conventional NOR-type flash memory devices and symmetric SB NOR-type flash memory devices ) during a transition region of the neuromorphic device ( Kim, claim 1, using an asymmetric Schottky barrier characterized by different junction depths of the source region and the drain region; Kim, page 1, flash memory device using asymmetric Schottky barrier; a high doping concentration is induced around the Schottky barrier of the drain; Kim’s disclosure inherently suggests varying doping concentration strategies at source and drain to optimize device characteristics. Therefore, forming a Schottky junction at a source with lighter doping concentration to facilitate tunneling currents would be inherent or obvious based on Kim’s disclosure ),
wherein the source and the drain form an asymmetric ( Kim, page 1, flash memory device using asymmetric Schottky barrier; Kim, page 10, an asymmetric SB NOR-type flash memory devices exhibit significantly higher current than conventional NOR-type flash memory devices and symmetric SB NOR-type flash memory devices ) structure in a concentration blocking a sneaky path of a neuron and a synapse array ( Kim, page 5, line 6 counted from bottom, In addition, the present invention induces a high doping concentration around the Schottky barrier of the drain, thereby increasing the hot electron effect, thereby improving the NOR performance; Kim, page 11, As in this embodiment, when a Schottky barrier is used in the drain, a high doping concentration is induced around the Schottky barrier, which increases the hot electron effect, thereby improving the write speed of the NOR flash structure ).
Kim fails to disclose:
wherein the charge storage layer including a silicon nitride includes:
a first region of a first silicon nitride composition having a first characteristic and a second region of a second silicon nitride composition having a second different characteristic, wherein a composition ratio of silicon (Si) and nitrogen (N) is different for the first and second silicon nitride compositions, the first silicon nitride composition has a composition ratio of silicon (Si) higher than nitrogen (N), the second silicon nitride composition has a composition ratio of nitrogen (N) higher than silicon (Si), and
wherein the first region is adjacent to the body layer, and the second region is further from the body layer than the first region,
wherein a characteristic of the neuromorphic synaptic device is adjusted and optimized, depending on positions of the first and second regions having the different characteristics,
However, Ganguly teaches:
wherein the charge storage layer includes a silicon nitride and:
a first region of a first silicon nitride composition ( Ganguly, [0022], In detailed embodiments, the second trapping sub-layer is engineered to provide a low charge trap generation and minimize endurance degradation of the device. In some embodiments, the second trapping sub-layer has a high charge trap density for improved memory window ) having a first characteristic and a second region of a second silicon nitride composition ( Ganguly, [0014], Nitrogen-rich nitride can produce satisfactory retention but enhanced endurance memory window degradation ) having a second different characteristic, wherein a composition ratio of silicon (Si) and nitrogen (N) is different for the first and second silicon nitride compositions, the first silicon nitride composition ( Ganguly [0022], the second trapping sub-layer comprises a silicon-rich silicon nitride compound containing more silicon on a atomic percentage basis than is present in stoichiometric silicon nitride ) has a composition ratio of silicon (Si) higher than nitrogen (N), the second silicon nitride composition ( Ganguly, [0021], the first trapping sub-layer comprises a nitrogen-rich silicon nitride compound containing about the same as or more nitrogen on an atomic percentage basis than is present in stoichiometric silicon nitride ) has a composition ratio of nitrogen (N) higher than silicon (Si), and
wherein the first region is adjacent to the body layer, and the second region is further from the body layer than the first region ( Ganguly, [0023], In one or more embodiments, the charge trapping layer is a graded layer having a variable composition and a thickness in the range of about 1 nm to 20 nm. The charge trapping layer comprises nitrogen-rich SixNy adjacent to the tunnel layer and silicon-rich SixNy adjacent to the interface region ),
wherein a characteristic of the neuromorphic synaptic device is adjusted and optimized, depending on positions of the first and second regions having the different characteristics ( Ganguly, [0050], By utilizing the graded charge trapping layer 18, the abruptness of the interface is reduced, the scattering is reduced or even avoided, and performance of the device 10 is improved ),
Kim and Ganguly are both considered to be analogous to the claimed invention because they are forming flash memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified A ( asymmetric Schottky barrier ), to incorporate the teachings of Ganguly ( multi-Layer charge trap silicon nitride/oxynitride layer engineering with interface region control ), to implement the charge trap flash memory device having asymmetric Schottky barrier and multi-Layer charge trap silicon nitride/oxynitride layer engineering with interface region control. Doing so would provide specific structures for charge trap flash memory device, and therefore to improve the performances ( i.e. “ tunneling currents ” and “ optimization for both retention and potentiation ” ).
Regarding ( Currently Amended ) Independent Claim 21, Kim teaches ( Kim, Drawing 1 ) a neuromorphic system comprising:
a body layer ( Kim, Drawing 1, area between channel 19 and substrate 10 ) formed on a semiconductor substrate ( Kim, Drawing 1, substrate 10 );
a source and a drain ( Kim, Drawing 1, source 12 and drain 14 ) formed at a left side and a right side or an upper side and a lower side of the body layer;
a contact metal ( Kim, Drawing 3, metal film 32 ) configured to form a schottky junction ( Kim, page 1, flash memory device using asymmetric Schottky barrier ) with the source, wherein the source has a light doping concentration sufficient for a schottky tunneling current to flow ( Kim, page 10, an asymmetric SB NOR-type flash memory devices exhibit significantly higher current than conventional NOR-type flash memory devices and symmetric SB NOR-type flash memory devices ) during a transition region of the neuromorphic device, the contact metal ( Kim, Drawing 3, metal film 32 ) in contact with the source and the drain ( Kim, claim 1, using an asymmetric Schottky barrier characterized by different junction depths of the source region and the drain region; Kim, page 1, flash memory device using asymmetric Schottky barrier; a high doping concentration is induced around the Schottky barrier of the drain; Kim’s disclosure inherently suggests varying doping concentration strategies at source and drain to optimize device characteristics. Therefore, forming a Schottky junction at a source with lighter doping concentration to facilitate tunneling currents would be inherent or obvious based on Kim’s disclosure );
a gate insulating layer ( Kim, Drawing 1, gate oxide layer 17 + gate 16 + tunnel oxide film 15 ) formed on the body layer and including an oxide layer ( Kim, Drawing 1, gate oxide layer 17 or tunnel oxide film 15 ) and a charge storage layer ( Kim, Drawing 1, gate 16 ); and
a gate ( Kim, Drawing 1, control gate 18 ) formed on the gate insulating layer ( Kim, Drawing 1, gate oxide layer 17 + gate 16 + tunnel oxide film 15 ); and
wherein the source and the drain form an asymmetric ( Kim, page 1, flash memory device using asymmetric Schottky barrier; Kim, page 10, an asymmetric SB NOR-type flash memory devices exhibit significantly higher current than conventional NOR-type flash memory devices and symmetric SB NOR-type flash memory devices ) structure in a concentration blocking a sneaky path of a neuron and a synapse array ( Kim, page 5, line 6 counted from bottom, In addition, the present invention induces a high doping concentration around the Schottky barrier of the drain, thereby increasing the hot electron effect, thereby improving the NOR performance; Kim, page 11, As in this embodiment, when a Schottky barrier is used in the drain, a high doping concentration is induced around the Schottky barrier, which increases the hot electron effect, thereby improving the write speed of the NOR flash structure ).
wherein the source and the drain have an asymmetric structure ( Kim, Caim1, using an asymmetric Schottky barrier characterized by different junction depths of the source region and the drain region ) in concentration gradient ( Kim, page 5, a high doping concentration around the Schottky barrier of the drain ) in concentration gradient to block a sneaky path of a neuron and a synapse array.
Kim fails to disclose:
wherein the charge storage layer includes a silicon nitride and:
a first region of a first silicon nitride composition having a first characteristic and a second region of a second silicon nitride composition having a second different characteristic, wherein a composition ratio of silicon (Si) and nitrogen (N) is different for the first and second silicon nitride compositions, the first silicon nitride composition has a composition ratio of silicon (Si) higher than nitrogen (N), the second silicon nitride composition has a composition ratio of nitrogen (N) higher than silicon (Si), and
wherein the first region is adjacent to the body layer, and the second region is further from the body layer than the first region,
wherein a characteristic of the neuromorphic synaptic device is adjusted and optimized, depending on positions of the first and second regions having the different characteristics,
However, Ganguly teaches:
wherein the charge storage layer includes a silicon nitride and:
a first region of a first silicon nitride composition ( Ganguly, [0022], In detailed embodiments, the second trapping sub-layer is engineered to provide a low charge trap generation and minimize endurance degradation of the device. In some embodiments, the second trapping sub-layer has a high charge trap density for improved memory window ) having a first characteristic and a second region of a second silicon nitride composition ( Ganguly, [0014], Nitrogen-rich nitride can produce satisfactory retention but enhanced endurance memory window degradation ) having a second different characteristic, wherein a composition ratio of silicon (Si) and nitrogen (N) is different for the first and second silicon nitride compositions, the first silicon nitride composition ( Ganguly [0022], the second trapping sub-layer comprises a silicon-rich silicon nitride compound containing more silicon on a atomic percentage basis than is present in stoichiometric silicon nitride ) has a composition ratio of silicon (Si) higher than nitrogen (N), the second silicon nitride composition ( Ganguly, [0021], the first trapping sub-layer comprises a nitrogen-rich silicon nitride compound containing about the same as or more nitrogen on an atomic percentage basis than is present in stoichiometric silicon nitride ) has a composition ratio of nitrogen (N) higher than silicon (Si), and
wherein the first region is adjacent to the body layer, and the second region is further from the body layer than the first region ( Ganguly, [0023], In one or more embodiments, the charge trapping layer is a graded layer having a variable composition and a thickness in the range of about 1 nm to 20 nm. The charge trapping layer comprises nitrogen-rich SixNy adjacent to the tunnel layer and silicon-rich SixNy adjacent to the interface region ),
wherein a characteristic of the neuromorphic synaptic device is adjusted and optimized, depending on positions of the first and second regions having the different characteristics ( Ganguly, [0050], By utilizing the graded charge trapping layer 18, the abruptness of the interface is reduced, the scattering is reduced or even avoided, and performance of the device 10 is improved ),
Kim and Ganguly are both considered to be analogous to the claimed invention because they are forming flash memory device. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified A ( asymmetric Schottky barrier ), to incorporate the teachings of Ganguly ( multi-Layer charge trap silicon nitride/oxynitride layer engineering with interface region control ), to implement the charge trap flash memory device having asymmetric Schottky barrier and multi-Layer charge trap silicon nitride/oxynitride layer engineering with interface region control. Doing so would provide specific structures for charge trap flash memory device, and therefore to improve the performances ( i.e. “ tunneling currents ” and “ optimization for both retention and potentiation ” ).
( Original ) Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Ganguly, as applied to claim 1 above, and further in view of Ye ( U: P. Ye, T. Ernst and M. V. Khare, "The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore's Law," in IEEE Spectrum, vol. 56, no. 8, pp. 30-35, Aug. 2019 ), hereinafter Ye.
Regarding ( Original ) claim 18, Kim and Ganguly teach the neuromorphic synaptic device as claimed in claim 1 on which this claim is dependent, Kim further teaches: wherein the gate ( Kim, Drawing 1, control gate 18 ) is formed on the gate insulating layer.
Kim and Ganguly fail to teach the gate has one of a structure to surround the body layer in a form of a fin, a gate-all-around structure to surround an entire portion of the body layer, and a multiple-gate structure.
However, Ye teaches the gate has one of a structure to surround the body layer in a form of a fin ( Ye, page 4, the figure of FinFET ), a gate-all-around structure to surround an entire portion of the body layer, and a multiple-gate structure. ( Ye, page 4, the figure of Stacked nanosheet FET ).
Kim and Ganguly and Ye are all considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim ( Drawing 1, control gate 18 ) to incorporate the teachings of Ye ( page 4, the figure of FinFET, the figure of Stacked nanosheet FET ), to make the gate have one of a structure to surround the body layer in a form of a fin, a gate-all-around structure to surround an entire portion of the body layer, and a multiple-gate structure. Doing so would have a better control on the leakage of current.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 12-14, and 16-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments have been considered. However, the claim limitations are met by the prior art as applied above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817