DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-3, 6, 7, 21-23, 25-33 are pending.
Claims 1, 2, 7, 21 and 25 are amended.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claims 1 and 21. Claim 1 recites the limitation “the apparatus further comprises a plurality of cell contact plugs arranged in the memory cell array region and coupled to bottom parts of the respective cell capacitors” seventh paragraph of the claim language.
Claim 21 is objected to for the same analogous reason as claim 1 above.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-3, 6, 7, 21-23, 25-33 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1 and 21. Claim 1 recites the limitation “bottom parts of the respective cell capacitors” in the seventh paragraph of the claim language.
Applicant does not have written support in the originally filed specifications for bottom parts of the respective cell capacitors.
Claim 1 recites the limitation “a corresponding cell plug of the plurality of cell contact plugs” in the eighth paragraph of the claim language.
Applicant does not have written support in the originally filed specifications for a corresponding cell plug of the plurality of cell contact plugs.
Claim 21 rejected for the same analogous reasons as claim 1 above.
Claims 2, 3, 6, 7, 22-23, 25-33 are rejected for dependence upon a 112(a) rejected instance claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 6, 7, 21-23, 25-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1 and 21. Claim 1 recites the limitation “bottom parts of the respective cell capacitors” in the seventh paragraph of the claim language.
It is unclear to the examiner as to what is encompassed by bottom parts of the respective cell capacitors.
For the purpose of examination and compact prosecution, examiner shall interpret bottom parts to be second electrode as supported by applicant’s originally filed specification in ([0008]).
Claim 1 also recites the limitation “a corresponding cell plug of the plurality of cell contact plugs” in the eighth paragraph of the claim language.
It is unclear to the examiner as to what is encompassed by a corresponding cell plug of the plurality of cell contact plugs.
For the purpose of examination and compact prosecution, examiner shall interpret a corresponding cell plug of the plurality of cell contact plugs to be a corresponding cell contact plug of the plurality of cell contact plugs
Claim 21 rejected for the same analogous reasons as claim 1 above.
Claims 2, 3, 6, 7, 22-23, 25-33 are rejected for dependence upon a 112(a) rejected instance claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6, 7, 26, 27, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (U.S. 2021/0210492), and further in view of Nishi (U.S. 2011/0291239).
Regarding claim 1. Han et al discloses an apparatus comprising: a plurality of cell capacitors (FIG. 13; [ABSTRACT]; [0042]) arranged in a memory cell array region (FIG. 13, item A; [0034]), each of the plurality of cell capacitors (FIG. 13; [ABSTRACT]; [0042]) having a first electrode (FIG. 13, item 32), a second electrode (FIG. 13, item BE) and an insulating film (FIG. 13, item DL) between ([0043], i.e. a dielectric layer DL) the first (FIG. 13, item 32) and second (FIG. 13, item BE) electrodes;
an embedding material (FIG. 13, item 34) configured to embed ([0045]) the plurality of cell capacitors therein (FIG. 13; [ABSTRACT]; [0042]), the embedding material (FIG. 13, item 34) being electrically connected ([0045]) in common to the first electrodes (FIG. 13, item 32) of the plurality of cell capacitors (FIG. 13; [ABSTRACT]; [0042]), wherein the embedding material (FIG. 13, item 34) is not included in the first electrode (FIG. 13, item 34 is not included in item 32) or the second electrode (FIG.13, item 34 is not included in item BE) of each of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]); and
a conductive film (FIG. 13, item MP) formed on the embedding material (FIG. 13, item 34), wherein the conductive film (FIG. 13, item MP) is limited to an upper surface (FIG. 13, item 44) of the embedding material (FIG. 13, item 34), and covers an entirety of the upper surface (FIG. 13, item 44) of the embedding material (FIG. 13, item 34); and
an insulating member (FIG. 13, items 40 and 48; Examiner makes note that FIG. 19E, item 40 also shows an insulating member) in a peripheral circuit region (FIG. 13, item B) adjacent to the memory cell array region (FIG. 13, item A)
wherein an entire side surface (FIG. 13, item 46) of the embedding member (FIG. 13, item 34) is not covered with the conductive film (FIG. 13, item MP) is in contact ([0047]) with the insulating member (FIG. 13, item 40) and is coplanar with a side surface (FIG. 13, item 46) of the conductive film (FIG. 13, item MP)
the insulating member (FIG. 13, items 40 and 48) covers (FIG. 13, items 48 and 40 covers item MP) the conductive film (FIG. 13, item MP) and the entire side surface (FIG. 13, item 46, item 40 covers item 46 of item 34) of the embedding material (FIG. 13, item 34),
the apparatus further comprises a plurality of cell contact plugs (FIG. 13, item LP) arranged in the memory cell array region (FIG. 13, item A) and coupled to bottom parts (FIG. 13, item BE) of the respective cell capacitors (FIG. 13; [ABSTRACT]; [0042]), and each of the plurality of cell contact plugs (FIG. 13, item LP) is electrically connected to the second electrode (FIG. 13, item BE) of each of the respective cell capacitors (FIG. 13; [ABSTRACT]; [0042]),
the plurality of cell capacitors (FIG. 13; [ABSTRACT]; [0042]) extend in a vertical direction (FIG. 13, item D1),
upper parts (FIG. 13, item SL2) and central parts (FIG. 13, item SL1) of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]) are supported ([0044]) by a first beam insulating film (FIG. 13, item SL2) and a second beam insulating film (FIG. 13, item SL1), respectively.
Han et al fails to be explicitly disclose the plurality of cell capacitors extend in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and
the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively.
However, Nishi teaches the plurality of cell capacitors (FIG. 1A, item 19) extend in a tapered form ([0058]-[0059]), each having a bottom surface (FIG. 1A, item 16) narrower ([0058], i.e. As shown in FIGS. 1A and 1B, the outer diameter D1 of the large-diameter part 12b is larger than the outer diameter D3 of a bottom face of the lower electrode 16) than a top surface and coupled to a corresponding cell plug (as best understood by the 112(b) above; FIG. 1A, item 12) of the plurality of cell contact plugs (FIG. 1A, item 12), and the bottom surface (FIG. 1A, item 15) of each of the cell capacitors (FIG. 1A, item 19) is narrower ([0058]) than a top surface (FIG. 1A, item 12e) of the corresponding cell contact plug (FIG. 1A, item 12) in a horizontal direction, and
the cell capacitors (FIG. 1A, item 19) in the tapered form ([0058]-[0059]) are supported by a beam insulating film (FIG. 1A, item 13), respectively.
Since Han et al and Nishi teach cell capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the apparatus as disclosed to modify Han et al with the teachings of the plurality of cell capacitors extend in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively as disclosed by Nishi. The use of the outer diameter D1 of the large-diameter part is larger than the outer diameter D3 of a bottom face of the lower electrode in Nishi provides for reducing misalignment problems (Nishi, [0058]).
Regarding claim 2. Han et al and Nishi discloses all the limitations of the apparatus of claim 1 above.
Han et al further discloses where the insulating film (FIG. 13, item DL) is configured to electrically disconnect ([0043], i.e. a dielectric layer DL) the first (FIG. 13, item 32) and second (FIG. 13, item BE) electrodes, and
A top surface of the insulating member (FIG. 13, item 48) is located higher ([0052]) than top surfaces of the conductive film (FIG. 13, item MP) and the embedding material (FIG. 13, item 34).
Regarding claim 3. Han et al and Nishi discloses all the limitations of the apparatus of claim 2 above.
Han et al further discloses further comprising: a wiring pattern (FIG. 13, item 16) formed in the peripheral circuit region (FIG. 13, item B) adjacent to the memory cell array region (FIG. 13, item A); and a contact plug (FIG. 13, item 56) electrically connected ([0054]) to the wiring pattern (FIG. 13, item 16) so as to penetrate ([0054]) the insulating member (FIG.13, item 48 and 40).
Regarding claim 6. Han et al and Nishi discloses all the limitations of the apparatus of claim 1 above.
Han et al further discloses wherein the side surface (FIG. 13, item 46) of the embedding material (FIG. 13, item 34) is substantially flat ([0113]).
Regarding claim 7. Han et al and Nishi discloses all the limitations of the apparatus of claim 6 above.
Han et al further discloses wherein the first beam insulating film (FIG. 13, item SL2) and the second beam insulating film (FIG. 13, item SL1) extend ([0044]-[0045]) in a direction substantially perpendicular ([0044]-[0045]) to the cell capacitors (FIG. 13; [ABSTRACT]; [0042])
wherein the first beam insulating film (FIG. 13, item SL2) and the second beam insulation film (FIG. 13, item SL1) projects ([0044]-[0045]) toward the side surface (FIG. 13, item 46) of the embedding material (FIG. 13, item 34) from ones of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]) located at an end ([0044]-[0045]) of the memory cell array region (FIG. 13, item A).
Regarding claim 26. Han et al and Nishi discloses all the limitations of the apparatus of claim 1 above.
Han et al further discloses wherein the conductive film (FIG. 13, item MP) is not included in the first electrode (FIG. 13, item MP is not included in item 32) or the second electrode (FIG. 13, item MP is not included in item BE) of each of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]).
Regarding claim 27. Han et al and Nishi discloses all the limitations of the apparatus of claim 1 above.
Han et al further discloses wherein a material ([0048], i.e. the conductive pad MP may be formed of or include tungsten (W)) of the conductive film (FIG. 13, item MP) is different from the embedding material (FIG. 13, item 34; [0048], i.e. silicon germanium layer 34).
Regarding claim 29. Han et al and Nishi discloses all the limitations of the apparatus of claim 1 above.
Han et al further discloses wherein the conductive film includes tungsten ([0048], i.e. the conductive pad MP may be formed of or include tungsten (W)).
Claims 1 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki (U.S. 2015/0060970), Han et al (U.S. 2021/0210492), and Nishi (U.S. 2011/0291239).
Regarding claim 1. Sasaki discloses an apparatus comprising: a plurality of cell capacitors ([0036], i.e. cell capacitors; FIG. 1B, item 86, 87, 88 of item C) arranged in a memory cell array region (FIG. 1A, item MA), each of the plurality of cell capacitors (FIG. 1B, item 86, 87, 88 of item C; [0040], i.e. The capacitor insulating film 87 is a thin insulating film that covers the whole of the surface of each of the lower electrodes 86 corresponding to the inside of the bottomed cylinder. The upper electrode 88 is a conductor formed to face the corresponding lower electrodes 86 via the capacitor insulating film 87. That is, each of the cell capacitors C has a configuration in which the lower electrode and the upper electrode 88 face each other with an intervention of the capacitor insulating film 87) having a first electrode (FIG. 1B, item 88; [0086], i.e. upper electrode 88 (third conductive layer) being a titanium nitride film), a second electrode (FIG. 1B, item 86) and an insulating film (FIG. 1B, item 87) between the first (FIG. 1B, item 88) and second (FIG. 1B, item 86) electrodes;
an embedded material (FIG. 1B, item 89; [0086], i.e. the upper electrode 89 being a polysilicon film) configured to embed ([0040], i.e. The upper electrode 89 is a conductor formed to fill hollow areas of the upper electrode 88) the plurality of cell capacitors therein (FIG. 1B, item 86, 87, 88 of item C), the embedding material (FIG. 1B, item 89) being electrically connected ([0036]) in common to the first electrodes (FIG. 1B, item 88) of the plurality of cell capacitors (FIG. 1B, item 86, 87, 88 of item C), wherein the embedding material ([0086], i.e. the upper electrode 89 being a polysilicon film) is not included in the first electrode (FIG. 1B, item 89 is not included in item 88) or the second electrode (FIG. 1B, item 89 is not included in item 86) of each of the cell capacitors (FIG. 1B, item 86, 87, 88 of item C); and
a conductive film (FIG. 1B, item 90) formed on the embedding material (FIG. 1B, item 89),
an insulating member (FIG. 1A-1B, item 92) in a peripheral circuit region (FIG. 1A, item PA; FIG. 1B, item KP) adjacent to the memory cell array region (FIG. 1A, item MA; FIG. 1B, item KM),
The insulating members covers the conductive film and a side surface of the embedding material.
Sasaki et al fails to explicitly disclose
wherein the conductive film is limited to an upper surface of the embedding material and covers an entirety of the upper surface of the embedding material.
wherein an entire side surface of the embedding member is not covered with the conductive film is in contact with the insulating member is coplanar with a side of the embedding material,
an insulating member covers an entire side surface of the embedding material
the apparatus further comprises a plurality of cell contact plugs arranged in the memory cell array region and coupled to bottom parts of the respective cell capacitors, and each of the plurality of cell contact plugs is electrically connected to the second electrode of each of the respective cell capacitors. the plurality of cell capacitors extend in a vertical direction in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and upper parts and central parts of the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively.
However, Han et al teaches
an insulating member (FIG. 13, items 40 and 48) covers the entire side surface (FIG. 13, item 46, item 40 covers item 46 of item 34) of the embedding material (FIG. 13, item 34),
wherein the conductive film (FIG. 13, item MP) is limited to an upper surface (FIG. 13, item 44) of the embedding material (FIG. 13, item 34),
wherein an entire side surface (FIG. 13, item 46) of the embedding member (FIG. 13, item 34) is not covered with the conductive film (FIG. 13, item MP) is in contact ([0047]) with the insulating member (FIG. 13, item 40) and is coplanar with a side surface (FIG. 13, item 46) of the conductive film (FIG. 13, item MP)
wherein an entire side surface (FIG. 13, item 46) of the embedding member (FIG. 13, item 34) is not covered with the conductive film (FIG. 13, item MP) is in contact ([0047]) with the insulating member (FIG. 13, item 40) and is coplanar with a side surface (FIG. 13, item 46) of the conductive film (FIG. 13, item MP)
the insulating member (FIG. 13, items 40 and 48) covers (FIG. 13, items 48 and 40 covers item MP) the conductive film (FIG. 13, item MP) and the entire side surface (FIG. 13, item 46, item 40 covers item 46 of item 34) of the embedding material (FIG. 13, item 34),
the apparatus further comprises a plurality of cell contact plugs (FIG. 13, item LP) arranged in the memory cell array region (FIG. 13, item A) and coupled to bottom parts (FIG. 13, item BE) of the respective cell capacitors (FIG. 13; [ABSTRACT]; [0042]), and each of the plurality of cell contact plugs (FIG. 13, item LP) is electrically connected to the second electrode (FIG. 13, item BE) of each of the respective cell capacitors (FIG. 13; [ABSTRACT]; [0042]),
the plurality of cell capacitors (FIG. 13; [ABSTRACT]; [0042]) extend in a vertical direction (FIG. 13, item D1),
upper parts (FIG. 13, item SL2) and central parts (FIG. 13, item SL1) of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]) are supported ([0044]) by a first beam insulating film (FIG. 13, item SL2) and a second beam insulating film (FIG. 13, item SL1), respectively.
Since Sasaki and Han et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the apparatus as disclosed to modify Sasaki with the teachings of wherein the conductive film is limited to an upper surface of the embedding material, wherein an entire side surface of the embedding member is not covered with the conductive film and is in contact with an insulating member in a peripheral circuit region adjacent to the memory cell array region as disclosed by Han et al. The use of third interlayered insulating layer may cover the side surface of the silicon germanium layer and may cover a portion of the top surface of the silicon germanium layer in Han et al provides for a reduced chip size and improved reliability (Han et al, [0004]).
Sasaki and Han et al fails to be explicitly disclose the plurality of cell capacitors extend in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and
the cell capacitors in the tapered form are supported by a beam insulating film, respectively.
However, Nishi teaches the plurality of cell capacitors (FIG. 1A, item 19) extend in a tapered form ([0058]-[0059]), each having a bottom surface (FIG. 1A, item 16) narrower ([0058], i.e. As shown in FIGS. 1A and 1B, the outer diameter D1 of the large-diameter part 12b is larger than the outer diameter D3 of a bottom face of the lower electrode 16) than a top surface and coupled to a corresponding cell plug (as best understood by the 112(b) above; FIG. 1A, item 12) of the plurality of cell contact plugs (FIG. 1A, item 12), and the bottom surface (FIG. 1A, item 15) of each of the cell capacitors (FIG. 1A, item 19) is narrower ([0058]) than a top surface (FIG. 1A, item 12e) of the corresponding cell contact plug (FIG. 1A, item 12) in a horizontal direction, and
the cell capacitors (FIG. 1A, item 19) in the tapered form ([0058]-[0059]) are supported by a beam insulating film (FIG. 1A, item 13), respectively.
Since Han et al and Nishi teach cell capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the apparatus as disclosed to modify Sasaki and Han et al with the teachings of the plurality of cell capacitors extend in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively as disclosed by Nishi. The use of the outer diameter D1 of the large-diameter part is larger than the outer diameter D3 of a bottom face of the lower electrode in Nishi provides for reducing misalignment problems (Nishi, [0058]).
Regarding claim 28. Sasaki and Han et al discloses all the limitations of the apparatus of claim 1 above.
Sasaki further discloses wherein the embedding material (FIG. 1B, item 89) includes polycrystalline silicon ([0086], i.e. 89 being a polysilicon film).
Claims 21-23, 25, 30-33 are rejected under 35 U.S.C. 103 as being unpatentable over Tung et al (U.S. 2021/0272961) and Han et al (U.S. 2021/0210492), and Kim et al (U.S. 2016/0020212)
Regarding claim 21. Tung et al discloses an apparatus (FIG. 12, comprising: a plurality of cell capacitors (FIG. 12, item 705a; [0106], i.e. capacitors 705a) arranged in a memory cell array region (FIG. 12, item 705a; [0106], i.e. capacitor array is completed, with the capacitors 705a formed on the central region I-1; [0061], i.e. refer to FIG. 1D and FIG. 12 collectively. In the embodiment, the semiconductor device is a dynamic random access memory (DRAM). The core region is a memory array region of the DRAM, the core component is a storage transistor, and the contact structure is a storage node contact connecting a capacitor (i.e. storage node) above), each of the plurality of cell capacitors (FIG. 12, item 705a) including a first electrode (FIG. 12, item 701), a second electrode (FIG. 12, item 703), and an insulating film (FIG. 12, item 702) between ([0105], i.e. a top electrode layer 703 is formed on the inner surface and outer surface of the capacitors dielectric layer 702, wherein the capacitors dielectric layer 702 covers the inner surface and outer surface of the cylindrical structures of the bottom electrode layer 701 to complete utilize the two opposite surfaces of bottom electrode layer 701 and form the capacitors with larger electrode area) the first electrode (FIG. 12, item 701) and the second electrodes (FIG. 12, item 703);
an embedding material (FIG. 12, item 704) including the plurality of cell capacitors (FIG. 12, item 705b) embedding therein ([0106]), wherein the embedding material (FIG. 12, item 704) is not included in the first electrode (FIG. 12, item 704 is not item 701) or the second electrode (FIG. 12, item 704 is not item 703) of each of the cell capacitors (FIG. 12, items 701-703); and
a side surface (FIG. 12, right side of item 704) of the first conductive member (FIG. 12, item 704),
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a material ([0106], i.e. top electrode filling layer 704 includes undoped polysilicon and boron-doped polysilicon) of the first conductive member (FIG. 12, item 704); and
a beam insulating film (FIG. 12, items 600, 601 and 602) configured to support ([0100], i.e. at least two middle supporting layers 601 may be stacked between the bottom supporting layer 600 and the top supporting layer 602 in order to provide better support for the bottom electrode layer) the plurality of cell capacitors (FIG. 12, item 705a); [0105], i.e. e top electrode layer 703 may constitute capacitors with the capacitor dielectric layer 702 and the bottom electrode layer 701 either inside or outside the corresponding cylindrical structures),
the plurality of cell capacitors extending in a direction perpendicular to the beam insulating film ([0101], i.e. The capacitor holes 700a, 700b pass sequentially through the top supporting layer 602, the second sacrificial layer 612, the middle supporting layer 601, the first sacrificial layer 611 and the bottom supporting layer 600),
wherein the beam insulating film (FIG. 12, items 600, 601 and 602; [0101], i.e. the supporting layer on the core region I) across the plurality of cell capacitors (FIG. 12, item 705a) in a lateral direction ([0105], i.e. top electrode layer 703 may constitute capacitors with the capacitor dielectric layer 702 and the bottom electrode layer 701 either inside or outside the corresponding cylindrical structures. In addition, since the presence of lateral supporting layer (i.e. the middle supporting layer 601 and the top supporting layer 602; [0101], i.e. the bottom supporting layer 600 remains on the peripheral region II to protect devices in the peripheral region II in later process of forming the capacitors) from the memory cell region (FIG. 12, item I; [0062], i.e. core region I; [0074], i.e. each contact plug in the central region I-1 of core region I connects a capacitor above (as 705a shown in FIG. 12)) toward ([0101]) a peripheral circuit region (FIG. 12, item II; [0062], i.e. peripheral region II) and projects in the lateral direction toward the side surface (annotated FIG. 12, side surface of item 704) of the embedding material (FIG. 12, item 704) from ones of the cell capacitors (FIG. 12, item 705a) located at an end of the memory cell array region (FIG. 12, item 705a; [0106], i.e. capacitor array is completed, with the capacitors 705a formed on the central region I-1; [0105], i.e. since the presence of lateral supporting layer (i.e. the middle supporting layer 601 and the top supporting layer 602) on the edge region of core region I (i.e. the border region of an array of the capacitor holes), the capacitor dielectric layer 702 and the top electrode layer 703 are provided with uneven sidewall structures. The uneven sidewall structure corresponds to the middle supporting layer 601 and the top supporting layer 602 outside the cylindrical structures of bottom electrode layer 701, thus the portion of top electrode layer 703 on the edge region of core region I (i.e. the border region of the array of capacitor holes) would protrude away from the bottom electrode layer 701 in a direction corresponding to the middle supporting layer 601) .
Tung et al fails to explicitly disclose
a conductive film formed on the embedding material wherein the conductive film is limited to an upper surface of the embedding material and covers an entirety of the upper surface of the embedding surface,
an insulating member in a peripheral region adjacent to the memory cell array region,
wherein an entire side surface of the embedding member is not covered with the conductive film is in contact with the insulating member and is coplanar with a side surface of the conductive film,
wherein the beam insulating film extends across the plurality of cell capacitors in a lateral direction from the memory cell region.
the apparatus further comprises a plurality of cell contact plugs arranged in the memory cell array region and coupled to bottom parts of the respective cell capacitors, and each of the plurality of cell contact plugs is electrically connected to the second electrode of each of the respective cell capacitors. the plurality of cell capacitors extend in a vertical direction in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and upper parts and central parts of the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively.
However, Han et al teaches a conductive film (FIG. 13, item MP) formed on the embedding material (FIG. 13, item 34), wherein the conductive film (FIG. 13, item MP) is limited to an upper surface (FIG. 13, item 44) of the embedding material (FIG. 13, item 34), and covers an entirety of the upper surface (FIG. 13, item 44) of the embedding material (FIG. 13, item 34); and
an insulating member (FIG. 13, items 40 and 48; Examiner makes note that FIG. 19E, item 40 also shows an insulating member) in a peripheral circuit region (FIG. 13, item B) adjacent to the memory cell array region (FIG. 13, item A)
wherein an entire side surface (FIG. 13, item 46) of the embedding member (FIG. 13, item 34) is not covered with the conductive film (FIG. 13, item MP) is in contact ([0047]) with the insulating member (FIG. 13, item 40) and is coplanar with a side surface (FIG. 13, item 46) of the conductive film (FIG. 13, item MP)
the insulating member (FIG. 13, items 40 and 48) covers (FIG. 13, items 48 and 40 covers item MP) the conductive film (FIG. 13, item MP) and the entire side surface (FIG. 13, item 46, item 40 covers item 46 of item 34) of the embedding material (FIG. 13, item 34),
the apparatus further comprises a plurality of cell contact plugs (FIG. 13, item LP) arranged in the memory cell array region (FIG. 13, item A) and coupled to bottom parts (FIG. 13, item BE) of the respective cell capacitors (FIG. 13; [ABSTRACT]; [0042]), and each of the plurality of cell contact plugs (FIG. 13, item LP) is electrically connected to the second electrode (FIG. 13, item BE) of each of the respective cell capacitors (FIG. 13; [ABSTRACT]; [0042]),
the plurality of cell capacitors (FIG. 13; [ABSTRACT]; [0042]) extend in a vertical direction (FIG. 13, item D1),
upper parts (FIG. 13, item SL2) and central parts (FIG. 13, item SL1) of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]) are supported ([0044]) by a first beam insulating film (FIG. 13, item SL2) and a second beam insulating film (FIG. 13, item SL1), respectively.
Since Sasaki and Han et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the apparatus as disclosed to modify Sasaki with the teachings of a conductive film formed on the embedding material wherein the conductive film is limited to an upper surface of the embedding material and covers an entirety of the upper surface of the embedding surface, an insulating member in a peripheral region adjacent to the memory cell array region, wherein an entire side surface of the embedding member is not covered with the conductive film is in contact with the insulating member and is coplanar with a side surface of the conductive film, wherein the beam insulating film extends across the plurality of cell capacitors in a lateral direction from the memory cell region as disclosed by Han et al. The use of third interlayered insulating layer may cover the side surface of the silicon germanium layer and may cover a portion of the top surface of the silicon germanium layer in Han et al provides for a reduced chip size and improved reliability (Han et al, [0004]).
Tung et al and Han et al fail to explicitly disclose wherein the beam insulating film extends across the plurality of cell capacitors in a lateral direction from the memory cell region.
However, Kim et al teaches wherein the beam insulating film (FIG. 1A-B, 2A-2E, items 124, 126, and 127; [0069], i.e. In an exemplary embodiment, as shown in FIG. 1B, the support pattern structure 127 may include first and second support patterns 124 and 126; [0030], the semiconductor device may have a capacitor support pattern including an oxide, which may have a compact structure of layer; ) extends across (FIG. 1A and 1B, item Y direction and item X direction) the plurality of cell capacitors (FIG. 1B, items 122; [0068], i.e. when the electrode structure 122 is a lower electrode of a capacitor in a DRAM device, a dielectric layer 134 (refer to FIGS. 2A to 2E) and an upper electrode 136, 138, 140, or 142 (refer to FIGS. 2A to 2E) may be formed on the electrode structure 122) in a lateral direction (FIG. 1A and 1B, item Y direction and item X direction) from the memory cell region (FIG. 1A and 1B, 2A-E).
Since Tung et al, Han et al, and Kim et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the apparatus as disclosed to modify Tung et al and Han et al with the teachings of the wherein the beam insulating film extends across the plurality of cell capacitors in a lateral direction from the memory cell region as disclosed by Kim et al. The use of the semiconductor device may have a capacitor support pattern including an oxide, which may have a compact structure of layer in Kim et al provides for enhanced leakage current characteristics (Kim et al, [0030]).
Tung et al, Han et al, and Kim et al fails to be explicitly disclose the plurality of cell capacitors extend in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and
the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively.
However, Nishi teaches the plurality of cell capacitors (FIG. 1A, item 19) extend in a tapered form ([0058]-[0059]), each having a bottom surface (FIG. 1A, item 16) narrower ([0058], i.e. As shown in FIGS. 1A and 1B, the outer diameter D1 of the large-diameter part 12b is larger than the outer diameter D3 of a bottom face of the lower electrode 16) than a top surface and coupled to a corresponding cell plug (as best understood by the 112(b) above; FIG. 1A, item 12) of the plurality of cell contact plugs (FIG. 1A, item 12), and the bottom surface (FIG. 1A, item 15) of each of the cell capacitors (FIG. 1A, item 19) is narrower ([0058]) than a top surface (FIG. 1A, item 12e) of the corresponding cell contact plug (FIG. 1A, item 12) in a horizontal direction, and
the cell capacitors (FIG. 1A, item 19) in the tapered form ([0058]-[0059]) are supported by a beam insulating film (FIG. 1A, item 13), respectively.
Since Tung et al, Han et al, Kim et al and Nishi teach cell capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the apparatus as disclosed to modify Tung et al, Han et al, and Kim et al with the teachings of the plurality of cell capacitors extend in a tapered form, each having a bottom surface narrower than a top surface and coupled to a corresponding cell plug of the plurality of cell contact plugs, and the bottom surface of each of the cell capacitors is narrower than a top surface of the corresponding cell contact plug in a horizontal direction, and the cell capacitors in the tapered form are supported by a first beam insulating film and a second beam insulating film, respectively as disclosed by Nishi. The use of the outer diameter D1 of the large-diameter part is larger than the outer diameter D3 of a bottom face of the lower electrode in Nishi provides for reducing misalignment problems (Nishi, [0058]).
Regarding claim 22. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus according to claim 21 above.
Tung et al further discloses wherein the insulating film (FIG. 12, item 702)is configured to electrically disconnect ([0105], i.e. e top electrode layer 703 may constitute capacitors with the capacitor dielectric layer 702 and the bottom electrode layer 701 either inside or outside the corresponding cylindrical structures) the first electrode (FIG. 12, item 701) and the second electrode (FIG. 12, item 703).
Regarding claim 23. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus according to claim 21 above.
Tung et al further discloses wherein the embedding material (FIG. 12, item 704) is electrically connected ([0106]) in common to the first electrodes (FIG. 12, item 703) of the plurality of cell capacitors (FIG. 12, item 705a; [0106], i.e. capacitors 705a).
Regarding claim 25. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus according to claim 21 above.
Han et al further discloses wherein a top surface of the insulating member (FIG. 13, item 48) is located higher ([0052]) than top surfaces of the conductive film (FIG. 13, item MP) and the embedding material (FIG. 13, item 34).
Regarding claim 30. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus of claim 21 above.
Han et al further discloses wherein the conductive film (FIG. 13, item MP) is not included in the first electrode (FIG. 13, item MP is not included in item 32) or the second electrode (FIG. 13, item MP is not included in item BE) of each of the cell capacitors (FIG. 13; [ABSTRACT]; [0042]).
Regarding claim 31. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus of claim 21 above.
Tung et al disclose the embedding material ([0106], i.e. filling layer 704 includes undoped polysilicon and boron-doped polysilicon).
Han et al further discloses wherein a material ([0048], i.e. the conductive pad MP may be formed of or include tungsten (W)) of the conductive film (FIG. 13, item MP) is different from the embedding material (FIG. 13, item 34; [0048], i.e. silicon germanium layer 34).
Regarding claim 32. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus of claim 1 above.
Tung et al further discloses wherein the embedding material (FIG. 12, item 704) includes polycrystalline silicon ([0106], i.e. filling layer 704 includes undoped polysilicon and boron-doped polysilicon).
Regarding claim 33. Tung et al, Han et al, Kim et al, and Nishi discloses all the limitations of the apparatus of claim 21 above.
Han et al further discloses wherein the conductive film (FIG. 13, item MP) includes tungsten ([0048], i.e. the conductive pad MP may be formed of or include tungsten (W)).
Response to Arguments
Applicant's arguments filed October 2, 2025 have been fully considered but they are not persuasive.
Regarding rejection of claims 1 and 21.
On page 10 of applicant’s remarks, Applicant appears to be argue that Han fails to teach applicant’s amended claim 1.
Examiner respectfully agrees with applicant’s assertion of amended claim 1.
Examiner respectfully points out that Han et al and Nishi teaches applicant’s amended claim 1.
On page 10 of applicant’s remarks, Applicant appears to be argue that Sasaki and Han fails to teach applicant’s amended claim 1.
Examiner respectfully agrees with applicant’s assertion of amended claim 1.
Examiner respectfully points out that Sasaki, Han et al and Nishi teaches applicant’s amended claim 1.
On page 10 of applicant’s remarks, Applicant appears to be argue that Sasaki and Han fails to teach applicant’s amended claim 21.
Examiner respectfully agrees with applicant’s assertion of amended claim 21.
Examiner respectfully points out that Tung et al, Han et al, Kim et al, and Nishi teaches applicant’s amended claim 21.
Regarding rejection of claims 2, 3, 6, 7, 22, 23, and 25-30.
On page 10 of applicant’s remarks, Applicant appears to be argue claims 2,3, 6, 7, 22, and 25-30 are patentable due to their dependency and analogous reasoning as above.
Examiner respectfully points out that claims 2,3, 6, 7, 22, and 25-30 are rejected for the same analogous reasons as claims 1 and 21 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815