DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1; and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims Status
Claims 1-3, 6-7, 15-18 and 21-31 are currently pending and being examined.
Claim Objections
Claims 25-29 are objected to because of the following informalities: the inconsistency of the expressions “a thin-film material” in line 2 of claim 18 and “The IC device according to claim 17” in line 1 and “the thin-film material” in lines 3, 9, 11, and 13 of claim 25.
For examination purposes, “The IC device according to claim 17” in line 1 will be interpreted to read as “The IC device according to claim 18”. Appropriate correction as suggested or similar is required.
A. Claims 26-29 are objected to due to their dependence from claim 25.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6-7, 15-16, 21-24; 17-18, 25-28; and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over DEWEY et al (US 2020/0006575 A1, hereafter Dewey) in view of YOO (US 2018/0374929 A1, hereafter Yoo).
Re claim 1, Dewey discloses in FIG. 3B an integrated circuit (IC) device (350), comprising:
a transistor (U-gate thin film transistor; [0025]; [0044] and [0091]) over a support structure (352; [0047]), the transistor (U-gate thin film transistor) having a gate electrode material (354; [0047]), a thin-film channel material (358; [0047]), and a first source or drain (S/D) region (unseen at 360; [0047] and [0076]) and a second S/D region (unseen at 362; [0047] and [0076]) in the thin-film channel material (358); and
a gate dielectric material (356; [0047]),
each of the thin-film channel material (358) and the gate dielectric material (356) has a horizontal portion (bottom) substantially parallel to the support structure (352),
each of the thin-film channel material (358) and the gate dielectric material (356) has a first sidewall portion (left side) and a second sidewall portion (right side),
each of the first sidewall portion (left side) and the second sidewall portion (right side) substantially perpendicular (normal) to the support structure (352),
the horizontal portion (bottom) of the gate dielectric material (356) is between the horizontal portion (bottom) of the thin-film channel material (358) and the gate electrode material (354),
the first sidewall portion (left side) of the gate dielectric material (356) is between the first sidewall portion (left side) of the thin-film channel material (358) and the gate electrode material (354),
the second sidewall portion (right side) of the gate dielectric material (356) is between the second sidewall portion (right side) of the thin-film channel material (358) and the gate electrode material (354),
the gate electrode material (354) has a recess (trench; [0047]) from a top surface (upper plane) of the gate electrode material (354),
the horizontal portion (bottom) of the gate dielectric material (356) is at a bottom (lower plane) of the recess (trench),
the first sidewall portion (left side) of the gate dielectric material (356) is at a first sidewall portion (left side) of the recess (trench),
the second sidewall portion (right side) of the gate dielectric material (356) is at a second sidewall portion (right side) of the recess (trench),
the first S/D region (unseen at 360) is stacked above (on) a first portion (left side) of the top surface (upper plane) of the gate electrode material (354),
the second S/D region (unseen at 362) is stacked above (on) a second portion (right side) of the top surface (upper plane) of the gate electrode material (354), and
the first portion (left side) and the second portion (right side) are on opposite sides of the recess (trench).
Dewey fails to disclose a memory material, wherein: the memory material is a ferroelectric (FE) material or an antiferroelectric (AFE) material,
each of the thin-film channel material and the memory material has a horizontal portion substantially parallel to the support structure,
each of the thin-film channel material and the memory material has a first sidewall portion and a second sidewall portion,
the horizontal portion of the memory material is between the horizontal portion of the thin-film channel material and the gate electrode material,
the first sidewall portion of the memory material is between the first sidewall portion of the thin-film channel material and the gate electrode material,
the second sidewall portion of the memory material is between the second sidewall portion of the thin-film channel material and the gate electrode material,
the horizontal portion of the memory material is at a bottom of the recess,
the first sidewall portion of the memory material is at a first sidewall portion of the recess, and
the second sidewall portion of the memory material is at a second sidewall portion of the recess.
However,
Yoo discloses in FIG. 1 an integrated circuit (IC) device (1), comprising: a memory material (laminate 110/120; [0018]), wherein: the memory material (laminate 110/120; [0018]) is a ferroelectric (FE) material (120; [0018] and [0028]) or an antiferroelectric (AFE) material (118; [0025]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Dewey, by substituting the memory material of Yoo for the gate dielectric material of Dewey, wherein: the memory material is a ferroelectric (FE) material or an antiferroelectric (AFE) material, such that each of the thin-film channel material and the memory material has a horizontal portion substantially parallel to the support structure, each of the thin-film channel material and the memory material has a first sidewall portion and a second sidewall portion, the horizontal portion of the memory material is between the horizontal portion of the thin-film channel material and the gate electrode material, the first sidewall portion of the memory material is between the first sidewall portion of the thin-film channel material and the gate electrode material, the second sidewall portion of the memory material is between the second sidewall portion of the thin-film channel material and the gate electrode material, the horizontal portion of the memory material is at a bottom of the recess, the first sidewall portion of the memory material is at a first sidewall portion of the recess, and the second sidewall portion of the memory material is at a second sidewall portion of the recess, to form a variable polarization memory devices comprising ferroelectric and antiferroelectric memory layers, where the antiferroelectric memory layer suppresses creation of the depolarization electric field or limits the effect of a depolarization electric field of the memory device compared with gate dielectric layers without antiferroelectric or paraelectric properties (Yoo; [0035]).
Re claim 2, Dewey discloses the IC device according to claim 1, wherein the transistor (U-gate thin film transistor) is a bottom-gated transistor ([0037]).
Re claim 3, Dewey discloses the IC device according to claim 1, wherein: the gate electrode material (354) is in a first layer over (interface of 352/354) the support structure (352), the first S/D region (unseen at 360) and the second S/D region (unseen at 362) are in a second layer (on 356) over the support structure (352), and the first layer (interface of 352/354) is between the support structure (352) and the second layer (on 356).
Re claim 6, Dewey discloses the IC device according to claim 1, wherein: a width of the recess (trench) is a dimension of the recess (trench) between the first sidewall portion (left side) of the recess (trench) and the second sidewall portion (right side) of the recess (trench), a length of the recess (trench) is a dimension of the recess that is perpendicular to the width of the recess (trench) and substantially parallel to the support structure (352), a depth of the recess (trench) is a dimension of the recess (trench) that is perpendicular to the support structure, and a gate length of the transistor (U-gate thin film transistor) is based on (the U-shape of 354 of) a sum of the width of the recess and two times of the depth of the recess (trench).
Re claim 7, Dewey discloses the IC device according to claim 1, wherein: the horizontal portion (bottom) of the thin-film channel material (358) is proximate the (lower plane) of the recess (trench),
the first sidewall portion (left side) of the thin-film channel material (358) is proximate the first sidewall portion (left side) of the recess (trench),
the second sidewall portion (right side) of the thin-film channel material (358) is proximate the second sidewall portion (right side) of the recess (trench), and
a gate length (7-30 nm; [0044] and [0076]) of the transistor (U-gate thin film transistor) includes a sum of a length of the first sidewall portion (left side) of the thin-film channel material (358), a length of the horizontal portion (bottom) of the thin-film channel material (358), and a length of the second sidewall portion (right side) of the thin-film channel material (358).
Re claim 15, Dewey discloses the IC device according to claim 1, wherein the transistor is a top-gated transistor (in some embodiments; [0037]).
Re claim 16, Dewey discloses the IC device according to claim 1.
But, fails to disclose wherein: the first S/D region (unseen at 360) and the second S/D region (unseen at 362) are in a first layer (358) over the support structure (352), the gate electrode material (354) is in a second layer (below 356) over the support structure (352), and the first layer (358) is between the support structure (352) and the second layer (below 356).
However, Dewey discloses in FIG. 2 a top-gated transistor (200) wherein the first S/D region (212; [0041]) and the second S/D region (214; [0041]) are in a first layer (206; [0041]) over the support structure (202; [0041), the gate electrode material (210; [0041]) is in a second layer (on 208) over the support structure (202), and the first layer (206) is between the support structure (202) and the second layer (on 208).
Thus, it would have been obvious to one of ordinary skill in the art to rearrange the IC device according to the configuration of FIG. 2 to form a top-gated transistor IC device.
Re claim 21, Dewey discloses the IC device according to claim 1, wherein in a cross-sectional side (lateral left-to-right) view of the IC device (350) the thin-film channel material has a U-shape ([0047]).
Re claim 22, Dewey and Yoo disclose the IC device according to claim 1, further comprising an insulator material (364; [0048]) in a center (middle) of the recess (trench), wherein: the first sidewall portion (left side) of the thin-film channel material (358) is between the insulator material (364) in a center (middle) of the recess (trench) and the first sidewall portion (left side) of the memory material (110/120 of Yoo), and the second sidewall portion (right side) of the thin-film channel material (358) is between the insulator material in the center (middle) of the recess (trench) and the second sidewall portion (right side) of the memory material (110/120 of Yoo), as part of the variable polarization memory devices comprising ferroelectric and antiferroelectric memory layers discussed for claim 1.
Re claims 23-24, Dewey and Yoo disclose the IC device according to claim 1, further comprising an insulator structure (364; [0048]) having a first sidewall portion (left side) and a second sidewall portion (right side), wherein: the first sidewall portion (left side) of the thin-film channel material (358) is on the first sidewall portion (left side) of the insulator structure (364), the second sidewall portion (right side) of the thin-film channel material (358) is on the second sidewall portion (right side) of the insulator structure (364), and the insulator structure (364) is in a middle (center) between the first portion (left side) of the top surface (upper plane) of the gate electrode material (354) and the second portion (right side) of the top surface (upper plane) of the gate electrode material (354); and wherein the insulator structure (364) is in the recess (trench).
Re claim 17, Dewey discloses in FIG. 3B an integrated circuit (IC) device (350), comprising:
a thin-film transistor (TFT U-gate thin film transistor; [0025]; [0044] and [0091]); and
an insulator material (356; [0047]) between a gate electrode material (354; [0047]) of the TFT and a thin-film channel material (358; [0047]) of the TFT (U-gate thin film transistor), and
in a cross-sectional side (lateral left-to-right) view of the IC device (350) the thin-film channel material memory material (358) has a U-shape ([0047]).
Dewey fails to disclose wherein: the insulator material (356) is a ferroelectric (FE) material or an antiferroelectric (AFE) material.
However, Yoo renders these limitations obvious (see claim 1).
Re claim 18, Dewey discloses the IC device according to claim 17, wherein the insulator material (356) is a thin-film material (as part of the TFT).
Re claims 25-26, Dewey discloses the IC device according to claim 18, further comprising an insulator structure having a first sidewall and a second sidewall opposite the first sidewall, wherein each of the thin-film material and the insulator material between the gate electrode material of the TFT and the thin-film channel material of the TFT includes: a first portion on the first sidewall of the insulator structure, a second portion on the second sidewall of the insulator structure, and a third portion (middle) between the first sidewall and the second sidewall, wherein: the first portion of the thin-film material is between the first sidewall of the insulator structure and the first portion of the insulator material, the second portion of the thin-film material is between the second sidewall of the insulator structure and the second portion of the insulator material, and the third portion (middle) of the thin-film material is between a portion of the insulator structure between the first sidewall and the second sidewall and the third portion (middle) of the insulator material (see claims 22-24); and wherein: the insulator structure is in a middle between the first portion of the thin-film material and the second portion of the thin-film material, and the insulator structure is in a middle between the first portion of the insulator material and the second portion of the insulator material (see claims 22-24).
Re claim 27, Dewey discloses the IC device according to claim 25, wherein the first portion of the thin-film material (356), the third portion (middle) of the thin-film material (356), and the second portion of the thin-film material (356) are materially continuous portions (conformal; [0047]) of the thin-film material (356).
Re claim 28, Dewey discloses the IC device according to claim 25, wherein the first portion of the thin-film material (356), the third portion (middle) of the thin-film material (356), and the second portion of the thin-film material (356) are parts (conformal layer; [0047]) of the U-shape.
Re claim 30, Dewey discloses in FIG. 3B an integrated circuit (IC) device (350), comprising:
a substrate (352; [0047]); and
a transistor (U-gate thin film transistor; [0025]; [0044] and [0091]) over the substrate (352), the transistor (U-gate thin film transistor) comprising a gate electrode material (354; [0047]), a first insulator material (356; [0047]), and a channel material (358; [0047]),
wherein: the gate electrode material (354) includes a recess (trench; [0047]),
a first portion (left side) of the first insulator material (356) is on a first sidewall (left side) of the recess (trench),
a second portion (right side) of the first insulator material (356) is on a second sidewall (right side) of the recess (recess),
a third portion (middle) of the first insulator material (356) is at a bottom (lower plane) of the recess (trench),
a first portion (left side) of the channel material (358) is on the first portion (left side) of the first insulator material (356) on the first sidewall (left side) of the recess (trench),
a second portion (right side) of the channel material (358) is on the second portion (right side) of the first insulator material (356) on the second sidewall (right side) of the recess (trench),
a third portion (middle) of the channel material (358) is on the third portion (middle) of the first insulator material (356) at the bottom (lower plane) of the recess (trench),
a second insulator material (ILD 364; [0048] and [0079]) is in a portion (center) of the recess (trench) between the first portion (left side) of the channel material (358) and the second portion (right side) of the channel material (358),
the first insulator material (356) is a gate dielectric material ([0047]), and a material composition (e.g. low-k dielectric material; [0079]) of the second insulator material (ILD 364) is different from (not the same as) a material composition (e.g. high-K material; [0073]) of the first insulator material (356).
Dewey fails to disclose the first insulator material is a ferroelectric (FE) material or an antiferroelectric (AFE) material.
However, Yoo renders these limitations obvious (see claim 1).
Re claim 31, Dewey discloses the IC device according to claim 30, wherein the first portion (left side) of the channel material (358), the third portion (middle) of the channel material (358), and the second portion (right side) of the channel material (358) are arranged in a U-shape ([0047]).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Dewey and Yoo as applied to claim 26 above, and further in view of de Rochemont (US 2020/0092014 A1).
Re claim 29, Dewey and Yoo disclose the IC device according to claim 26.
But, fail to disclose wherein an average grain size of the thin-film material (356 of Dewey modified by 110/120 of Yoo) is below 1 millimeter.
However,
de Rochemont discloses in FIG. 4 an IC module comprising: Hf and/or Zr-based ferroelectric thin-film materials ([0065]; [0074]; [0080] and [0187]), wherein an average grain size of the thin-film material (Hf and/or Zr-based ferroelectrics) is below 1 millimeter (10 nm to 25 µm; [0067]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Dewey and Yoo, by using the Hf and/or Zr-based ferroelectrics of de Rochemont for the ferroelectrics of Yoo, wherein an average grain size of the thin-film material is below 1 millimeter, are high energy density electroceramic dielectrics, used for memory systems ([0002]) that polarize and depolarize with femto-second response times ([0057]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
A. US-20060081901-A1; US-20060017120-A1; US-20020153542-A1; US-20010012698-A1; US-7973348-B1; US-20110316059-A1; and US-20150171183-A1 disclose transistors with gates formed over ferroelectric layers.
B. US-20180155820-A1; and US-20190322588-A1 disclose grain sizes of Zr-based ferroelectric materials.
Neither references A. or B. disclose U-shaped bottom-gated structures for embedded memory solutions to which the claimed invention is directed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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