Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 8-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/20/2024. Claims 1-7 and 15-20 are being considered on the merit, while claims 8-14 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (US PGPUB 20170162702).
Regarding claim 1, Hu discloses an integrated circuit (IC) device [0061], comprising: a transistor (figures 2 and 4a) [0029] over a support structure (402) [0037], the transistor having a gate electrode material (404) [0037], a thin-film channel material (108) [0025] [0056], and a first source or drain (S/D) region (110) [0025] and a second S/D region (112) [0025] in the thin-film channel material (108); and a memory material (104) [0025], wherein: the memory material (104) is a ferroelectric (FE) material [0025] or an antiferroelectric (AFE) material, each of the thin-film channel material (108) and the memory material (104) has a horizontal portion substantially parallel to the support structure (see below for clear portions and all further limitations), each of the thin-film channel material (108) and the memory material (104) has a first sidewall portion and a second sidewall portion, each of the first sidewall portion and the second sidewall portion substantially perpendicular to the support structure (402), the horizontal portion of the memory material (104) is between the horizontal portion of the thin-film channel material (108) and the gate electrode material (404), the first sidewall portion of the memory material (104) is between the first sidewall portion of the thin-film channel material (108) and the gate electrode material (404), and the second sidewall portion of the memory material (104) is between the second sidewall portion of the thin-film channel material (108) and the gate electrode material (404).
Regarding claim 2, Hu discloses the IC device according to claim 1, wherein the transistor (figure 4A) is a bottom-gated transistor. Note that figure 4A shows a view with the gate on top, but if you flip it vertically, it is a bottom gated transistor and this orientation makes no functional difference in the device [0029].
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Marked Up Figures for Clarification Regarding Claim 2
Regarding claim 4, Hu discloses the IC device according to claim 1, wherein: the gate electrode material (402) [0037] has a recess (see marked up figure 4a below) (portion below the dashed line) from a top surface (dashed line) of the gate electrode material, the horizontal portion of the memory material (104) [0025] is at a bottom of the recess, the first sidewall portion of the memory material (104) is at a first sidewall portion of the recess, and the second sidewall portion of the memory material (104) is at a second sidewall portion of the recess.
Note that as applied to claim 2, if you flip figure 4A vertically, it is a bottom gated transistor, which would create no functional change, and would be an obvious possible arrangement to a person of ordinary skill in the art before the effective filing date of the invention.
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Marked Up and Rotated Figure 4A for Clarification Regarding Claim 4
Regarding claim 5, Hu discloses the IC device according to claim 4, wherein: the first S/D region (110) [0030] is over a first portion of the top surface of the gate electrode material, the second S/D region (112) [0026] is over a second portion of the top surface of the gate electrode material (404) [0037], and the first portion (see figure below) and the second portion are on opposite sides of the recess (region below the dashed line).
Note that the source/drain regions are not shown in figure 4A, but in figure 2A, you can see that the source/drain regions are above (over) the top surface of the gate electrode if it is oriented as a bottom-gate transistor.
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Marked Up and Rotated Figure 4A for Clarification Regarding Claim 5
Regarding claim 6, Hu discloses the IC device according to claim 4, wherein: a width of the recess (see figure below) is a dimension of the recess between the first sidewall portion of the recess and the second sidewall portion of the recess, a length of the recess (see figure below) is a dimension of the recess that is perpendicular to the width of the recess and substantially parallel to the support structure (402), a depth of the recess (see figure below) is a dimension of the recess that is perpendicular to the support structure (402), and a gate length of the transistor (400) is based on a sum of the width of the recess and two times of the depth of the recess (see figure below).
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Marked Up and Rotated Figure 4A for Clarification Regarding Claim 6
Regarding claim 7, Hu discloses the IC device according to claim 4, wherein: the horizontal portion (see “Marked Up and Rotated Figure 4A for Clarification Regarding Claim 4” above for portions and recess clarification) of the thin-film channel material (108) [0025] [0056] is proximate the bottom of the recess, the first sidewall portion of the thin-film channel material (108) is proximate the first sidewall portion of the recess, the second sidewall portion of the thin-film channel material (108) is proximate the second sidewall portion of the recess, and a gate length of the transistor includes a sum of a length of the first sidewall portion of the thin-film channel material (108), a length of the horizontal portion of the thin-film channel material (108), and a length of the second sidewall portion of the thin-film channel material (108).
Claims 1 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morris et al. (US PGPUB 20190273087).
Regarding claim 1, Morris discloses an integrated circuit (IC) device [0027] in figures 3/4, comprising: a transistor (103) [0064] over a support structure (102) [0073], the transistor having a gate electrode material (108) [0073], a thin- film channel material (118) [0073] [0132], and a first source or drain (S/D) region (120) [0069] and a second S/D region (122) [0069] in the thin-film channel material; and a memory material (124) [0073], wherein: the memory material is a ferroelectric (FE) material [0073] or an antiferroelectric (AFE) material, each of the thin-film channel material (118) and the memory material (124) has a horizontal portion substantially parallel to the support structure (see below for clear portions and all further limitations), each of the thin-film channel material (118) and the memory material (124) has a first sidewall portion and a second sidewall portion, each of the first sidewall portion and the second sidewall portion substantially perpendicular to the support structure, the horizontal portion of the memory material (124) is between the horizontal portion of the thin-film channel material (118) and the gate electrode material (108) [0064], the first sidewall portion of the memory material (124) is between the first sidewall portion of the thin-film channel material (124) and the gate electrode material (108), and the second sidewall portion of the memory material (118) is between the second sidewall portion of the thin-film channel material (118) and the gate electrode material (108).
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Figure 4 Marked Up For Claim 1 Clarification
Regarding claim 15, Morris discloses the IC device according to claim 1, wherein the transistor is a top-gated transistor (Figure 4).
Regarding claim 16, Morris discloses The IC device according to claim 1, wherein: the first S/D region (122) and the second S/D region (120) are in a first layer over the support structure (102) (see below for clarification on order of layers in reference document and all further limitations), the gate electrode material (108) is in a second layer over the support structure (102), and the first layer is between the support structure (102) and the second layer.
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Marked Up Figure 3 For Clarifying Claim 16 Rejection
Regarding claim 17, Morris discloses an integrated circuit (IC) device in figure 21 [0132], comprising: a thin-film transistor (TFT) (1240) (figure 4 for better view of transistor and components) [0132]; and a memory material (124) between a gate electrode (108) [0073] material of the TFT and a thin-film channel material of the TFT, wherein: the memory material is a ferroelectric (FE) material or an antiferroelectric (AFE) material [0065], and in a cross-sectional side view of the IC device the memory material has a U-shape (figure 3).
Regarding claim 18, Morris discloses the IC device according to claim 17, wherein the memory material is a thin-film material [0065].
Claims 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bhuwalka (US Patent 8604518)
Regarding claim 19, Bhuwalka discloses a method of fabricating an integrated circuit (IC) device in figures 1A and 1B, the method comprising: providing a thin-film (Col. 3, lines 10-20) transistor (TFT) (20) (Col. 1, lines 64-65); and providing a memory material (26) (Col. 2, lines 13-18) (HfO2 is known to be ferroelectric at thin dimensions as used in this device) between a gate electrode material (28) (Col. 2, lines 17-18) of the TFT (20) and a thin-film channel material (24) (Col. 3, lines 10-20) of the TFT (20), wherein: the memory material (26) is a ferroelectric (FE) material (HfO2) (Col. 2, lines 13-18) or an antiferroelectric (AFE) material, and in a cross-sectional side view of the IC device the memory material (26) has a U-shape (see figure 1B – if the view shown was rotated by 180 degrees it has a u-shape).
Note that the thickness of the gate insulator (26) (memory material) is not directly disclosed, but it is disclosed that the channel portions (24) and channel splitter (22) (Col. 2, lines 5-8) are at thin dimensions (Col. 3, lines 10-20), so it can be determined from the views in figures 1A and 1B that the gate insulator (26) (memory material) is also a thin material.
Regarding claim 20, Bhuwalka discloses the method according to claim 19, wherein providing the TFT (20) and providing the memory material (26) includes: depositing the gate electrode material (28), forming a recess in the gate electrode material (28), depositing a liner of the memory material (26) on sidewalls and bottom of the recess and over the gate electrode material (28) around the recess, depositing a liner of the thin-film channel material (24) over the liner of the memory material (26), and depositing an insulator material (22) (Col. 2, lines 5-8) in a remaining portion of the recess.
Note that the channel splitter (22) is disclosed as a material having a higher bandgap than the channel material in order to force current flow through the channel and thus reduce leakage current (Col. 4, lines 35-48), which an insulator material in this portion does have and serves the same purpose.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Morris as applied to claim 1 above, and further in view of Müller (US PGPUB 20220376114).
Regarding claim 3, Morris discloses the IC device according to claim 1, but does not disclose wherein: the gate electrode material is in a first layer over the support structure, the first S/D region and the second S/D region are in a second layer over the support structure, and the first layer is between the support structure and the second layer.
However, Müller discloses an IC device comprising a transistor in Figure 4B over a support structure (302) [0054], a channel material (302w) [0053], two source/drain regions (302sd) [0047] in the channel material, ferroelectric memory material (310) [0048], and a gate electrode (306) [0054];
wherein: the gate electrode material (306) is in a first layer over the support structure (302), the first S/D region (302sd) and the second S/D region (302sd) are in a second layer over the support structure (302), and the first layer (306) is between the support structure (302) and the second layer (302sd).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Morris to have the embedded source/drain regions in light of the disclosure of Muller in order to improve connections as taught by Muller [0056].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY OWEN KEEGAN whose telephone number is (703)756-1688. The examiner can normally be reached M-F 8:00-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thao X. Le can be reached on (571) 272-1708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOTHY O KEEGAN/Examiner, Art Unit 2892
/THAO X LE/Supervisory Patent Examiner, Art Unit 2892
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