DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/26/25 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Status
Claims 1-3, 5-6 and 8-13 are under consideration in this application.
Claim 14-19 are withdrawn from consideration as being drawn to a non-elected Group or Species. The election was made without traverse in the response of 2/3/24.
Claims 4 and 7 were canceled in the response of 6/13/24.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over the embodiment of Figure 8 in Guha et al. US 20180374712 A1, hereafter Guha in view of the embodiment of Figure 2 of Guha, Or-Bach et al. US 20210118699 A1, hereafter Or-Bach, Lee et al., US 20190348432 A1, hereafter Lee, and Wang et al, US 20200411545 A1, hereafter Wang.
Regarding independent claim 1 Guha, the embodiment of Figure 8, discloses the following limitations:
A method for fabricating a semiconductor device (Guha, [0019] method of fabricating a memory device), the method comprising:
forming an etch target layer (Guha, Figure 8A, where the etch target layer contains stack 804 and 820/824 bottom two pairs of layers) on a substrate (Guha, Figure 8A, 808), wherein the etch target layer includes an alternating stack layer (Guha, Figure 8A, 804), and a sacrificial stack layer (Guha, Figure 8A, 820/824 bottom two pairs of layers) on the alternating stack layer (Shown, Guha, Figure 8A), wherein the sacrificial stack layer includes a plurality of first sacrificial layers (Guha, Figure 8A, bottom two layers labeled 820) and a plurality of second sacrificial layers (Guha, Figure 8A, bottom two layers labeled 824), and the alternating stack layer includes a plurality of insulating layers (Guha, Figure 8A, unhatched layers in stack 804) and a plurality of sacrificial layers (Guha, Figure 8A, hatched layers in stack 804);
forming a hard mask pattern (Guha, Figure 8B, 820/824 top pair of layers) on the sacrificial stack layer (Guha, Figure 8B);
etching the etch target layer (Guha, Figure 8B, 824/820 bottom two layers are etched through and 8C, stack 804 is etched trough) using the sacrificial stack layer (Guha, Figure 8A, 820/824 bottom two pairs of layers) and the hard mask pattern (Guha, Figure 8B, 820/824 top pair of layers) as an etch barrier to form a plurality of initial high aspect ratio features (Shown, Guha, Figure 8B and 8C), the initial high aspect ratio features penetrating through the etch target layer (Shown. Guha, Figure 8B and 8C and [0039-0040]); and
removing the hard mask pattern (Guha, Figure 8C, 824/820 top pair has been removed) and the sacrificial stack layer (Guha, Figure 8C, 824/820 bottom two pairs have been removed) to form a plurality of high aspect ratio features (Shown, Guha, Figure 8C, and [0040]),
wherein the hard mask pattern contains a carbon material (Guha, Figure 8, top layer 820, [0039] carbon containing hardmask).
Guha in the embodiment of Figure 8, fails to disclose the following limitation:
wherein the sacrificial stack layer includes the same material as the alternating stack layer
wherein the first sacrificial layers and the insulating layers include silicon oxide, and the second sacrificial layers and the sacrificial layers include silicon nitride.
an alternating stack layer on a lower level alternating stack,
wherein the lower level alternating stack includes high aspect ratio features, and
wherein an upper width, closest to the alternating stack layer, of the high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein a thickness of an insulating layer within the lower level alternating stack increases the further away the insulating layer is located from the alternating stack layer.
Guha in the embodiment of Figure 2, discloses the following limitations (lined through items are not taught by the reference they have been included for clarity):
wherein (Guha, Figure 2G, 204, and [0036] discloses that stack 204 may be alternating layers of silicon oxide and silicon nitride (ONON stack) (insulting layer and sacrificial layers)),
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have used alternating layers of silicon oxide and silicon nitride as the stack, as taught in the embodiment of Figure 2, in the embodiment of Figure 8. Doing so would be simple substitution of one known element for another to obtain predictable results of an etched stack device.
The combination of Guha the embodiment of Figure 8 and Figure 2 fails to teach the following limitations:
wherein the sacrificial stack layer includes the same material as the alternating stack layer.
wherein the first sacrificial layers
an alternating stack layer on a lower level alternating stack,
wherein the lower level alternating stack includes high aspect ratio features, and
wherein an upper width, closest to the alternating stack layer, of the high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein a thickness of an insulating layer within the lower level alternating stack increases the further away the insulating layer is located from the alternating stack layer.
Or-Bach discloses the following limitation:
wherein the sacrificial stack layer includes the same material as the alternating stack layer (Or-Bach, [0098] discloses a hard mask stack of silicon oxide and silicon nitride layers, the same materials as the ONON stack 804 of combination of embodiments 8 and 2 of Guha).
wherein the first sacrificial layers (Or-Bach, [0098] discloses a hard mask stack of containing silicon oxide layers), and the second sacrificial layers (Or-Bach, [0098] discloses a hard mask stack containing silicon nitride layers).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have substituted the mask of Or-Bach in to the device of the embodiments of Figures 8 and 2 of Guha because Or-Bach discloses the use of a silicon oxide/silicon nitride stack as a hardmask. Doing so would be a simple substitution of a known hardmask for another hardmask to obtain predictable results.
The combination of Guha the embodiment of Figure 8 and Figure 2, and Or-Bach fail to teach the following limitations:
an alternating stack layer on a lower level alternating stack,
wherein the lower level alternating stack includes high aspect ratio features, and
wherein an upper width, closest to the alternating stack layer, of the high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein a thickness of an insulating layer within the lower level alternating stack increases the further away the insulating layer is located from the alternating stack layer.
Lee discloses the following limitations:
an alternating stack layer (Lee, Figure 6, upper structure 130) on a lower level alternating stack (Lee, Figure 6, lower structure 110),
wherein the lower level alternating stack includes high aspect ratio features (Lee, Figure 6, first hole H1 containing sacrificial pattern 120), and
wherein an upper width, closest to the alternating stack layer, of the high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer (Lee, Figure 6, shows the width of first hole H1 is greater where H1 touches the bottom of upper stack 130 than it is at the lower level of the lower stack, where H1 touches the substrate, and [0032] discloses that first hole H1 may have a tapered shape and the shape of the hole may be influenced by the characteristics of the etching process).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Lee to form a stack on top of another stack and to etch using etchants that result in different top and bottom widths of the holes, to the method of Guha and Or-Bach. Doing so would allow more memory cells to be formed in a given area, thereby increasing memory density.
The combination of Guha the embodiment of Figure 8 and Figure 2, and Or-Bach, and Lee fail to teach the following limitations:
wherein a thickness of an insulating layer within the lower level alternating stack increases the further away the insulating layer is located from the alternating stack layer.
Wang discloses the following limitation:
wherein a thickness of an insulating layer within the alternating stack increases the further away the insulating layer is located from the alternating stack layer (Figure 5, and [0071] discloses dielectric layers 112 and sacrificial layers 111 where the thickness of the insulating layers 112 increases from top to bottom, and [0050] discloses insulating layers 112 as silicon dioxide and sacrificial layers 111 as silicon nitride).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention o have applied the teaching so Wang to the method of Guha the embodiment of Figure 8 and Figure 2, and Or-Bach, and Lee because Wang teaches that using a structure where the layer thickness is varied improves the uniformity of the memory cells.
Regarding claim 2 Guha the embodiment of Figure 8 and 2 discloses the following limitations:
The method according to 1, wherein forming the alternating stack layer (Guha, Figure 8A, 804, and Figure 2G, 204, and [0036] discloses that stack 204 may be alternating layers of silicon oxide and silicon nitride ONON stack) includes alternately stacking the plurality of insulating layers (Guha, Figure 8A, 804, and Figure 2G, 204, ONON stack - oxide layers) and the plurality of sacrificial layers (Guha, Figure 8A, 804, and Figure 2G, 204, ONON stack - nitride layers), and
wherein the plurality of insulating layers and the plurality of sacrificial layers include different materials (Guha, Figure 8A, 804, and Figure 2G, 204, ONON stack).
Regarding claim 3, the combination of Guha the embodiments of Figure 8 and Figure 2, Or-Bach, Lee and Wang disclose the following limitations:
The method according to 2, wherein forming the sacrificial stack layer (Or-Bach, [0098] discloses a hard mask stack of silicon oxide and silicon nitride layers) includes alternately stacking the plurality of first sacrificial layers (Or-Bach, [0098] discloses a hard mask stack including silicon oxide layers) and the plurality of second sacrificial layers (Or-Bach, [0098] discloses a hard mask stack including silicon nitride layers), wherein
the plurality of first sacrificial layers (Or-Bach, [0098] discloses a hard mask stack including silicon oxide layers) and the plurality of insulating layers (Guha, Figure 8A, 804, and Figure 2G, 204, ONON stack - silicon oxide layers) made of a same material (silicon oxide)
the plurality of second sacrificial layers (Or-Bach, [0098] discloses a hard mask stack including silicon nitride layers) and the plurality of sacrificial layers (Guha, Figure 8A, 804, and Figure 2G, 204, ONON - nitride layers) are made of a same material (Or-Bach, [0098] discloses a hard mask stack of silicon oxide and silicon nitride layers, the same materials as the ONON stack of Figure 8A, 804, and Figure 2G, 204 of embodiments 8 and 2 of Guha)
Regarding claim 5 the combination of Guha the embodiment of Figures 8 and Figure 2, Or-Bach, Lee, and Wang disclose the following limitations:
The method according to 1, wherein the etch target layer (Guha, Figure 8A, 804, and Figure 2G, 204, ONON stack, and 820/824 in view of Or-Bach, [0098] hard mask stack of silicon oxide and silicon nitride layers) is alternately stacked with oxide layers (Guha, Figure 8A, 804 and Figure 2G, 204, ONON stack - silicon oxide layers) and nitride layers (Guha, Figure 8A, 804 and Figure 2G, 204, - ONON stack - silicon nitride layers),
wherein the alternating stack layer (Guha, Figure 8A, 804 and Figure 2G, 204) includes a greater number of oxide layers and nitride layers that are alternately stacked than in the sacrificial stack layer (Guha, Figure 8, 824/820 and Figure 2G, 204 and Or-Bach, [0098]).
Regarding claim 6, Figure 8 of Guha disclose the following limitations :
The method according to 1, wherein a thickness of the sacrificial stack layer is thinner than a thickness of the alternating stack layer (Guha, Figure 8A, the thickness of the stack of 820/824 layers is thinner than he thickness of stack 804).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Guha, Or-Bach and Lee and Wang as applied to claim 1 above in further view of Baklanov US 8961803 B1, hereafter Baklanov.
Regarding claim 8, Guha embodiment of Figure 8 further discloses the following limitations:
The method according to 1, wherein the alternating stack layer (Guha, Figure 8A, 804 and Figure 2A 204, ONON stack) and the sacrificial stack layer (Guha, Figure 8A, 820/824 bottom two pairs of layers), include silicon oxide (Guha, Figure 8A, 820 [0039] silicon oxide, and ONON stack contains silicon oxide).
Guha embodiment of Figure 8 fails to disclose the following limitations:
the hard mask pattern includes amorphous carbon.
Baklanov discloses the following limitation:
the hard mask pattern includes amorphous carbon (Baklanov, col. 8, lines 10-11, discloses silicon nitride and amorphous carbon as materials for hardmask).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Baklanov to the process of Guha and to therefore have substituted an amorphous carbon hardmask into the process of Guha and Or-Bach. Such a substitution would be a simple substitution of one known element for another to obtain predictable results (See MPEP 2143 (I)(B)).
Regarding claim 9, Guha the embodiments of Figure 8 and Or-Bach disclose the following limitations:
the alternating stack layer (Guha, Figure 8A and Figure 2G, 204, ONON stack)
the sacrificial stack layer include silicon nitride (Or-Bach, [0098] discloses a hard mask stack of silicon oxide and silicon nitride layers)
wherein the hard mask pattern includes amorphous carbon (Baklanov, col. 8, lines 10-11, discloses amorphous carbon as materials for hardmask).
Claims 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over the embodiment of Figure 8 in Guha et al. US 20180374712 A1, hereafter Guha in view of the embodiment of Figure 2 of Guha, Baklanov US 8961803 B1, hereafter Baklanov, Kim US 20210151460 A1, hereafter Kim, and Lee et al. US 20190348432 A1, hereafter Lee, and Wang et al, US 20200411545 A1, hereafter Wang.
Regarding independent claim 10, Guha the embodiment of Figure 8 discloses the following limitations:
A method for fabricating a semiconductor device (Guha, [0019] method of fabricating a memory device), the method comprising:
forming an alternating stack layer (Guha, Figure 8A, stack 804) by alternately stacking on a substrate (Guha, Figure 8A, 808);
forming a sacrificial stack layer (Guha, Figure 8A, 820/824 bottom two pairs of layers) by alternately stacking second oxide layers (Guha, Figure 8A, bottom two layers marked 820, silicon oxide) and second nitride layers (Guha, Figure 8A, bottom two layers marked 824, titanium nitride) on the alternating stack (Guha, Figure 8A, stack 804);
etching the sacrificial stack layer (Guha, Figure 8B) and the alternating stack layer (Guha, Figure 8C) to form a plurality of initial high aspect ratio features layer (Guha, Figure 8B, 824/820 bottom two layers are etched and Figure 8C), the initial high aspect ratio features penetrating through the sacrificial stack layer (Guha, Figure 8B) and the alternating stack layer (Guha, Figure 8C);
removing the sacrificial stack layer to form a plurality of high aspect ratio features (Guha, Figure 8C);
Guha in the embodiment of Figure 8, fails to discloses the following limitation:
first oxide layers, and first nitride layers.
forming an amorphous carbon layer pattern on the sacrificial stack layer;
using the amorphous carbon layer pattern as an etch barrier
removing the amorphous carbon pattern
forming a vertical channel structure filling the high aspect ratio features; and
replacing the first nitride layers of the alternating stack layer with gate electrodes.
a lower level alternating stack, the lower level alternating stack on a substrate
wherein the lower level alternating stack includes second high aspect ratio features, and
wherein an upper width, closest to the alternating stack layer, of the second high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein the lower level alternating stack is formed by alternately stacking third oxide layers and third nitride layers on the substrate and a thickness of a third oxide layer within the lower level alternating stack increases the further away the third oxide layer is located from the alternating stack layer.
Guha in the embodiment of Figure 2, discloses the following limitation:
first oxide layers, and first nitride layers (Guha, Figure 8G, 204, and [0036] discloses that stack 204 may be alternating layers of silicon oxide and silicon nitride (ONON stack))
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have used alternating layers of silicon oxide and silicon nitride as the stack, as taught in the embodiment of Figure 2, in the embodiment of Figure 8. Doing so would be simple substitution of one known element for another to obtain predictable results of an etched stack device.
Guha in the embodiment of Figure 8 and Figure 2, fail to disclose discloses the following limitations:
forming an amorphous carbon layer pattern on the sacrificial stack layer;
using the amorphous carbon layer pattern as an etch barrier
removing the amorphous carbon pattern
forming a vertical channel structure filling the high aspect ratio features; and
replacing the first nitride layers of the alternating stack layer with gate electrodes.
a lower level alternating stack, the lower level alternating stack on a substrate
wherein the lower level alternating stack includes second high aspect ratio features, and wherein an upper width, closest to the alternating stack layer, of the second high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein the lower level alternating stack is formed by alternately stacking third oxide layers and third nitride layers on the substrate and a thickness of a third oxide layer within the lower level alternating stack increases the further away the third oxide layer is located from the alternating stack layer.
Baklanov discloses the following limitations:
forming an amorphous carbon layer pattern on the sacrificial stack layer (Baklanov, col. 8, lines 10-11, discloses silicon nitride and amorphous carbon as materials for hardmask);
using the amorphous carbon layer pattern as an etch barrier (Baklanov, col. 8, lines 10-11, discloses amorphous carbon as a hardmask)
removing the amorphous carbon pattern (Baklanov, col. 8, lines 10-11 discloses that titanium nitride, silicon nitride, and amorphous carbon are equivalent hardmask materials).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Baklanov to the process of Guha and to therefore have substituted an amorphous carbon hardmask for the nitride hardmask in the process of Guha. Such a substitution would be a simple substitution of one known element for another to obtain predictable results (See MPEP 2143 (I)(B)). The substitution would result in the amorphous carbon hardmask being used as an etch barrier when preforming the etching in the process of Guha, and after etching the amorphous carbon hardmask would be removed in the process of Guha.
The combination of the embodiments of Figure 8 and Figure 2 of Guha and Baklanov fail to teach the following limitations:
forming a vertical channel structure filling the high aspect ratio features; and
replacing the first nitride layers of the alternating stack layer with gate electrodes.
a lower level alternating stack, the lower level alternating stack on a substrate
wherein the lower level alternating stack includes second high aspect ratio features, and wherein an upper width, closest to the alternating stack layer, of the second high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein the lower level alternating stack is formed by alternately stacking third oxide layers and third nitride layers on the substrate and a thickness of a third oxide layer within the lower level alternating stack increases the further away the third oxide layer is located from the alternating stack layer.
Kim discloses the following limitations:
forming a vertical channel structure (Kim, Figure 13A, VCS [0102]) filling the high aspect ratio features (Kim, Figure 13A, VCS); and
replacing the first nitride layers (Kim, Figure 13A, 210, SL layers are disclosed as silicon nitride [0102]), of the alternating stack layer with gate electrodes (Kim, Figure 15A, SL layers are removed, and Figure 17A where EL1 and EL2 replace SL layers and [0102]-[0103] and [0107] where the removed portions of SL layers are replaced with gate electrode layers EL1 and EL2).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the gate electrode layer replacement process of Kim to the process of Guha and Baklanov and to therefore have used the gate electrode layer replacement process to fabricate a memory device. Doing so would allow a high-quality gate oxide to be formed prior to the fabrications of the gate electrodes thereby improving device performance and reliability.
The combination of the embodiments of Figure 8 and Figure 2 of Guha, Baklanov and Kim fail to teach the following limitations:
first oxide layers and first nitride layers on a lower level alternating stack, the lower level alternating stack on a substrate
a lower level alternating stack, the lower level alternating stack on a substrate
wherein the lower level alternating stack includes second high aspect ratio features, and wherein an upper width, closest to the alternating stack layer, of the second high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer.
wherein the lower level alternating stack is formed by alternately stacking third oxide layers and third nitride layers on the substrate and a thickness of a third oxide layer within the lower level alternating stack increases the further away the third oxide layer is located from the alternating stack layer.
Lee discloses the following limitations:
a lower level alternating stack (Lee, Figure 6, lower structure 110), the lower level alternating stack on a substrate (Lee, Figure 6, substrate 100)
wherein the lower level alternating stack includes second high aspect ratio features (Lee, Figure 6, first hole H1 containing sacrificial pattern 120), and
wherein an upper width, closest to the alternating stack layer, of the second high aspect ratio features included in the lower level alternating stack are greater than a bottom width, closest to the lower level alternating stack, of the initial high aspect ratio features included in the alternating stack layer (Lee, Figure 6, shows the width of first hole H1 is greater where H1 touches the bottom of upper stack 130 than it is at the lower level of the lower stack, where H1 touches the substrate, and [0032] discloses that first hole H1 may have a tapered shape and the shape of the hole may be influenced by the characteristics of the etching process).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Lee to the method of Guha and Or-Bach. Doing so would allow more memory cells to be formed in a given area, thereby increasing memory density.
The combination of the embodiments of Figure 8 and Figure 2 of Guha, Baklanov, Kim, and Lee fail to teach the following limitations:
wherein the lower level alternating stack is formed by alternately stacking third oxide layers and third nitride layers on the substrate and a thickness of a third oxide layer within the lower level alternating stack increases the further away the third oxide layer is located from the alternating stack layer.
Wang discloses the following limitation:
wherein the lower level alternating stack is formed by alternately stacking third oxide layers and third nitride layers on the substrate and a thickness of a third oxide layer within the lower level alternating stack increases the further away the third oxide layer is located from the alternating stack layer (Figure 5, and [0071] discloses dielectric layers 112 and sacrificial layers 111 where the thickness of the insulating layers 112 increases from top to bottom, and [0050] discloses insulating layers 112 as silicon dioxide and sacrificial layers 111 as silicon nitride).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention o have applied the teaching so Wang to the method of Guha the embodiment of Figure 8 and Figure 2, Baklanov, Kim, and Lee because Wang teaches that using a structure where the layer thickness is varied improves the uniformity of the memory cells.
Regarding claim 11, Guha, the embodiment of Figure 8, discloses the following limitations:
The method according to 10, wherein the first oxide layers (Guha, Figure 8A, layers 820 contained in stack 804 [0038]-[0039], and in [0039] silicon oxide is disclosed for 820) and the second oxide (Guha, Figure 8A, bottom two layers marked 820) layers include silicon oxide (Guha, [0039]).
Regarding claim 13, Guha, the embodiment of Figure 8, discloses the following limitations:
a number that the first oxide layers and the first nitride layers alternate (Guha, Figure 8A, 804 contains ten pairs of 824/820 layers) is greater than a number that the second oxide layers and the second nitride layers alternate (Guha, Figure 8A, bottom two pairs of layers marked 824/820).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Guha, Baklanov, Kim, Lee, and Wang as applied to claim 10 above, and further in view of Or-Bach 20210118699 A1, hereafter Or-Bach.
Regarding claim 12, embodiment of Figure 8 of Guha further discloses:
The method according to 10, wherein the first nitride layers (Guha, Figure 8A, 804 ONON stack – silicon nitride layers) and the second nitride layers (Guha, Figure 8A, bottom two layers marked 824).
The combination of the embodiment of Figure 8 and Figure 2 in Guha, Baklanov, Kim, Lee, and Wang fail to disclose the following limitation:
include silicon nitride
Or-Bach discloses the following limitation:
include silicon nitride (Or-Bach, [0098] discloses a hard mask stack of silicon oxide and silicon nitride layers)
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have substituted the mask of Or-Bach in to the device of the embodiments of Figures 8 and 2 of Guha because Or-Bach discloses the use of a silicon oxide/silicon nitride stack as a hardmask. Doing so would be a simple substitution of a known hardmask for another hardmask to obtain predictable results.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 5-6, 8-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The rejections of independent claims 1 and 10 have been modified to address the new limitations drawn to the insulating layers of the stack increasing in thickness form the top to the bottom of the stack. Wang discloses a stack where the insulating layer thickness increases from top to bottom of the stack.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jung at al., US 20130309849 A1, discloses a silicon nitride/silicon oxide stack where the silicon nitride layers decrease in width the further away from the substrate or the oxide layer may increase in thickness as they move away from the substrate.
Guo, WO 2022205694 A1, discloses DRAM capacitors with support layers that are formed by etching high aspect ratio openings.
Chiang, US 20230115949 A1, discloses layers of a semiconductor and sacrificial where the thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.
Jiang CN 113921388 A, discloses a stack of semiconductor and sacrificial layer where the thickness of one is increased for bottom to top.
Su et al., CN 109742082 B, discloses a stack of sacrificial and insulting layers where the sacrificial layers decrease in width from bottom to top.
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/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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