DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on December 15, 2025.
Claims 1 and 29 have been amended. No new claims have been added. Claims 2, 9-11, 15-20, 23 and 25-26 have been canceled. Currently, claims 1, 3-8, 12-14, 21-22, 24 and 27-29 are pending.
Applicant’s amendment to claim 29 successfully overcomes the 112(b) rejection of claim 29 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7, 12-14, 21-22, 24, 27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2017/0125538 A1; hereafter Sharangpani) in view of Sohn et al. (US 2014/0220750 A1; hereafter Sohn), Lee et al. (US 2015/0294980 A1; hereafter Lee) and Shukla et al. (US 9,875,929 B1; hereafter Shukla).
Regarding claim 1, Sharangpani teaches a three-dimensional memory device (see e.g., Figure 19), comprising:
a vertical repetition containing multiple instances of a unit layer stack (see e.g., stack of alternating insulating layer 32 and an electrically conductive layer 46 (the backside blocking dielectric layer 66 is optional), Paras [0044], [0087], [0089], Figures 7 and 19)
memory openings vertically extending through the vertical repetition (see e.g., memory openings 49 extend through the stack, Figures 2A and 19)
memory stack structures extending through the vertical repetition and located within a respective one of the memory openings, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film, wherein the memory film comprises a vertical stack of memory elements (see e.g., memory stack structures 55 each of which contains a memory film 50 and a semiconductor channel 60 extend vertically through the stack of alternating insulating layer 32 and the electrically conductive layer 46. The memory film 50 and semiconductor channel 60 are sequentially deposited in the memory openings 49. Memory film 50 includes a first blocking dielectric layer 501, a second blocking dielectric layer 503, a charge storage element 504, a tunneling dielectric layer 506, Paras [0053], [0068], [0074], Figures 2H, 19), and wherein the unit layer stack comprises, in order, an insulating layer comprising a solid-phase dielectric material portion (see e.g., insulating layer 32 made of an insulating material not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials, Paras [0040], [0041], Figure 19), a metal layer (see e.g., electrically conductive layer 46 made of tungsten, Paras [0089], [0097], Figure 19).
a metal layer in direct contact with each of the memory stack structures
Sharangpani backside blocking dielectric layer 66 is optional (see e.g., In case the at least one blocking dielectric layer (501, 503) is present within each memory opening, the backside blocking dielectric layer 66 is optional. In case the at least one blocking dielectric layer (501, 503) is omitted, the backside blocking dielectric layer 66 is present, Para [0087]). In its absence the memory film including blocking dielectric layers 501 and 503, charge storage element 504 and a tunneling dielectric layer 506 located within the memory opening 49 will be in direct contact with the electrically conductive layer 46 made of tungsten.
wherein the solid-phase dielectric material portion is in direct contact with the memory film (see e.g., the solid insulating material of the insulating layer 32 is in direct contact with the memory film including blocking dielectric layers 501 and 503, charge storage element 504 and a tunneling dielectric layer 506 located within the memory opening 49, Figure 19)
Sharangpani does not explicitly teach
“an airgap-containing insulating layer comprising a combination of a solid-phase dielectric material portion and an encapsulated airgap which is encapsulated by the solid-phase dielectric material portion,…. and the encapsulated airgap is not in direct contact with the memory film, and is spaced from the memory film by the solid-phase dielectric material portion”.
In a similar field of endeavor Sohn teaches
an airgap-containing insulating layer comprising a combination of a solid-phase dielectric material portion and an encapsulated airgap which is encapsulated by the solid-phase dielectric material portion (see e.g., second insulating layer 183 with encapsulated airgaps AG, Para [0095], Figure 15),…. the encapsulated airgap is not in direct contact with the memory film, and is spaced from the memory film by the solid-phase dielectric material portion (see e.g., the airgap AG is not in direct contact with the memory film and is spaced from the memory film DA by the second insulating layer 183, Figure 15).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Sohn’s teachings of an airgap-containing insulating layer comprising a combination of a solid-phase dielectric material portion and an encapsulated airgap which is encapsulated by the solid-phase dielectric material portion,…. the encapsulated airgap is not in direct contact with the memory film, and is spaced from the memory film by the solid-phase dielectric material portion in the device of Sharangpani in order to reduce parasitic capacitance.
Sharangpani does not explicitly teach
“a first interfacial dielectric capping layer in direct contact with the airgap insulating layer,
a metal layer in direct contact with the first interfacial dielectric capping layer,
and a second interfacial dielectric capping layer”,
In a similar field of endeavor Lee teaches
a first interfacial dielectric capping layer in direct contact with the airgap insulating layer (see e.g., high-k dielectric pattern 59a disposed between the conductive lines LSL, WL1 to WLn, and USL and the intergate insulating layer 7 and is in direct contact with the integrate insulating layer 7, Para [0078], Figure 23),
a metal layer in direct contact with the first interfacial dielectric capping layer (see e.g., as shown in Figure 23 the word lines are in direct contact with the memory stack including a high-k dielectric layer 19, a blocking dielectric layer 21, a charge trap layer 23, a tunnel dielectric layer 25, and a first active layer 27 and a second active layer 29, Para [0062])
and a second interfacial dielectric capping layer (see e.g., the high-k dielectric pattern 59a disposed between the conductive lines LSL, WL1 to WLn, and USL and the intergate insulating layer 11, Para [0078], Figure 23).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of a first interfacial dielectric capping layer in direct contact with the airgap insulating layer, a metal layer in direct contact with the first interfacial dielectric capping layer, and a second interfacial dielectric capping layer in the device of Sharangpani in order to reduce the RC delay and improve the signal transfer speed of the gate electrodes.
Sharangpani does not explicitly teach
“the encapsulated airgap has a first end and an opposing second end;
the first end comprises a vertical surface that is parallel to the memory film; and
the second end comprises a tapered end that is located farther from the memory film than the first end”.
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Shukla teaches
the encapsulated airgap has a first end and an opposing second end (see e.g., encapsulated voids 37’ and 33’ have a first end and an opposing end, Column 18, Lines 61-67, Column 19, Lines 1-10, Figure 11C);
the first end comprises a vertical surface that is parallel to the memory film; and (see e.g., the first end comprises a vertical surface parallel to the memory film 50, Figure 11C)
the second end comprises a tapered end that is located farther from the memory film than the first end (see e.g., the other end comprises a tapered end that is located further away from the memory film than the first end, Figure 11C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shukla’s teachings of the encapsulated airgap has a first end and an opposing second end; the first end comprises a vertical surface that is parallel to the memory film; and
the second end comprises a tapered end that is located farther from the memory film than the first end in the device of Sharangpani as this would lead to predictable improvements in device performance, such as optimized electrical isolation and reduced parasitic capacitance due to controlled tapered geometry.
Regarding claim 3, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani further teaches
further comprising a pair of backside trench fill structures, wherein the pair of backside trench fill structures contacts sidewalls of the vertical repetition, and wherein each of the memory stack structures is located between the pair of backside trench fill structures (see e.g., pair of backside via trenches 79, shown in Figure 5B, are formed in an area in which backside contact via structures 76 are desired. The memory stack structures 55 are located between the pair of the backside via trenches 79. The backside contact via structures 76 formed in the backside via trenches extend through and is in contact with the alternating stack (32, 46), Paras [0074], [0081], [0142], Figures 5B and 19).
Regarding claim 4, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 3 as mentioned above. Sharangpani does not explicitly teach
“wherein each of the encapsulated airgaps laterally surrounds each of the memory stack structures and is located between the pair of backside trench fill structures”.
In a similar field of endeavor Sohn teaches
wherein each of the encapsulated airgaps laterally surrounds each of the memory stack structures and is located between the pair of backside trench fill structures (see e.g., the second insulating layer 183 with encapsulated airgaps laterally surrounds each of the memory stacks structures and is located between the pair of through electrode 185 formed to fill the trench 140, Figure 15; Examiner’s interpretation: Figure 15 is a cross-section of the memory device there would be multiple memory stack structures and through electrodes 185 in the memory device).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Sohn’s teachings of wherein each of the encapsulated airgaps laterally surrounds each of the memory stack structures and is located between the pair of backside trench fill structures in the device of Sharangpani in order to reduce the RC delay and improve the signal transfer speed of the gate electrodes.
Regarding claim 7, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani does not explicitly teach wherein:
“an average thickness of the first interfacial dielectric capping layers is less than 20 % of an average thickness of the metal layers; and
an average thickness of the second interfacial dielectric capping layers is less than 20 % of the average thickness of the metal layers”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Lee shows in Figure 23 the high-k dielectric patterns 59a being much thinner than the conductive lines LSL, WL1 to WLn, and USL.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the thickness of the first and second interfacial dielectric capping layers as per device requirements.
Regarding claim 12, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani further teaches
wherein: the memory film comprises a continuous memory material layer which continuously vertically extends through the vertical repetition of the insulating layers, the metal layers; and (see e.g., memory material 504 is a continuous memory material layer which continuously vertically extends through the vertical repetition of insulating layers 32 and metal layers 46, Figure 19)
the vertical stack of memory elements comprises portions of the continuous memory material layer that continuously vertically extends through the vertical repetition (see e.g., a memory material layer 504 extending through the alternating stack (32, 46) and comprises an insulating charge trapping material, such as one or more silicon nitride segments, Para [0058], Figures 2H and 19).
Sharangpani does not explicitly teach
“the vertical repetition of the airgap-containing insulating layers, the first interfacial dielectric capping layers, the metal layers, and the second interfacial dielectric capping layers”.
In a similar field of endeavor Lee teaches
the vertical repetition of the airgap-containing insulating layers (see e.g., airgap disposed between the first integrate insulating layer 7 and second integrate insulating layer 11, Para [0054], Figure 23), the first interfacial dielectric capping layers (see e.g., high-k dielectric pattern 59a, Para [0078], Figure 23), the metal layers (see e.g., gate electrodes, Para [0078], Figure 23), and the second interfacial dielectric capping layers (see e.g., high-k dielectric pattern 59a, Para [0078], Figure 23).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of the vertical repetition of the airgap-containing insulating layers, the first interfacial dielectric capping layers, the metal layers, and the second interfacial dielectric capping layers in the device of Sharangpani in order to reduce the RC delay and improve the signal transfer speed of the gate electrodes.
Regarding claim 13, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 12 as mentioned above. Sharangpani further teaches
wherein each of the memory stack structures comprises at least one blocking dielectric layer (see e.g., first blocking layer 501 and a second blocking layer 503 extending through the alternating stack (32, 46), Para [0053], Figures 2H and 19).
Regarding claim 14, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 13 as mentioned above. Sharangpani further teaches
wherein the at least one blocking dielectric layer comprises an outer aluminum oxide blocking dielectric layer and an inner silicon oxide blocking dielectric layer located between the outer aluminum oxide blocking dielectric layer and the respective continuous memory material layer (see e.g., first blocking layer 501 deposited on the sidewalls of each memory opening 49 includes a dielectric metal oxide such as aluminum oxide. The second blocking dielectric layer 503 formed on the first blocking dielectric layer 501 and includes silicon oxide, Paras [0055] – [0056], Figures 2H and 19).
Regarding claim 21, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 12 as mentioned above. Sharangpani further teaches
wherein the respective memory film is located entirely within a respective one of the memory openings, (see e.g., the memory stack structure comprises a memory film including blocking dielectric layers 501 and 503, charge storage element 504 and a tunneling dielectric layer 506 located within the memory opening 49, Para [0053], Figures 2D, 19).
and is in direct contact with each of the metal layers in the vertical repetition
Sharangpani backside blocking dielectric layer 66 is optional (see e.g., In case the at least one blocking dielectric layer (501, 503) is present within each memory opening, the backside blocking dielectric layer 66 is optional. In case the at least one blocking dielectric layer (501, 503) is omitted, the backside blocking dielectric layer 66 is present, Para [0087]). In its absence the memory film including blocking dielectric layers 501 and 503, charge storage element 504 and a tunneling dielectric layer 506 located within the memory opening 49 will be in direct contact with the electrically conductive layer 46 made of tungsten.
Regarding claim 22, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 21 as mentioned above. Sharangpani further teaches
wherein the memory film further comprises: at least one blocking dielectric layer that vertically extends through (see e.g., blocking dielectric layer 501 and 503, vertically extending through the memory opening 49, Para [0053], Figures 2D and 19); and a tunneling dielectric layer (see e.g., tunneling dielectric layer 506, Para [0059], Figures 2D and 19).
at least one blocking dielectric layer is in direct contact with each of the metal layers in the vertical repetition
Sharangpani backside blocking dielectric layer 66 is optional (see e.g., In case the at least one blocking dielectric layer (501, 503) is present within each memory opening, the backside blocking dielectric layer 66 is optional. In case the at least one blocking dielectric layer (501, 503) is omitted, the backside blocking dielectric layer 66 is present, Para [0087]). In its absence the memory film including blocking dielectric layers 501 and 503, charge storage element 504 and a tunneling dielectric layer 506 located within the memory opening 49 will be in direct contact with the electrically conductive layer 46 made of tungsten.
Regarding claim 24, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 14 as mentioned above. Sharangpani further teaches
wherein: the outer aluminum oxide blocking dielectric layer contacts the inner silicon oxide blocking dielectric layer; and the inner silicon oxide blocking dielectric layer contacts the respective continuous memory material layer (see e.g., first blocking layer 501 deposited on the sidewalls of each memory opening 49 includes a dielectric metal oxide such as aluminum oxide. The second blocking dielectric layer 503 formed on the first blocking dielectric layer 501 and includes silicon oxide, Paras [0055] – [0056], Figures 2H and 19).
Regarding claim 27, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani further teaches
wherein: the memory film further comprises a blocking dielectric layer that laterally surrounds the vertical stack of memory elements; and (see e.g., the memory film includes blocking dielectric layers 501 and 503, charge storage element 504 and a tunneling dielectric layer 506 located within the memory opening 49, Paras [0055] – [0056], Figures 2H and 19)
the solid-phase dielectric material portion is in direct contact with the blocking dielectric layer (see e.g., the solid material of the insulating layer 32 is in direct contact with the blocking dielectric layer 501 and 503, Para [0053], Figure 19).
Regarding claim 29, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani further teaches
wherein an outer sidewall of the memory film vertically extends straight through an entirety of the vertical repetition; and (see e.g., the outer sidewall of the memory film 50 that is, the outer sidewall of the blocking dielectric layer 501, vertically extends straight through an entirety of the vertical repetition, Para [0053], Figures 2H and 19)
Sharangpani does not explicitly teach
“the first end of the encapsulated airgap comprises a vertical surface”.
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Shukla teaches
the first end of the encapsulated airgap comprises a vertical surface (see e.g., encapsulated voids 37’ and 33’ have a first end and an opposing end. The first end comprises a vertical surface parallel to the memory film 50, Column 18, Lines 61-67, Column 19, Lines 1-10, Figure 11C)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Shukla’s teachings of the first end of the encapsulated airgap comprises a vertical surface in the device of Sharangpani as this would lead to predictable improvements in device performance, such as optimized electrical isolation and reduced parasitic capacitance.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2017/0125538 A1; hereafter Sharangpani) in view of Sohn et al. (US 2014/0220750 A1; hereafter Sohn), Lee et al. (US 2015/0294980 A1; hereafter Lee), Shukla et al. (US 9,875,929 B1; hereafter Shukla) and further in view of Ohto et al. (US 2004/0152334 A1; hereafter Ohto).
Regarding claim 5, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani does not explicitly teach
“wherein: the first interfacial dielectric capping layer comprises a first oxygen-free dielectric material; and
the second interfacial dielectric capping layer comprises a second oxygen-free dielectric material”.
In a similar field of endeavor Lee teaches
the first interfacial dielectric capping layer comprises a first oxygen-free dielectric material; and
the second interfacial dielectric capping layer comprises a second oxygen-free dielectric material (see e.g., a high-k dielectric pattern 59a disposed between the conductive lines LSL, WL1 to WLn, and USL and the intergate insulating layers 7 and 11 adjacent thereto, Para [0078], Figure 23).
Lee teaches in paragraph 0056 that a high-k dielectric material is a material which has a dielectric constant higher than that of silicon oxide.
Lee is silent with regards to the specific material having dielectric constant higher than that of silicon oxide used for the high-k dielectric pattern 59a thereby, not precluding materials such as SiN, SiC or SiCN which have dielectric constant greater than that of SiO.sub.2. as taught by Ohto (see e.g., Para [0011]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of the first interfacial dielectric capping layer comprises a first oxygen-free dielectric material; and the second interfacial dielectric capping layer comprises a second oxygen-free dielectric material in the device of Sharangpani in order to reduce the RC delay and improve the signal transfer speed of the gate electrodes.
Regarding claim 6, Sharangpani, as modified by Sohn, Lee, Shukla and Ohto, teaches the limitations of claim 5 as mentioned above. Sharangpani does not explicitly teach
“wherein: the first oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride; and
the second oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride”.
In a similar field of endeavor Lee teaches
the first oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride; and
the second oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride (see e.g., a high-k dielectric pattern 59a disposed between the conductive lines LSL, WL1 to WLn, and USL and the intergate insulating layers 7 and 11 adjacent thereto, Para [0078], Figure 23).
Lee teaches in paragraph 0056 that a high-k dielectric material is a material which has a dielectric constant higher than that of silicon oxide.
Lee is silent with regards to the specific material having dielectric constant higher than that of silicon oxide used for the high-k dielectric pattern 59a thereby, not precluding materials such as SiN, SiC or SiCN which have dielectric constant greater than that of SiO.sub.2. as taught by Ohto (see e.g., Para [0011]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of the first oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride; and the second oxygen-free dielectric material is selected from silicon carbide, silicon nitride, or silicon carbide nitride in the device of Sharangpani in order to reduce the RC delay and improve the signal transfer speed of the gate electrodes.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2017/0125538 A1; hereafter Sharangpani) in view of in view of Sohn et al. (US 2014/0220750 A1; hereafter Sohn), Lee et al. (US 2015/0294980 A1; hereafter Lee), Shukla et al. (US 9,875,929 B1; hereafter Shukla) and further in view of Kitagawa et al. (US 2022/0310401 A1; hereafter Kitagawa).
Regarding claim 8, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 1 as mentioned above. Sharangpani does not explicitly teach
“wherein the metal layers comprise molybdenum at an atomic percentage that is greater than 90%”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Kitagawa teaches
wherein the metal layers comprise molybdenum at an atomic percentage that is greater than 90% (see e.g., The conductor layer 22 comprises, for example, elemental molybdenum in an amount of not less than 99 atom %, Para [0069], Figure 5).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kitagawa’s teachings of metal layers comprising molybdenum at an atomic percentage that is greater than 90% in the device of Sharangpani in order to optimize device performance.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (US 2017/0125538 A1; hereafter Sharangpani) in view of in view of Sohn et al. (US 2014/0220750 A1; hereafter Sohn), Lee et al. (US 2015/0294980 A1; hereafter Lee), Shukla et al. (US 9,875,929 B1; hereafter Shukla) and further in view of Ahn et al. (US 2020/0402997 A1; hereafter Ahn).
Regarding claim 28, Sharangpani, as modified by Sohn, Lee and Shukla, teaches the limitations of claim 27 as mentioned above. Sharangpani does not explicitly teach
“wherein the encapsulated airgap is spaced from the blocking dielectric layer only by the solid-phase dielectric material portion”.
In a similar field of endeavor Ahn teaches
wherein the encapsulated airgap is spaced from the blocking dielectric layer only by the solid-phase dielectric material portion (see e.g., the encapsulated air space 144 is spaced from the blocking dielectric layer 152Z by the insulating layer 142, Paras [0040], [0042], Figure 3)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Ahn’s teachings of wherein the encapsulated airgap is spaced from the blocking dielectric layer only by the solid-phase dielectric material portion in the device Sharangpani in order to have an air gap in the insulating layer so as to decrease the parasitic capacitance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893