The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23-25 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) in view of Nakajima (2014/0204552).Regarding claim 23, Yun et al. teach in figure 4 and related text a semiconductor device apparatus comprising:
a die 402 comprising an input port and an output port 408; and
a multilayer package substrate 100, 102 (see figure 1A) or MCM 400 (see figure 4 and related text “package substrate in a chip module or multi-chip module (MCM).) comprising:
contacts on a first surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board (PCB); and
a passive filter 422 comprising an input port and an output port (inherently therein), and a planar inductor 416 coupled to a given contact 134 (see figure 1B) of the contacts of the multilayer package substrate with a first via (un-numbered) of the multilayer package substrate and to the input port of the die with a second via; and
a die 402 attached to the multilayer package substrate, the die comprising an input port coupled to the output port 408 of the multilayer package substrate and an output port 414/410 coupled to a second pad of the pads of the multilayer package substrate, wherein the input port and the output port of the die are coupled to (i.e. linked to or joined together) on a topmost surface of the multilayer package substrate.
Yun et al. do not explicitly state using pads or metal structures on a surface of the multilayer package substrate and wherein the planar inductor is coupled to the input port of the die with a second via of the multilayer package substrate.
Nakajima teaches in figure 1A and related text using metal structures and pads 3 on a surface of the multilayer package substrate 2.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use pads and metal structures on a surface of the multilayer package substrate, as taught by Nakajima and to couple the planar inductor to the input port of the die with a second via of the multilayer package substrate in Yun et al.’s device, in order to improve the contact resistance of the device by using conventional pads and in order to be able to couple the planar inductor to the input port of the die because both elements are located inside the multilayer package substrate, when using the device in a portable application (where the bottom surface is the topmost surface of the device), respectively.
Regarding claim 24, Yun et al. teach in figure 4 and related text that the multilayer package substrate 114, 102 further comprises: a first metal plating pattern 412 forming a first layer of the multilayer package substrate; and a dielectric layer (un-numbered) applied to the first metal plating pattern to form a second layer of the multilayer package substrate.
Regarding claim 25, Yun et al. teach in figure 4 and related text that the planar inductor is a spiral inductor (see figure 1A), and the second layer includes the spiral inductor 418.
Regarding claim 28, Yun et al. teach in figure 4 and related text a molding material 426 adhering to the die to the multilayer package substrate.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) and Nakajima (2014/0204552), as applied to the claims above, and further in view of Nakahara (5,502,421).Regarding claim 26, Yun et al. and Nakajima teach substantially the entire claimed structure, as applied to the claims above, except using a second spiral inductor coupled to the second input port of the die with a third via and to another pad of the pads of the multilayer package substrate with a fourth via.
Nakahara teaches in figure 3 and related text a second inductor 4b (see figure 2) coupled to a second input port of the die 100 with a third via 13a and to another pad (the square contact) of the pads of the multilayer package substrate with a fourth via 13b.
Nakajima, Yun et al. and Nakahara are analogous art because they are directed to devices comprising filters and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a second spiral inductor coupled to the second input port of the die with a third via and to another pad of the pads of the multilayer package substrate with a fourth via, as taught by Nakahara, such that the passive filter in prior art’s device comprising a second spiral inductor coupled to the second input port of the die with a third via and to another pad of the pads of the multilayer package substrate with a fourth via, in order to use the device in an application which requires specific band width.
Claims 1-5, 10-14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293) in view of Nakajima (2014/0204552) and Mathew et al. (5,328,079).
Regarding claims 1 and 21, Yun et al. teach in figures 4, 1B and related text a semiconductor device apparatus comprising:
a die 402 comprising an input port 408 and an output port 408; and
a multilayer package substrate 114, 102 (see figure 1A) comprising:
an input port 414/410 coupled (at least electrically coupled) to the output port 408 of the die:
an output port 414/410 coupled (at least electrically coupled) to the input port 408 of the die
contacts 410 on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board (PCB); and
a passive filter 422 comprising a planar inductor 416/128 coupling a given contact 134 (see figure 1B) of the contacts of the multilayer package substrate to the output port 414/410 of the multilayer package substrate 114,
wherein the input port and the output port of the die are coupled to (i.e. linked to or joined together) a topmost surface of the multilayer package substrate.
Yun et al. do not explicitly state using pads or metal structures on a surface of the multilayer package substrate, wherein the planar inductor is coupled to the input port of the die with a second via of the multilayer package substrate, and wherein the multilayer package substrate comprising an input port coupled to the output port of the die and an output port coupled to the input port of the die
Nakajima teaches in figure 1A and related text a multilayer package substrate 2 comprising metal structures 3 an input port 3 coupled to the output port 7 of the die 4.
Mathew et al. teach in figure 4 and related text that the multilayer package substrate 12 comprising metal structures 14 an input/output port 18 coupled to the input/output port of the die 16.
Nakajima, Yun et al. and Mathew et al. are analogous art because they are directed to semiconductor devices comprising dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use pads on a surface of the multilayer package substrate and to couple the planar inductor to the input port of the die with a second via of the multilayer package substrate, and to form the multilayer package substrate comprising metal structures and an input port coupled to the output port of the die and an output port coupled to the input port of the die, as taught by Nakajima and Mathew et al., in Yun et al.’s device, in order to improve the contact resistance of the device by using conventional pads and in order to be able to couple the planar inductor to the input port of the die because both elements are located inside the multilayer package substrate, and to provide electrical connection between the filter and the die, when using the device in a portable application (where the bottom surface is the topmost surface of the device), respectively.
Regarding claim 2, Yun et al. teach in figure 1B and related text that the planar inductor 128 is a spiral inductor formed on an interior layer of the multilayer package substrate.
Regarding claim 3, Yun et al. teach in figure 4 and related text that the passive filter 422 further comprises a capacitor 420 coupled to the input port of the die, the output port of the multilayer packed substrate and to another pad (or contact) of the pads of the multilayer package substrate.
Regarding claim 4, Yun et al. teach in figure 4 and related text that the capacitor 420 is formed with plates formed on spaced apart layers of the multilayer package substrate.
Regarding claim 5, the claimed limitations of “the capacitor is a surface mount technology (SMT) capacitor”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Regarding claim 10, Yun et al. teach in figure 4 and related text that the planar inductor is coupled to the given pad of the pads of the multilayer package substrate with a third via.
Regarding claim 11, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the planar inductor having an inductance of at least 200 nanohenries in Yun et al.’s device, in order to use the device in application which requires specific capacitance values.
Regarding claims 12-13, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a die comprises a power converter module, wherein the power converter module is a buck converter and wherein the output port of the die is configured to be coupled to a load mounted on the PCB in Yun et al.’s device, in order to use the device in application which requires specific electronic elements.
Regarding claim 14, Yun et al. teach in figure 14 and related text that the passive filter is configured to be coupled to a bulk filter mounted of the PCB, whereby the bulk filter is a first section filter of a two section input filter for the power converter module and the passive filter is a second section filter of the two section input filter for the power converter module.
Regarding claim 21, Yun et al. teach in figure 4 and related text substantially the entire claimed structure, as applied to the claims above, except explicitly stating connecting the apparatus to a printed circuit board (PCB). It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect Yun et al.’s device to a printed circuit board (PCB) in, in order to use the device in a practical application.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (11,728,293), Nakajima (2014/0204552) and Mathew et al. (5,328,079), as applied to the claims above, and further in view of Nakahara (5,502,421).Regarding claim 6, Yun et al., Nakajima and Mathew et al. teach substantially the entire claimed structure, as applied to the claims above, except using a second spiral inductor coupled to the second input port of the die with a first via and to another pad of the pads of the multilayer package substrate with a second via.
Nakahara teaches in figure 3 and related text a second inductor 4b (see figure 2) coupled to a second input port of the die 100 with a third via 13a and to another pad (the square contact) of the pads of the multilayer package substrate with a fourth via 13b.
Nakajima, Yun et al., Mathew et al. and Nakahara are analogous art because they are directed to semiconductor devices comprising dies and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yun et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a second spiral inductor coupled to the second input port of the die with a first via and to another pad of the pads of the multilayer package substrate with a second via, as taught by Nakahara, such that the passive filter in Yun et al.’s device comprising a second spiral inductor coupled to the second input port of the die with a first via and to another pad of the pads of the multilayer package substrate with a second via, in prior art’s device in order to use the device in an application which requires specific band width.
Regarding claims 7 and 9, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first spiral inductor and the second spiral inductor having about equal inductance and to form the first spiral inductor and the second spiral inductor having a combined inductance of at least 20 nanohenries, in prior art’s device in order to use the device in an application which requires specific capacitance.
Regarding claim 8, in the combined device, first spiral inductor and the second spiral inductor are spaced apart.
Response to Arguments
1. Applicants argue that Yun et al., Nakajima and Mathew et al. do not teach the presence of metal structures on a topmost surface of the multilayer package substrate.
1. As discussed in the rejection above, Nakajima teaches in figure 1A and related text metal structures 3 on a topmost surface of the multilayer package substrate 2 and Mathew et al. teach in figure 4 and related text metal structures 14 on a topmost surface of the multilayer package substrate 12.
Furthermore, regarding applicants’ argument that metal structures are not present on a topmost surface of the multilayer package substrate, it is asserted that the combined device of Yun et al., Nakajima and Mathew et al. can be used in a portable application such that the bottom surface is the topmost surface of the device.
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O.N. /ORI NADAV/
11/29/2025 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800