Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed March 16th, 2026 (“A...”), in which: claims 1, 3, and 7 are amended; claims 2 and 9 – 10 are cancelled; no new claims are added; and the rejection of the claims are traversed. Claims 1, 3 – 8, and 11 – 17, wherein claims 12 – 17 are withdrawn from consideration, are currently pending an Office action on the merits as follows.
Acknowledgment is made of the amendment filed March 16th, 2026 (“A...”), in which claims 2 and 10 are cancelled in response to the rejection of claims 2 and 10 under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The amendment is such that rejection of claims 2 and 10 under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends is rendered moot. Examiner withdraws the rejection of claims 2 and 10 under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Response to Arguments
Applicant’s arguments filed March 16th, 2026 (“REM”) with respect to claims 1, 3 – 8, and 11 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 7 – 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Parries et al. (US 20120122303 A1), and further in view of Cai et al. (US 9202864 B2) and Rauscher et al. (US 20070262411 A1).
Regarding independent Claim 1, Parries teaches a method for fabricating semiconductor device, comprising:
forming a mask layer on the substrate ([0022]; lines 1 - 4 teaches pad nitride layer 20 and oxide hard mask layer 22, wherein the examiner is interpreting both the teaches pad nitride layer 20 and oxide hard mask layer 22 to be a mask layer);
removing part of the mask layer to form a second patterned mask (Fig. 1 and [0025] teaches etching through the mask layer to form first trench 24 and second trench 26 simultaneously; such that parts of the mask is removed, leaving a second patterned mask) on the substrate and a first trench (Fig. 1; first trench 24) and a second trench (Fig. 1; second trench 26) in a substrate (Fig. 1; semiconductor substrate 12) at the same time (Fig. 1 and [0025] teaches etching through the mask layer to form first trench 24 and second trench 26 simultaneously), …
forming a liner ([0026] and Fig. 2 teaches forming liner 28) in the first trench and the second trench (Fig. 2); …
removing the liner in the first trench (Fig. 4); …
forming an insulating layer (Fig. 2; polysilicon 30) in the first trench and the second trench (Fig. 2) and covering the second patterned mask (Fig. 2) at the same time as ... the insulating layer in the second trench directly contacts a top surface (Fig. 2; see bottom of second trench) and sidewalls of the liner (Fig. 2; see sidewalls of second trench), ... and
planarizing part of the insulating layer (Fig. 6) ...
However, Parries remains silent regarding the method for fabricating a semiconductor device (bolded for emphasis):
… wherein a depth of the first trench is greater than a depth of the second trench; …
forming a first patterned mask on the substrate to cover the second trench; …
removing the first patterned mask; …
forming an insulating layer in the first trench and the second trench and covering the second patterned mask at the same time as the insulating layer in the first trench directly contacts the substrate directly under and adjacent to two sides of the first trench and the insulating layer in the second trench directly contacts a top surface and sidewalls of the liner, wherein the insulating layer comprises undoped polysilicon; ...
planarizing … all the second patterned mask to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.
However, in the same field of endeavor, Cai teaches a similar method wherein a depth of the first trench is greater than a depth of the second trench (Fig. 10). Cai’s teaching may be applied to the trenches of Parries, as Cai teaches the shallow trenches being used for intra-well isolation and the deep trench isolation (DTI) being used for inter-well isolation (Col. 3; lines 7 – 14). Therefore, it would have been obvious before the effective filing date of the instant invention to modify Parries’ method for fabricating a semiconductor device, in view of Cai, to yield a method wherein a depth of the first trench is greater than a depth of the second trench.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Parries method of forming a semiconductor device to include the difference in depths between the first and second trench, as taught by Cai, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Cai’s trenches are comparable to Parries’ trenches because they both form isolation structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Parries method of forming a semiconductor device to include the difference in depths between the first and second trench, as taught by Cai, with the predictable result of providing isolation structures of different capabilities, e.g., the shallow trenches being used for intra-well isolation and deep trench isolation (DTI) being used for inter-well isolation (Col. 3; lines 7 – 14).
Further, in the same field of endeavor, Rauscher teaches a method of forming trench isolation structures including the use of a first patterned mask (Fig. 4c; masking layer 31) such that a liner (Figs. 4b-c; a dielectric layer 30), as well as additional material, may be etched away from the bottom of a first trench (Fig. 4c; hole 26). Parries’ semiconductor device structure may be modified, such that the method of forming Parries’ semiconductor device may include an added step of using Rauscher’s first patterned mask to remove the portions of Parries’ liner 28 from the bottom of the first trench before depositing polysilicon. Rauscher teaches that isolation structure reaches the bottom of the substrate in order to form contact post that may be used to ground or bias a substrate ([0003] – [0004]), wherein one of ordinary skill in the art would recognize the benefit of forming contact posts analogous to that of Rauscher in the semiconductor device of Parries. Thus, examiner asserts it would be obvious before the effective filing date of the instant invention to modify Parries’ structure and method, further in view of Rauscher, to include the step of forming a first patterned mask on the substrate to cover the second trench and subsequently removing the first patterned mask.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Parries’ method of forming a semiconductor structure to include Rauscher’s method of forming a first patterned mask on the substrate to cover the second trench and subsequently removing the first patterned mask, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Rauscher’s method of forming a patterned mask is comparable to Parries use of mask, as well as the applicants’ use, because they are used to mask portions of a device substrate such that unmasked portions of a device substrate may be processed to form structures thereon. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Parries’ method of forming a semiconductor structure to include Rauscher’s method of forming a first patterned mask on the substrate to cover the second trench and subsequently removing the first patterned mask with the predictable result of processing unmakes portions of the device substrate.
The combination of Parries, further in view of Cai and Rauscher, further has the effect of modifying Parries’ formed insulating layer (bold and underlined for emphasis) such that forming an insulating layer in the first trench and the second trench and covering the second patterned mask at the same time as the insulating layer in the first trench directly contacts the substrate directly under and adjacent to two sides of the first trench and the insulating layer in the second trench directly contacts a top surface and sidewalls of the liner. This is a result of Rauscher’s disclosed contact post.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Parries’ trenches to include Rauscher’s insulating material filling the trenches and touching the device substrate, because Rauscher’s undoped polysilicon insulating material filling the material is known versatile material that is insulating but may be processed to implant/drive-in dopants forming semiconducting structures that may hold/carry/trap/ charges or to prevent/facilitate the movement thereof, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Rauscher’s undoped polysilicon is comparable to Parries’ filling insulating materials because they may be used for trench isolation structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Parries’ trenches to include Rauscher’s undoped polysilicon insulating material filling with the predictable result of forming a deep isolation within the semiconductor device.
Further, Rauscher teaches the use of undoped polysilicon 34 as an insulating layer filling both of trench 28, i.e., a second trench, and hole 26, i.e., a first trench. Therefore, it would be obvious to use undoped polysilicon as a filling material for trench isolation because it is demonstrated as standard practice within the field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Parries’ trenches to include Rauscher’s polysilicon, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, polysilicon is comparable to the insulating materials disclosed by Parries because Parries discloses polysilicon as an insulating fill material. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Parries’ trenches to include Rauscher’s polysilicon with the predictable result of forming isolation structures.
Additionally, in the same field of endeavor, Cai teaches a similar method further including the step of planarizing part of the insulating layer and all the second patterned mask to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench (Figs. 13 – 14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the method of Parries, further in view of Cai and Rauscher, to include Cai’s method of planarizing part of the insulating layer and all the second patterned mask to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench (Figs. 13 – 14), because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Cai’s semiconductor device is comparable to the semiconductor device of Parries, further in view of Cai and Rauscher, because both disclose methods of forming isolation structures; further, Cai demonstrates a production capability within the art to remove top layers from a substrate, where both disclose devices that are formed on/in a substrate. Therefore, it is within the capabilities of one of ordinary skill in the art to the method of Parries, further in view of Cai and Rauscher, to include Cai’s method of planarizing part of the insulating layer and all the second patterned mask to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench (Figs. 13 – 14) with the predictable result of planarizing a substrate surface.
Regarding dependent Claim 3, Parries, further in view of Cai and Rauscher, disclose the method of claim 1, wherein the mask layer comprises:
a first mask layer on the substrate (Parries: Fig. 1; pad nitride layer 20); and
a second mask layer (Parries: Fig. 1; oxide hard mask 22) on the first mask layer (Parries: Fig. 1).
Regarding dependent Claim 7, Parries, further in view of Cai and Rauscher, disclose the method of claim 1, further comprising:
forming the first patterned mask on the second patterned mask (Parries: Fig. 2);
using the first patterned mask as mask to remove the liner in the first trench (Yield through the combination of Parries and Rauscher; wherein Rauscher’s first patterned mask is taught to protect the liner in such a way that the first patterned mask is used to remove the liner in the first trench).
Regarding dependent Claim 8, Parries, further in view of Cai and Rauscher, disclose the method of claim 1, further comprising:
forming the insulating layer in the first trench and the second trench after
removing the first patterned mask (Parries: Fig. 5) and
performing a planarizing process (Parries: Fig. 6) to remove part of the insulating layer for forming the deep trench isolation structure.
Regarding dependent Claim 11, Parries, further in view of Cai and Rauscher, disclose the method of claim 1, wherein:
a width of the trap rich isolation structure is greater than a width of the deep trench isolation structure.
Parries teaches first trench 24 having a greater width than second trench 26 (Fig. 1).
Claims 4 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over Parries et al. (US 20120122303 A1), and further in view of Cai et al. (US 9202864 B2), Rauscher et al. (US 20070262411 A1), and Baars et al. (US 10103067 B1).
Regarding dependent Claim 4, Parries, further in view of Cai and Rauscher, disclose the method of claim 3; however, Parries remains silent wherein:
the first mask layer comprises silicon oxide and the second mask layer comprises silicon nitride.
However, in the same field of endeavor, Baars teaches oxide layer 4, taught as silicon oxide, and layer 5, taught as silicon nitride, (See col 6; lines 8 – 23); wherein oxide layer 4 is under layer 5. Thus, it would have been obvious to swap the order of Parries layer to yield the method for fabricating a semiconductor device wherein the first mask layer comprises silicon oxide and the second mask layer comprises silicon nitride.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the order of Parries’ first mask and second mask layers such that the first mask layer comprises silicon oxide and the second mask layer comprises silicon nitride, as disclosed by Baars, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Baars’ mask layer is comparable to Parries’ mask layer because they both are mask layers including a first mask layer and a second mask layer of materials including silicon oxide and silicon nitride. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the order of Parries’ first mask and second mask layers such that the first mask layer comprises silicon oxide and the second mask layer comprises silicon nitride, as disclosed by Baars, with the predictable result of providing protection to the substrate and the formed trenches and liners therein/thereon during further manufacturing, e.g., removing the liner from the first trench.
Regarding dependent Claim 5, Parries, further in view of Cai and Rauscher, disclose the method of claim 1; however, Parries remains silent regarding the method further comprising:
performing an oxidation process to oxidize sidewalls of the first trench and the second trench for forming the liner.
However, in the same field of endeavor, Baars teaches that the trenches can be lined with a silicon oxide liner formed by a thermal oxidation process (Col. 1; lines 39 – 41). Thus, Baars may be used to modify Parries liner such that the liner is formed performing an oxidation process to oxidize sidewalls of the first trench and the second trench for forming the liner.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Parries’ method of forming a liner to include Baars’ oxidation process, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Baars’ oxidation process is comparable to Parries’ method of forming a liner because they both result in a liner formed of similar materials, i.e., materials that function as liners. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Parries’ method of forming a liner to include Baars’ oxidation process with the predictable result of forming a liner.
Regarding dependent Claim 6, Parries, further in view of Cai, Rauscher, and Baars, disclose the method of claim 5 wherein:
the liner comprises silicon oxide (Baars: Col. 1; lines 39 – 41).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent, in no particular hierarchy of importance, relevance, or similarity, to the applicant’s disclosure:
US 20150279879 A1 – formally relied upon in previous office actions.
US 20180315747 A1 – formally relied upon in previous office actions.
CN 103151293 A – formally relied upon in previous office actions.
US 20120025199 A1 – formally relied upon in previous office actions.
US 10043812 B1 – formally relied upon in previous office actions.
US 6096621 A – formally relied upon in previous office actions regarding U.S. application 17380057.
US 20140353792 A1 – teaches a similar semiconductor device structure with deep extending trenches containing traps.
US 20130084689 A1 –teaches isolated stacks comprising a trap rich layer.
US 20160372592 A1 –teaches a similar method for forming a similar semiconductor device comprising similar materials and structure.
US 20180096884 A1 –teaches a similar method for forming a similar semiconductor device comprising similar materials and structure; specifically addressing new limitations introduced by continuation in part.
US 20130134511 A1 –teaches similar structures comprising similar materials for achieving trench isolation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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