Prosecution Insights
Last updated: May 29, 2026
Application No. 17/380,643

HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM

Non-Final OA §102§103
Filed
Jul 20, 2021
Priority
Jul 21, 2006 — divisional of 7999383 +7 more
Examiner
WARREN, MATTHEW E
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Gula Consulting Limited Liability Company
OA Round
6 (Non-Final)
88%
Grant Probability
Favorable
6-7
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
867 granted / 991 resolved
+19.5% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
26 currently pending
Career history
1014
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
70.3%
+30.3% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 991 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the Remarks filed October 27, 2025. Response to Arguments Applicant’s arguments, filed on October 27, 2025, with respect to the rejection(s) of claim(s) 1-12 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. A new grounds of rejection is made below. Claim Rejections - 35 USC § 103 The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-12, are rejected under pre-AIA 35 U.S.C. 102 (b) as being anticipated by Voldman (US Pub. 2007/0029646 A1) in view of Douglass (US 5,786,979) , and Lien et al. (US Pub. 2005/0082075 A1). In re claim 1, Voldman shows (figs. 5 and 6) a system comprising: a first die (3) comprising a downwardly-facing surface and a plurality of conducting layers (34, 38, 46); a first inductive coupling portion (38 as part of 45 or I) arranged along the downwardly-facing surface of the first die in at least one of the plurality of conducting layers of the first die; a second inductive coupling portion (46 as part of 45 or I) configured to couple the first die to another coupling portion (at interconnect 53) and a second die (5) including a third inductive coupling portion (66) arranged along an upwardly-facing surface of the second die, a plurality of In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B). However, Douglass also shows (fig. 7) a system comprising a first inductive coupling portion (712) and a second inductive coupling portion (714) on a first die (712). The first coupling portion couples to a third inductive coupling portion (708) of a third die (704). The second coupling portion couples to another coupling portion (710) of a fourth die (706). With this configuration, multiple, separate couplings can be made to a plurality of devices. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Voldman by forming second coupling portion on the die as taught by Douglass to provide multiple connections to a plurality of devices. Voldman and Douglass show all of the elements of the claims except the second die includes a plurality of silicide layers. The limitations are not patentably distinguishable over the cited prior art because it is well known in the art that silicide is used for electrical connections particularly in modifying the resistance of conductive lines and interconnections. However, Lien et al. discloses [0032] a semiconductor device comprising an inductor (fig. 1a; 106) comprising electrically conductive silicide materials. The silicide layers are suitable for use as conductive layers to form the inductor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made the semiconductor device of Voldman and Douglass by using a plurality of silicide layer since Lien teaches that silicide is suitable for use as an inductor conductive material. In re claims 2-12, the combined references of Voldman, Douglass, Lien, and Bhatt show all of the elements of the claims. Voldman et al. shows (figs. 5 and 6) all of the elements of the claims including the downwardly-facing surface of the first die (3) and the upwardly-facing surface of the second die (5) are separated by an interface material comprising (not labeled, on layer 32) at least one of a heat conductor or an interposer. Douglass shows (fig. 7) that an interface material is not present in a region between the first inductive coupling portion and the third inductive coupling portion. The first inductive coupling portion comprises a spiral inductor and the third inductive coupling portion comprises a spiral inductor (see figs. 3-4 of Douglass). The spiral inductor of the first inductive coupling portion spans only one conducting layer in the first die; and the spiral inductor of the third inductive coupling portion spans only one conducting layer in the second die (as shown in figs. 3-4 of Douglass). Response to Arguments Applicant’s arguments with respect to claims 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Show 11 earlier events
Nov 04, 2024
Response Filed
Feb 05, 2025
Final Rejection mailed — §102, §103
Apr 07, 2025
Response after Non-Final Action
May 27, 2025
Request for Continued Examination
May 28, 2025
Response after Non-Final Action
Jun 11, 2025
Non-Final Rejection mailed — §102, §103
Oct 27, 2025
Response Filed
Feb 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641771
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
3y 8m to grant Granted May 26, 2026
Patent 12641794
SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC LAYER AND METHOD OF MANUFACTURING THE SAME
3y 1m to grant Granted May 26, 2026
Patent 12635142
THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING HORIZONTAL CHANNEL REGION
3y 6m to grant Granted May 19, 2026
Patent 12635228
POWER SEMICONDUCTOR DEVICE
2y 9m to grant Granted May 19, 2026
Patent 12628522
DISPLAY PANEL AND DISPLAY DEVICE
2y 6m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

6-7
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.6%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 991 resolved cases by this examiner. Grant probability derived from career allowance rate.

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