DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 6/17/26. Currently, claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The rejection of claim(s) 1, 17, 18 and 20 under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US PGPub 2019/0254173, hereinafter referred to as “Chang”) has been maintained for reasons of record.
Chang discloses the semiconductor device as claimed. See figures 1-7 and corresponding text, where Chang teaches, in claim 1, a semiconductor device comprising:
a frontside (F) and a backside (BS);
four sidewalls (F, BS, TS, and B); and
a first solder (50) or glue connection on the frontside (left of component) and a second solder (50) or glue connection on the backside (right of component), wherein the semiconductor device (30) is connected to a printed circuit board (20) via one of the four sidewalls (F, BS, TS, and B), so that the first solder (50) or glue connection and the second solder (50) or glue connection are visible for a visual solder or glue inspection (figure 3; [0023]). (See modified illustration below.)
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Chang teaches, in claim 17, wherein the semiconductor device further comprises a solder pad on the one sidewall connecting the semiconductor device (30) to the printed circuit (20) (figures 1 and 3; [0023-0024]).
Chang teaches, in claim 18, further comprising an open contact on the frontside and an open contact on the backside (figures 1 and 3; [0023-0024]).
Chang teaches, in claim 20, wherein the frontside and the backside are wettable flanks, and wherein the semiconductor device is mounted to by the one sidewall to the printed circuit at an angle of 90o (figure 3; [0023])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The rejection of claim(s) 2-8 and 19 under 35 U.S.C. 103 as being unpatentable over Chang et al. (US PGPub 2019/0254173, hereinafter referred to as “Chang”) as applied to claim 1 above, and further in view of Hable et al. (US PGPub 2018/022720, hereinafter referred to as “Hable”) have been maintain for reasons record.
Chang discloses the semiconductor device substantially as claimed. See the rejection above.
However, Chang fails explicitly to show, in claim 2, wherein the semiconductor device further comprises an isolating layer on the four sidewalls.
Hable teaches, in claim 2, a semiconductor device that is encapsulated by a ceramic material ([0039-0041]). In addition, Hable provides the advantages of improving electrical reliability and integrity of the package ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art at the invention was filed, to incorporate wherein the semiconductor device further comprises an isolating layer on the four sidewalls, in the device of Chang, according to the teachings of Hable, with the motivation of improving electrical reliability and integrity of the package.
Chang fails to show, in claim 3, wherein the isolating layer is a ceramic, parylene or equivalent coating.
Hable teaches, in claim 3, a semiconductor device that is encapsulated by a ceramic material ([0039-0041]). In addition, Hable provides the advantages of improving electrical reliability and integrity of the package ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art at the invention was filed, to incorporate wherein the isolating layer is a ceramic, parylene or equivalent coating, in the device of Chang, according to the teachings of Hable, with the motivation of improving electrical reliability and integrity of the package.
Chang fails to show, in claim 4, wherein the isolating layer is a mould.
Hable teaches, in claim 4, a semiconductor device that is encapsulated by a ceramic material ([0039-0041]). In addition, Hable provides the advantages of improving electrical reliability and integrity of the package ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art at the invention was filed, to incorporate wherein the isolating layer is a mould, in the device of Chang, according to the teachings of Hable, with the motivation of improving electrical reliability and integrity of the package.
Chang fails to show, in claims 5-8, an automotive part comprising a semiconductor device.
Hable teaches, in claims 5-8, an automotive part comprising a semiconductor device (figure 8; [0041], [0095]). In addition, Hable provides the advantages of improving parasitic inductances and electrical reliability ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art at the invention was filed, to incorporate wherein the isolating layer is a mould, in the device of Chang, according to the teachings of Hable, with the motivation of improving parasitic inductances and electrical reliability.
Chang fails to show, in claim 19, further comprising an isolating layer on the four sidewalls that protect non-contact areas of the semiconductor device mounted to the printed circuit by the one sidewall are protected by the isolating layer.
Hable teaches, in claim 10, a semiconductor device that is encapsulated by a ceramic material ([0039-0041]). In addition, Hable provides the advantages of improving electrical reliability and integrity of the package ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art at the invention was filed, to incorporate further comprising an isolating layer on the four sidewalls that protect non-contact areas of the semiconductor device mounted to the printed circuit by the one sidewall are protected by the isolating layer, in the device of Chang, according to the teachings of Hable, with the motivation of improving electrical reliability and integrity of the package.
Response to Arguments
Applicant's arguments filed 6/17/26 have been fully considered but they are not persuasive. In the remarks applicant raises the clear issue as to whether Chang alone or in combination with Hable suggest four sidewalls; wherein the semiconductor device is connected to a printed circuit board via one of the four sidewalls, so that the first solder or glue connection and the second solder or glue inspection. In addition, applicant argues that the examiner interpretation is inconsistent with the broadest reasonable interpretation with the interpretation.
The examiner views that the examiner’s broadest interpretation is proper in light of the specification. Specifically, in applicant’s own disclosure in paragraph [0036] “frontside 206, a backside 208 a first sidewall 214 and a second sidewall 216. The other two sidewalls are not visible in FIG.2. The semiconductor device further comprises a first solder connection 210 on the frontside 206 and a second solder connection 212 on the backside 208. The semiconductor device 200 is connected to printed circuit board 202 via the first sidewall 214 or via the second sidewall 216 or via other two sidewalls that are not visible in FIG. 2.” Chang teaches the sidewalls where the first and/or second sidewalls connect the semiconductor device to the circuit board (see rejection and modified figure above). In addition, Chang teaches sidewalls that are not visible that are also connected to the circuit board, thus meets the claimed invention (see rejection and modified figure above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 August 26, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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