DETAILED ACTION
The Amendment (after RCE) filed February 19, 2026 has been entered. Claims 1-79 are pending. Claims 1-51 were cancelled. Claim 79 has been added. Claim 52 is independent.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Independent claims 52-78 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-32 of US Patent No. 10,847,195.
Instant Application
US Patent 10,847,195
Comment
Claim 52. A memory module comprising:
a first memory device including a first rank controlled by a first rank selection signal and configured to perform a memory access operation; and
a second memory device including a second rank controlled by a second rank selection signal and configured to perform a termination operation while the first memory device performs the memory access operation,
wherein the termination operation is triggered when the second rank selection signal is maintained during two successive edges of a clock signal.
Claim 1. A semiconductor device comprising:
a first rank configured to operate in synchronization with a clock signal in response to a first rank selection
signal; and
a second rank configured to operate in synchronization with the clock signal in response to a second rank selection signal,
wherein the first rank performs a termination operation by
blocking an internal control operation if both a value of the first rank selection sampled by a first edge of the clock signal and a value of the first rank selection
sampled by a second edge of the clock signal have an enabled state.
Note footnote1
Independent claims 52-78 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-29 of US Patent No. 10,373,662.
Instant Application
US Patent 10,373,662
Comment
Claim 52. A memory module comprising:
a first memory device including a first rank controlled by a first rank selection signal and configured to perform a memory access operation; and
a second memory device including a second rank controlled by a second rank selection signal and configured to perform a termination operation while the first memory device performs the memory access operation,
wherein the termination operation is triggered when the second rank selection signal is maintained during two successive edges of a clock signal.
Claim 1. A semiconductor device comprising:
a first rank configured to operate in synchronization with a clock signal in response to a first rank selection
signal; and
a second rank configured to operate in synchronization
with the clock signal in response to a second rank selection signal,
wherein the first rank generates a command for execution of an internal control operation and a termination command for execution of a termination operation based on the first rank selection signal,
wherein the first rank generates the termination command
and terminates generation of the command when the first rank selection signal is enabled during an Nth period of the clock signal, and N is a natural number
greater than or equal to 2.
Note footnote1
Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 52-79 rejected under AIA 35 U.S.C. 103 as being unpatentable over Kyung (US 2003/0099138) in view of e.g., Goh et al. (US 2018/0324951).
Regarding independent claim 52, Kyung teaches a memory module (see FIG. 4) comprising:
a first memory rank (460 or 470) including a first memory device (440, para. 0035: a first memory module 440 in which DRAMs 460 and 470 are mounted) controlled by a first rank selection signal (ATC_0) and configured to perform a memory access operation (see para. 0035-38, especially para. 0038: … data is written to or rad from the DRAMs 460 and 470 …); and
a second memory rank (480 or 490) including a second memory device (450) controlled by a second rank selection signal (ATC_1) and configured to perform a termination operation while the first memory device performs the memory access (see para. 0035-38, especially para. 0038: … a second control signal ATC_1 for enabling the active terminators …),
wherein the termination operation is triggered when the second rank selection signal is maintained during two successive edges of a clock signal (see FIGS. 7A-10C).
wherein the first memory device and the second memory device are mounted in or on (para. 0035: The memory modules 440 and 450 may be mounted in card slots (not shown) of the memory system 400) the memory module.
Kyung’s teaching regarding “in card slots” does not clearly describe the memory module.
However, memory devices mounted in or on the memory module is a well-known technology for a type of memory device for its purpose.
For support, of the above asserted facts, see for example, Goh et al. teach the deficiencies in e.g., FIG. 2 and accompanying disclosure, e.g.., para. 0024, i.e., a first memory module 35 (corresponding to Kyung’s first module 440) and a second memory module 36 (corresponding to Kyung’s second module 450) are mounted to the printed circuit board, i.e., claimed memory module 35 and 36 are mounted on the memory mother board 31.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Goh et al. to the teaching of Kyung such that a memory module, as taught by Kyung, utilizes mounted in a module, as taught by Goh et al., for the purpose of enabling enhancing package.
Regarding claim 53, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the memory access operation and the termination operation are performed simultaneously (FIG. 4 and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 54, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the first memory device is configured to operate in synchronization with a clock signal in response to a first rank selection signal (FIGS. 7A-10C).
Regarding claim 55, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the first memory device is configured to perform the memory access operation when successive values of the first rank selection that are sampled during two successive edges of the clock signal have changed (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure).
Regarding claim 56, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device is configured to operate in synchronization with the clock signal in response to the second rank selection signal (FIGS. 7A-10C).
Regarding claim 57, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device is configured to block an internal control operation when the second memory device performs the termination operation (FIG. 4 and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 58, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device is configured to block an internal control operation when successive values of the second rank selection that are sampled during two successive edges of the clock signal have been maintained (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 59, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device comprises a command circuit: wherein the command circuit configured to generate a command for execution of the internal control operation and a termination command for execution of the termination operation based on the second rank selection signal (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 60, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device comprising a command circuit: wherein the command circuit configured to generate a termination command and terminate generation of a command when the second rank selection signal is enabled during an Nth period of the clock signal (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 61, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung’s termination operation on memory module do not explicitly mention the termination operation includes an ODT operation.
However, memory module, especially DRAM, termination operation comprises on-die-termination operation is a well-known technology for a type of memory (e.g., DRAM) for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize ODT operation in memory module termination operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 62, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device comprise a clock circuit: wherein the clock circuit is configured to receive the clock signal and provide a first internal clock signal and a second internal clock signal; and wherein the first internal clock signal has substantially twice cycle time of the clock signal (see e.g., FIG. 4 along with FIGS. 7A-10C).
Regarding claim 63, Kyung and Goh et al, as combined, teach the limitations of claim 62.
Kyung further teaches the first internal clock signal and the second internal clock signal have substantially same cycle time (see e.g., FIG. 4 along with FIGS. 7A-10C).
Regarding claim 64, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teach the second memory device comprises a clock circuit: wherein the clock circuit is configured to receive the clock signal; and wherein the clock signal includes a differential clock signal (see e.g., FIG. 4 along with FIGS. 7A-10C).
Kyung’s clock does not explicitly disclose a differential clock signal.
However, clock and complimentary clock signal utilized in memory operation is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a differential clock signal in memory because these conventional technology are well established in the art of the memory devices.
Regarding claim 65, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device comprise a command circuit: wherein the command circuit configured to input a first internal clock signal and a second internal clock signal and generate a first signal and a second signal based on an internal clock signal (see e.g., FIG. 4 along with FIGS. 7A-10C).
Regarding claim 66, Kyung and Goh et al, as combined, teach the limitations of claim 65.
Kyung further teaches the command circuit is configured to output the first signal or the second signal (FIGS. 4, 11 ,17).
Regarding claim 67, Kyung and Goh et al, as combined, teach the limitations of claim 65.
Kyung further teaches the command circuit is configured to generate the first signal and the second signal (FIGS. 4, 11 ,17).
Regarding claim 68, Kyung and Goh et al, as combined, teach the limitations of claim 65.
Kyung further teaches the command circuit is configured to change the first signal based a rank selection signal (FIGS. 4, 11 ,17).
Regarding claim 69, Kyung and Goh et al, as combined, teach the limitations of claim 65.
Kyung further teaches the command circuit is configured to latch a command/address signal and decode the command/address signal to generate the first signal and the second signal (FIGS. 4, 11 ,17).
Regarding claim 70, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the memory access operation includes at least one among memory read operation, memory write operation, register read operation and register write operation (FIGS. 4, 11 ,17, and accompanying disclosure).
Regarding claim 71, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device performs the termination operation only when the memory access operation includes one among read operation, write operation and register access operation (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 72, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the first memory device produces a third signal that triggers an internal operation and a fourth signal that triggers the termination operation while the second memory device produces a first signal and a second signal (FIGS. 4, 11 ,17, and accompanying disclosure).
Regarding claim 73, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the first memory device receives a command/address signal that is received by same with that of which the second memory device receives (FIGS. 4, 11 ,17, and accompanying disclosure).
Regarding claim 74, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device configured to perform the termination operation based on internal clock signals and a second signal (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure).
Regarding claim 75, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches a command and address signal is connected to the first memory device and the second memory device (FIGS. 4, 11 ,17, and accompanying disclosure).
Regarding claim 76, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device comprising: a clock circuit configured to produce a first internal clock signal and a second internal clock signal, and a command circuit configured to produce a first signal that triggers an internal operation and a second signal that triggers the termination operation (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure).
Regarding claim 77, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches a semiconductor device comprises the first memory device and the second memory device, wherein the first memory device includes a first rank and the second memory device includes the second rank (FIGS. 4, 11 ,17, and accompanying disclosure).
Regarding claim 78, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the second memory device performs the termination operation when the memory access operation includes one among read operation, write operation, and register access operation (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure, e.g., para. 0035-38).
Regarding claim 79, Kyung and Goh et al, as combined, teach the limitations of claim 52.
Kyung further teaches the first memory device performs the memory access operation in response to a command/address signal, and the second memory device performs the termination operation in response to the command/address signal (see e.g., FIG. 4 along with FIGS. 7A-10C, and accompanying disclosure; further memory operations performed in response to commands and/or addresses are well-known technologies in the field of semiconductor memory).
Response to Argument
Applicant’s arguments filed 02/19/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
1 Re independent claim 52, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights