Tech Center 2800 • Art Units: 2825
This examiner grants 91% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 19117386 | POWER SUPPLY CONTROL CIRCUIT, METHOD AND APPARATUS FOR STORAGE SYSTEM, AND STORAGE MEDIUM | Non-Final OA | SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD. |
| 18771863 | MEMORY CELL ARRAY AND METHOD OF OPERATING SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18769407 | MEMORY DEVICE INCLUDING DUAL CONTROL CIRCUITS | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
| 18758504 | NEW WAS CELL FOR SRAM HIGH-R ISSUE IN ADVANCED TECHNOLOGY NODE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18748972 | MEMORY CIRCUITS AND METHODS FOR OPERATING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18739538 | Device and Method for Reading a Memory Cell | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18755062 | PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES | Non-Final OA | Micron Technology, Inc. |
| 18791901 | SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULATION FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM) | Non-Final OA | STMicroelectronics International N.V. |
| 18522547 | BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT | Final Rejection | STMicroelectronics International N.V. |
| 18739363 | PRE-CHARGE SYSTEM FOR PERFORMING TIME-DIVISION PRE-CHARGE UPON BIT-LINE GROUPS OF MEMORY ARRAY AND ASSOCIATED PRE-CHARGE METHOD | Non-Final OA | MEDIATEK INC. |
| 18444754 | NEGATIVE BIT LINE CONTROL MECHANISM | Final Rejection | MEDIATEK INC. |
| 18545370 | SEMICONDUCTOR DEVICE | Non-Final OA | SK hynix Inc. |
| 18643674 | SENSE AMPLIFIER FOR ACTIVE STANDBY OPERATION | Non-Final OA | Rambus Inc. |
| 18355359 | MULTI-TIME PROGRAMMABLE MEMORY DEVICES AND METHODS | Non-Final OA | Sandisk Technologies, Inc. |
| 18571407 | AUGMENTED MEMORY COMPUTING: A NEW PATHWAY FOR EFFICIENT AI COMPUTATIONS | Non-Final OA | UNIVERSITY OF SOUTHERN CALIFORNIA |
| 18506989 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH WELL TAP CELLS | Non-Final OA | Socionext Inc. |
| 18637823 | DELTA-SIGMA MODULATOR-BASED VARIABLE-RESOLUTION ACTIVATION IN-MEMORY COMPUTING MACRO | Non-Final OA | THE RESEARCH FOUNDATION FOR THE STATE UNIVERISTY OF NEW YORK |
| 18626860 | Reconfigurable Compute Memory Having Selection Logic to Control Compute Operations | Final Rejection | NUMEM Inc. |
| 18588007 | SFGT STORAGE ARRAY, STORAGE CHIP AND DATA-READING METHOD | Non-Final OA | XI'AN UNIIC SEMICONDUCTORS CO., LTD. |
| 18418060 | OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY | Non-Final OA | FlashSilicon Incorporation |
| 18047097 | WORD LINE VOLTAGE DETECTION CIRCUIT FOR ENCHANCED READ OPERATION | Non-Final OA | Intel NDTM US LLC |
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