DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-19 are pending.
Claim 20 is cancelled.
Claims 1, 9 and 19 are currently amended.
Claims 2-4, 7-8, 10-12 and 15-16 are original.
Claims 5-6, 13-14 and 17-18 are previously presented.
Claims 1-19 are rejected herein.
Response to Arguments
Applicant’s arguments, see pages 11-16, filed 11/25/2025, with respect to the rejections under 35 U.S.C. have been fully considered and are persuasive. The rejections under 35 U.S.C. of 09/04/2025 has been withdrawn.
Otherwise, Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive.
Applicant argues that the coaxial connection (312) of Kim “does not ‘pass through multiple metal layers’.” Remarks, page 19. This argument is not persuasive. Notably, Kim has not been applied for teaching a coaxial connection passing through multiple metal layers. In any event, Rodriguez discloses the column (116), the resin sheath (110), and the ground shield pass through multiple layers (107) of the substrate (100, 100’, 100’’). Rodriguez refers to the multiple layers (107) as “ground planes” that may be electrically coupled to the outer ground structure. See, e.g., paragraph [0020]. Ganesan discloses using metal for ground planes. Accordingly, Rodriguez in view of Ganesan discloses the column, the resin sheath, and the ground shield pass through multiple metal layers of the substrate, as claimed.
Applicant argues that “the annotated image of Kim provided by the Office is not what is disclosed in Kim, but instead is a modification made by the Office.” Remarks, page 19. This argument is not persuasive. Notably, the annotations added to the image of Kim do not “modify” the illustrated structures of Kim in any way. Rather, the annotations provided to the image of Kim merely attach certain reference characters to parts and/or structures of Kim that are clearly illustrated but otherwise lack identifying reference character, so that such parts and/or structures can be more easily referenced throughout the Office Action.
Applicant argues that “there is no disclosure or suggestion in Rodriguez of a sense line.” Remarks, page 19. This argument is not persuasive. Notably, Rodriguez has not been applied for teaching a sense line. In any event, Kim discloses a plurality of sense lines (314’, 315’) including a first sense line (315’) and a second sense line (314’). Sturcken further discloses first and second sense lines (i.e., “separate supply voltage sense and ground reference sense lines”) that are coupled to a power distribution network (PDN) to monitor voltage on the PDN.
Applicant appears to argue that Rodriguez is not analogous art because it is not in the same field of endeavor. Remarks, page 20. This argument is not persuasive. Indeed, Applicant’s specification explicitly states that “[a]spects of this disclosure relate generally to an integrated circuit” (paragraph [0001]). Further, claim 1 of the present Application, for example, is directed to an apparatus comprising a semiconductor device including a substrate. Notably, Rodriguez explicitly discloses:
“[0012] Various implementations of the embodiments herein may be formed or carried out on a substrate, such as a package substrate. A package substrate may comprise any suitable type of substrate capable of providing electrical communications between a die, such as an integrated circuit (IC) die, and a next-level component to which an IC package may be coupled (e.g., a circuit board). In another embodiment, the substrate may comprise any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled with a lower IC/die package, and in a further embodiment a substrate may comprise any suitable type of substrate capable of providing electrical communication between an upper IC package and a next-level component to which an IC package is coupled.”
Accordingly, Rodriguez is found to be analogous art in the same field of endeavor, namely, IC devices.
Applicant argues that Ganesan has been “used to teach multiple metal layers” and that one of ordinary skill in the art would not look to Ganesan to modify Rodriguez. Remarks, pages 20-21. This argument is not persuasive and is again a mischaracterization of the combination. Notably, Rodriguez discloses that the multiple layers (107) are ground planes that may be electrically coupled to the outer ground structure. See, e.g., paragraph [0020]. Yet, Rodriguez does not explicitly disclose that the multiple layers (107) are metal. Ganesan (in analogous art, i.e., in the field of endeavor of “electronic packages” and “semiconductor devices” – see Abstract and paragraph [0001]) discloses that metal is a known and suitable material for ground planes. That is to say, Ganesan is not “used to teach multiple metal layers” as the Applicant alleges, but rather Ganesan is used to teach that metal is a known and suitable material for ground planes in electronic packages and/or semiconductor device, e.g., such as the ground planes disclosed in Rodriguez. Indeed, one of ordinary skill in the art would look to Ganesan to find and/or select a known and suitable material to use for the ground planes disclosed by Rodriguez.
Applicant also argues that one of ordinary skill in the art would not look to Kang to modify Rodriguez. Remarks, page 21. This argument is also not persuasive. Indeed, Rodriguez discloses laminating sub-laminate boards and that an “opening may be formed through a portion of the resin, wherein a conductive coaxial via may be formed in the opening.” Paragraph [0026]. One of ordinary skill in the art would look to Kang for a suitable material to fill the via opening disclosed by Rodrigues, at least insomuch as Kang discloses an electrically conducting paste material expressly for via filling. See, e.g., Title and Abstract. Kang further discloses that the electrically conductive materials for via fill applications achieve good reliability, low shrinkage, good electrical continuity and/or other desired properties (see, e.g., pages 889 and 890) and that formulations have been produced to fill via holes with high aspect ratios (see, e.g., Abstract).
Applicant argues that “[t]he Office goes on to allege that one of ordinary skill in the art … would replace the coaxial via/interconnect of Rodriguez with the coaxial interconnect disclosed by Kim.” Remarks, page 21. This argument is not persuasive and is a mischaracterization of the proposed combination. Indeed, in the outstanding rejection, the proposed combination is to include sense lines as taught by Kim in the device of Rodriguez. Nowhere does the prior or current Office Action suggest replacing the coaxial via/interconnect of Rodriguez with the coaxial interconnect disclosed by Kim.
Applicant argues that “Kim's coaxial interconnect structure is completely different than that disclosed in Rodriguez” and “[a]ny alleged combination would eliminate the key technical features disclosed by Rodriguez.” Remarks, page 21. This argument is not persuasive.
First, the allegation that Kim's coaxial interconnect structure is “completely” different than that disclosed in Rodriguez is erroneous. Indeed, the coaxial interconnect structures are very similar in that they both include a central column as claimed, they both include dielectric resin sheaths surrounding the column as claimed and they both include ground shields surrounding the sheath, as claimed.
Second, the proposed combination would not eliminate the key technical features disclosed by Rodriguez. Indeed, the horse shoe structure (112) of Rodriguez is not eliminated nor is Rodriguez rendered unsatisfactory for its intended purpose of providing a coaxial via structure by the incorporation of sense lines as taught by Kim in the device of Rodriguez. Indeed, Rodriguez expressly acknowledges that coaxial via structures may be used to transfer power and signals vertically through microelectronic packages. See, e.g., paragraph [0001].
Applicant further argues that “there are no disclosure of sense lines in Rodriguez, PDN or power controller / regulator and hence no disclosure or motivation couple non-existent sense lines to a power distribution network (PDN) to monitor voltage on the PDN in a portion of the substrate.” Remarks, page 22. This argument is not persuasive.
Indeed, as more fully described below herein, it would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a plurality of sense lines including a first sense line and a second sense line in the device of Rodriguez as taught by Kim, for example, to provide power and ground signals through a coaxial connection. See, e.g., paragraph [0039] of Kim. Additionally, as more fully described herein, it would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the first and second sense lines to monitor voltage on the PDN in a portion of the substrate as taught by Sturcken, for example, in order to provide feedback control for an output voltage so that the output voltage equals a target output voltage. See, e.g., paragraph [0055] of Sturcken.
Applicant argues that “[t]he remaining references (Sun and Lo), as applied, fail to cure the above-noted deficiencies in the alleged combination of Rodriguez, Kang, Ganesan. Kim and Sturcken.” Remarks, page 22. This argument is not persuasive. In particular, the alleged “above-noted deficiencies” have not been found persuasive and neither Sun nor Lo has been applied for the purpose of curing any alleged deficiency noted in Applicant’s arguments. Rather, Sun has been referenced for teaching a coreless substrate for semiconductor packaging applications, and Lo has been referenced for teaching a PMIC.
Applicant argues that “[i]ndependent claim 9 and independent claim 19, recite similar features and are therefore allowable at least for similar reasons as independent claim 1.” Remarks, page 23. This argument is not persuasive. Notably, the reasons Applicant has argued for the allowance of claim 1 have not been found persuasive and independent claim 1 has not been found allowable. Accordingly, similarity to claim 1 is therefore a not a persuasive argument for the allowance of independent claims 9 and 19.
Finally, Applicant argues that the dependent claims are “likewise allowable at least by virtue of their dependence upon one of the above-noted independent claims” and that the dependent claims “recite additional subject matter, which is not believed suggested by the cited art taken either alone or in combination.” Remarks, page 23. This argument is not persuasive. First, the independent claims have not been found allowable and hence dependance therefrom is not itself a reason for the allowance of the dependent claims. Second, the Applicant has not identified how any “recited additional subject matter” of any dependent claim further distinguishes such dependent claim over the prior art of record, nor has Applicant identified how any rejection of any dependent claim is further in error.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “power rail” (e.g., as claimed in claim 19 – that is “in a portion of the substrate beneath and adjacent to the die”) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5-10 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez (US 20180184522 A1) in view of Kang (S. K. Kang et al., "Development of conductive adhesive materials for via fill applications," 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070), Las Vegas, NV, USA, 2000, pp. 887-891, doi: 10.1109/ECTC.2000.853269), Ganesan (US 20210028116 A1), Kim (US 20160013125 A1) and Sturcken (US 20200075541 A1).
Regarding claim 1, Rodriguez discloses (see generally, e.g., FIGS. 1a-d and 2):
An apparatus (FIGS. 1a-d) comprising:
a semiconductor device (130) including a substrate (100, 100’, 100’’), the substrate (100, 100’, 100’’) comprising:
a column (116);
a resin sheath (110) surrounding the column (116), wherein the resin sheath (110) comprises a dielectric material (see also, e.g., paragraph [0018] – “The resin material 110 may comprise a dielectric material, or another suitable electrically isolating material in other embodiments”); and
a ground shield (106) surrounding the resin sheath (110), wherein the column (116), the resin sheath (110), and the ground shield pass through multiple layers (107) of the substrate (100, 100’, 100’’).
Rodriguez further disclose laminating sub-laminate boards and that an “opening may be formed through a portion of the resin, wherein a conductive coaxial via may be formed in the opening.” Paragraph [0026]. Yet, Rodriguez does not explicitly disclose that the column comprises a conductive paste.
However, in analogous art, Kang discloses an electrically conducting paste material for via filling. See, e.g., Title and Abstract. Kang further discloses that the electrically conductive materials for via fill applications achieve good reliability, low shrinkage, good electrical continuity and/or other desired properties. See, e.g., pages 889 and 890. Kang discloses that formulations have been produced to fill via holes with high aspect ratios. See, e.g., Abstract.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the electrically conductive paste material as taught by Kang for the column (116) of Rodriguez according to known methods to yield predictable results, for example, to achieve a via with good reliability, low shrinkage, good electrical continuity and/or other desired properties.
Furthermore, Rodriguez refers to the multiple layers (107) as “ground planes” that may be electrically coupled to the outer ground structure. See, e.g., paragraph [0020]. Yet, Rodriguez does not explicitly disclose that the multiple layers (107) are metal.
However, in analogous art, Ganesan discloses a semiconductor package including a metal layer (372) disposed between dielectric layers (371) where the metal layer (372) may be a ground plane. See, e.g., FIG. 3A and paragraph [0048].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used metal for the multiple layers (107) of Rodriguez in accordance with the teachings of Ganesan according to known methods to yield predictable results, for example, to use a known material (i.e., metal) with good conductivity and/or other desired physical and/or electrical properties for the layers (107).
Rodriguez does not explicitly disclose:
a plurality of sense lines including a first sense line and a second sense line, wherein the first sense line is connected to the column and the second sense line is connected to the ground shield,
wherein the first sense line is located in a different metal layer of the multiple metal layers than the second sense line; and
wherein the first sense line and the second sense line are coupled to a power distribution network (PDN) to monitor voltage on the PDN in a portion of the substrate.
However, in analogous art, Kim discloses (see generally, e.g., annotated partial FIG. 3 herein and FIG. 4) a semiconductor device (300) including a coaxial connection (312) having a column (328’), a sheath (330) surrounding the column (328’), wherein the sheath comprises a dielectric material (paragraph [0039]), and a ground shield (332) surrounding the sheath (330). Kim further discloses:
a plurality of sense lines (314’, 315’) including a first sense line (315’) and a second sense line (314’), wherein the first sense line (315’) is connected to the column (328’) and the second sense line (314’) is connected to the ground shield (332),
wherein the first sense line (315’) is located in a different metal layer (ML1) of the multiple metal layers (ML1, ML2, ML3, ML4) than the second sense line (314’) (i.e., located in metal layer ML2); and
wherein the first sense line (315’) and the second sense line (314’) are coupled to a power distribution network (PDN). See, e.g., paragraphs [0043]-[0049].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a plurality of sense lines including a first sense line and a second sense line in the device of Rodriguez, wherein the first sense line is connected to the column (116) of Rodriguez and the second sense line is connected to the ground shield (106) of Rodriguez, wherein the first sense line is located in a different metal layer of the multiple metal layers than the second sense line, and wherein the first sense line and the second sense line are coupled to a power distribution network (PDN), as taught by Kim according to known methods to yield predictable results, for example, to provide power and ground signals through a coaxial connection. See, e.g., paragraph [0039] of Kim.
[AltContent: textbox (ANNOTATED PARTIAL FIG. 3 OF KIM)][AltContent: textbox (ML4)][AltContent: ][AltContent: textbox (ML3)][AltContent: ][AltContent: textbox (328’)][AltContent: textbox (314’)][AltContent: textbox (315’)][AltContent: textbox (ML1)][AltContent: textbox (ML2)][AltContent: ][AltContent: ][AltContent: rect]
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While Rodriguez in view of Kang, Ganesan and Kim discloses that the first sense line and the second sense line are coupled to a power distribution network (PDN), the combination does not explicitly disclose that the first sense line and the second sense line are coupled to a power distribution network (PDN) “to monitor voltage on the PDN in a portion of the substrate.”
However, in analogous art, Sturcken discloses first and second sense lines (i.e., “separate supply voltage sense and ground reference sense lines”) that are coupled to a power distribution network (PDN) to monitor voltage on the PDN in a portion of the substrate (“separate supply voltage sense and ground reference sense lines allow the power converter chiplet 60 to measure the output voltage at the load independent of the power delivery channel”). See, e.g., FIG. 6 and paragraph [0055].
Ra
Regarding claim 2, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez further discloses that the substrate (100, 100’, 100’’) comprises a cored substrate. Note, e.g., core material (104).
Regarding claim 5, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez does not explicitly disclose that the column has a diameter of 100 micrometers.
However, in analogous art, Kim discloses a coaxial connection (312) with a column (328) having a diameter (702) of 100 micrometers. See, e.g., FIGS. 3, 7A and 7B and paragraph [0062].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have the column (116) of Rodriguez have a diameter of about 100 micrometers as taught by Kim according to known methods to yield predictable results, for example, to meet a desired characteristic impedance value.
Regarding claim 6, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez does not explicitly disclose that the column, the resin sheath, and the ground shield combined occupy an area of 250 micrometers by 250 micrometers.
However, in analogous art, Kim discloses a coaxial connection (312) with a column (328) and sheath (330) that collectively have a diameter (704) of about 40-400 micrometers. See, e.g., FIGS. 3, 7A and 7B and paragraph [0062]. FIG. 7B further shows a relatively thin shield (712) as compared to the diameter of the column (328) and sheath (330). Accordingly, the column (328), sheath (330) and shield (712) as disclosed by Kim can collectively have a diameter of 250 µm, i.e., it occupies an area of about 250 micrometers by 250 micrometers. Moreover, under the broadest reasonable interpretation (BRI), “occupying an area” as claimed does not require a specified area be entirely occupied by a thing nor does it prohibit a thing occupying a specified area from extending beyond the specified area.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have the combined column (116), resin sheath (110) and ground shield (106) of Rodriguez occupy an area of 250 micrometers by 250 micrometers as taught by Kim according to known methods to yield predictable results, for example, to meet a desired characteristic impedance value and/or contain the structures within a desired area to allow an improved density of components and/or elements within a compact semiconductor package.
Regarding claim 7, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez further discloses a die (402) coupled to the semiconductor device (404). See, e.g., FIG. 4 and paragraph [0029] – “In the illustrated embodiment, the computing system 400 includes at least one die 402, disposed on a surface (such as on a top or bottom or side surface) of the substrate 404, such as a package substrate comprising the coaxial via structures/boards of the various embodiments herein.” Accordingly, the substrate 404 is disclosed as comprising the coaxial via structures/boards disclosed in FIGS. 1a-d and 2 (e.g., including elements 100, 100’, 100’’ and/or 130) connected to the die (402).
Regarding claim 8, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez further discloses that the apparatus is a mobile device. See, e.g., FIG. 4 and paragraph [0032].
Regarding claim 9, Rodriguez discloses (see generally, e.g., FIGS. 1a-d and 2):
A method of fabricating an apparatus (FIGS. 1a-d), the method comprising:
building up a substrate (100, 100’, 100’’) comprising:
forming a column (116);
forming a resin sheath (110) that surrounds the column (116), wherein the resin sheath (110) comprises a dielectric material (see also, e.g., paragraph [0018] – “The resin material 110 may comprise a dielectric material, or another suitable electrically isolating material in other embodiments”);
forming a ground shield (106) that surrounds the resin sheath (110), wherein the column (116), the resin sheath (110), and the ground shield (106) pass through multiple layers (107) of the substrate (100, 100’, 100’’); and
attaching a semiconductor device (400) to the substrate (100, 100’, 100’’).
See, e.g., FIG. 4 and paragraph [0029] – “In the illustrated embodiment, the computing system 400 includes at least one die 402, disposed on a surface (such as on a top or bottom or side surface) of the substrate 404, such as a package substrate comprising the coaxial via structures/boards of the various embodiments herein.” Accordingly, the substrate 404 is disclosed as comprising the coaxial via structures/boards disclosed in FIGS. 1a-d and 2 (e.g., including elements 100, 100’, 100’’ and/or 130) connected to the die (402).
Rodriguez further disclose laminating sub-laminate boards and that an “opening may be formed through a portion of the resin, wherein a conductive coaxial via may be formed in the opening.” Paragraph [0026]. Yet, Rodriguez does not explicitly disclose that the column comprises a conductive paste.
However, in analogous art, Kang discloses an electrically conducting paste material for via filling. See, e.g., Title and Abstract. Kang further discloses that the electrically conductive materials for via fill applications achieve good reliability, low shrinkage, good electrical continuity and/or other desired properties. See, e.g., pages 889 and 890. Kang discloses that formulations have been produced to fill via holes with high aspect ratios. See, e.g., Abstract.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the electrically conductive paste material as taught by Kang for the column (116) of Rodriguez according to known methods to yield predictable results, for example, to achieve a via with good reliability, low shrinkage, good electrical continuity and/or other desired properties.
Furthermore, Rodriguez refers to the multiple layers (107) as “ground planes” that may be electrically coupled to the outer ground structure. See, e.g., paragraph [0020]. Yet, Rodriguez does not explicitly disclose that the plurality of layers (107) are metal.
However, in analogous art, Ganesan discloses a semiconductor package including a metal layer (372) disposed between dielectric layers (371) where the metal layer (372) may be a ground plane. See, e.g., FIG. 3A and paragraph [0048].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used metal for the plurality of layers (107) of Rodriguez in accordance with the teachings of Ganesan according to known methods to yield predictable results, for example, to use a known material (i.e., metal) with good conductivity and/or other desired physical and/or electrical properties for the layers (107).
Rodriguez does not explicitly disclose:
forming a plurality of sense lines including a first sense line and a second sense line,
wherein the first sense line is connected to the column and the second sense line is connected to the ground shield,
wherein the first sense line is located in a different metal layer of the plurality of metal layers than the second sense line; and
wherein the first sense line and the second sense line are coupled to a power distribution network (PDN) to monitor voltage on the PDN in a portion of the substrate.
However, in analogous art, Kim discloses (see generally, e.g., annotated partial FIG. 3 herein and FIG. 4) a method of fabricating an apparatus (300) including a coaxial connection (312) having a column (328’), a sheath (330) surrounding the column (328’), wherein the sheath comprises a dielectric material (paragraph [0039]), and a ground shield (332) that surrounds the sheath (330). Kim further discloses:
forming a plurality of sense lines (314’, 315’) including a first sense line (315’) and a second sense line (314’),
wherein the first sense line (315’) is connected to the column (328’) and the second sense line (314’) is connected to the ground shield (332),
wherein the first sense line (315’) is located in a different metal layer (ML1) of the plurality of metal layers (ML1, ML2, ML3, ML4) than the second sense line (314’) (i.e., located in metal layer ML2); and
wherein the first sense line (315’) and the second sense line (314’) are coupled to a power distribution network (PDN). See, e.g., paragraphs [0043]-[0049].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a plurality of sense lines including a first sense line and a second sense line in the device of Rodriguez, wherein the first sense line is connected to the column (116) of Rodriguez and the second sense line is connected to the ground shield (106) of Rodriguez, wherein the first sense line is located in a different metal layer of the plurality of metal layers than the second sense line, and wherein the first sense line and the second sense line are coupled to a power distribution network (PDN), as taught by Kim according to known methods to yield predictable results, for example, to provide power and ground signals through a coaxial connection. See, e.g., paragraph [0039] of Kim.
While Rodriguez in view of Kang, Ganesan and Kim discloses that the first sense line and the second sense line are coupled to a power distribution network (PDN), the combination does not explicitly disclose that the first sense line and the second sense line are coupled to a power distribution network (PDN) “to monitor voltage on the PDN in a portion of the substrate.”
However, in analogous art, Sturcken discloses first and second sense lines (i.e., “separate supply voltage sense and ground reference sense lines”) that are coupled to a power distribution network (PDN) to monitor voltage on the PDN in a portion of the substrate. See, e.g., FIG. 6 and paragraph [0055].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the first and second sense lines in the device of Rodriguez (i.e., as modified in accordance with the teachings of Kang, Ganesan and Kim as detailed herein) to monitor voltage on the PDN in a portion of the substrate as taught by Sturcken according to known methods to yield predictable results, for example, in order to provide feedback control for an output voltage so that the output voltage equals a target output voltage. See, e.g., paragraph [0055] of Sturcken.
Regarding claim 10, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez further discloses that the substrate (100, 100’, 100’’) comprises a cored substrate. Note, e.g., core material (104).
Regarding claim 13, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez does not explicitly disclose that the column has a diameter of about 100 micrometers.
However, in analogous art, Kim discloses a coaxial connection (312) with a column (328) having a diameter (702) of 100 micrometers. See, e.g., FIGS. 3, 7A and 7B and paragraph [0062].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have the column (116) of Rodriguez have a diameter of 100 micrometers as taught by Kim according to known methods to yield predictable results, for example, to meet a desired characteristic impedance value.
Regarding claim 14, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez does not explicitly disclose that the column, the resin sheath, and the ground shield combined occupy an area of 250 micrometers by 250 micrometers.
However, in analogous art, Kim discloses a coaxial connection (312) with a column (328) and sheath (330) that collectively have a diameter (704) of about 40-400 micrometers. See, e.g., FIGS. 3, 7A and 7B and paragraph [0062]. FIG. 7B further shows a relatively thin shield (712) as compared to the diameter of the column (328) and sheath (330). Accordingly, the column (328), sheath (330) and shield (712) as disclosed by Kim can collectively have a diameter of 250 µm, i.e., it occupies an area of 250 micrometers by 250 micrometers. Moreover, under the broadest reasonable interpretation (BRI), “occupying an area” as claimed does not require a specified area be entirely occupied by a thing nor does it prohibit a thing occupying a specified area from extending beyond the specified area.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have the combined column (116), resin sheath (110) and ground shield (106) of Rodriguez occupy an area of 250 micrometers by 250 micrometers as taught by Kim according to known methods to yield predictable results, for example, to meet a desired characteristic impedance value and/or contain the structures within a desired area to allow an improved density of components and/or elements within a compact semiconductor package.
Regarding claim 15, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez further discloses coupling a die (402) to the semiconductor device (400). See, e.g., FIG. 4 and paragraph [0029] – “In the illustrated embodiment, the computing system 400 includes at least one die 402, disposed on a surface (such as on a top or bottom or side surface) of the substrate 404, such as a package substrate comprising the coaxial via structures/boards of the various embodiments herein.” Accordingly, the substrate 404 is disclosed as comprising the coaxial via structures/boards disclosed in FIGS. 1a-d and 2 (e.g., including elements 100, 100’, 100’’ and/or 130) connected to the die (402).
Regarding claim 16, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez further discloses including the semiconductor device (400) in an apparatus that is a mobile device. See, e.g., FIG. 4 and paragraph [0032].
Regarding claim 17, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Kim further discloses wherein the first sense line (315’) and the second sense line (314’) are low current sense lines. Note, Applicant’s admits (see, e.g., Remarks filed 06/25/2025, page 11) that “low current” is “inherent in the functioning of the sense lines to be able to monitor the voltage.”
Regarding claim 18, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Kim further discloses wherein the first sense line (315’) and the second sense line (314’) are low current sense lines. Note, Applicant’s admits (see, e.g., Remarks filed 06/25/2025, page 11) that “low current” is “inherent in the functioning of the sense lines to be able to monitor the voltage.”
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claims 1 and 9 respectively, and further in view of Sun (Sun, Yu et al. “Development of ultra-thin low warpage coreless substrate.” 2013 IEEE 63rd Electronic Components and Technology Conference (2013): 1846-1849).
Regarding claim 3, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez does not explicitly disclose that the substrate comprises a coreless substrate.
However, in analogous art, Sun discloses a coreless substrate for semiconductor packaging applications. See generally, e.g., Abstract and Introduction on page 1846.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a coreless substrate for the substrate (100, 100’, 100’’) of Rodriguez in accordance with the teachings of Sun according to known methods to yield predictable results, for example, to achieve a substrate with very low z-height, which means such substrate will be lighter, smaller and it will have very short interconnection, fine linewidth, and good power integrity. See, e.g., Abstract of Sun.
Regarding claim 11, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez does not explicitly disclose that the substrate comprises a coreless substrate.
However, in analogous art, Sun discloses a coreless substrate for semiconductor packaging applications. See generally, e.g., Abstract and Introduction on page 1846.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a coreless substrate for the substrate (100, 100’, 100’’) of Rodriguez in accordance with the teachings of Sun according to known methods to yield predictable results, for example, to achieve a substrate with very low z-height, which means such substrate will be lighter, smaller and it will have very short interconnection, fine linewidth, and good power integrity. See, e.g., Abstract of Sun.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claims 1 and 9 respectively, and further in view of Lo (US 20220068736 A1).
Regarding claim 4, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 1 discloses the apparatus of claim 1.
Rodriguez further discloses a die (402) coupled to a via (412) of a semiconductor device (404). Rodriguez also discloses that device (404) may comprise an interposer. See, e.g., FIG. 4 and paragraphs [0029] and [0031]. The via (412) is connected to the sense lines (314’, 315’) of Kim as detailed herein and the die (402) is accordingly coupled to at least one of the sense lines (314’, 315’). Note, paragraph [0029] – “In the illustrated embodiment, the computing system 400 includes at least one die 402, disposed on a surface (such as on a top or bottom or side surface) of the substrate 404, such as a package substrate comprising the coaxial via structures/boards of the various embodiments herein.” Accordingly, the substrate 404 is disclosed as comprising the coaxial via structures/boards disclosed in FIGS. 1a-d and 2.
Rodriguez does not explicitly disclose that the die (402) is a Power Management Integrated Circuit (PMIC).
However, in analogous art, Lo discloses a PMIC (50) coupled to an interposer (102). See, e.g., FIG. 3 and paragraph [0019] and [0029].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PMIC as the die (402) of Rodriguez in accordance with the teachings of Lo according to known methods to yield predictable results, for example, to provide power management within a semiconductor package.
Regarding claim 12, Rodriguez in view of Kang, Ganesan, Kim and Sturcken as applied to claim 9 discloses the method of claim 9.
Rodriguez further discloses a die (402) coupled to a via (412) of a semiconductor device (404). Rodriguez also discloses that device (404) may comprise an interposer. See, e.g., FIG. 4 and paragraphs [0029] and [0031]. The via (412) is connected to the sense lines (314’, 315’) of Kim as detailed herein and the die (402) is accordingly coupled to at least one of the sense lines (314’, 315’). Note, paragraph [0029] – “In the illustrated embodiment, the computing system 400 includes at least one die 402, disposed on a surface (such as on a top or bottom or side surface) of the substrate 404, such as a package substrate comprising the coaxial via structures/boards of the various embodiments herein.” Accordingly, the substrate 404 is disclosed as comprising the coaxial via structures/boards disclosed in FIGS. 1a-d and 2.
Rodriguez does not explicitly disclose that the die (402) is a Power Management Integrated Circuit (PMIC).
However, in analogous art, Lo discloses a PMIC (50) coupled to an interposer (102). See, e.g., FIG. 3 and paragraph [0019] and [0029].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PMIC as the die (402) of Rodriguez in accordance with the teachings of Lo according to known methods to yield predictable results, for example, to provide power management within a semiconductor package.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Kang, Ganesan, Kim, Sturcken, and Lo.
Regarding claim 19, Rodriguez discloses (see generally, e.g., FIGS. 1a-d and 2):
An apparatus (FIGS. 1a-d) comprising:
a die.
Note, Rodriguez discloses at least one die (402) (implying multiple dies) coupled to the semiconductor device (404). See, e.g., FIG. 4 and paragraph [0029] – “In the illustrated embodiment, the computing system 400 includes at least one die 402, disposed on a surface (such as on a top or bottom or side surface) of the substrate 404, such as a package substrate comprising the coaxial via structures/boards of the various embodiments herein.” Accordingly, the substrate 404 is disclosed as comprising the coaxial via structures/boards disclosed in FIGS. 1a-d and 2 (e.g., including elements 100, 100’, 100’’ and/or 130) connected to the die (402).
Rodriguez further discloses:
a substrate (100, 100’, 100’’) comprising:
a column (116);
a resin sheath (110) surrounding the column (116), wherein the resin sheath (110) comprises a dielectric material (see also, e.g., paragraph [0018] – “The resin material 110 may comprise a dielectric material, or another suitable electrically isolating material in other embodiments”), wherein the column (116) and the resin sheath (110), pass through multiple layers (107) of the substrate (100, 100’, 100’’); and
a ground shield (106) surrounding the resin sheath (110).
Rodriguez further disclose laminating sub-laminate boards and that an “opening may be formed through a portion of the resin, wherein a conductive coaxial via may be formed in the opening.” Paragraph [0026]. Yet, Rodriguez does not explicitly disclose that the column comprises a conductive paste.
However, in analogous art, Kang discloses an electrically conducting paste material for via filling. See, e.g., Title and Abstract. Kang further discloses that the electrically conductive materials for via fill applications achieve good reliability, low shrinkage, good electrical continuity and/or other desired properties. See, e.g., pages 889 and 890. Kang discloses that formulations have been produced to fill via holes with high aspect ratios. See, e.g., Abstract.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the electrically conductive paste material as taught by Kang for the column (116) of Rodriguez according to known methods to yield predictable results, for example, to achieve a via with good reliability, low shrinkage, good electrical continuity and/or other desired properties.
Furthermore, Rodriguez refers to the multiple layers (107) as “ground planes” that may be electrically coupled to the outer ground structure. See, e.g., paragraph [0020]. Yet, Rodriguez does not explicitly disclose that the multiple layers (107) are metal.
However, in analogous art, Ganesan discloses a semiconductor package including a metal layer (372) disposed between dielectric layers (371) where the metal layer (372) may be a ground plane. See, e.g., FIG. 3A and paragraph [0048].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used metal for the multiple layers (107) of Rodriguez in accordance with the teachings of Ganesan according to known methods to yield predictable results, for example, to use a known material (i.e., metal) with good conductivity and/or other desired physical and/or electrical properties for the layers (107).
Rodriguez also disclose an active device. In particular, Rodriguez discloses at least one die (402) (implying multiple dies) of a semiconductor device (404).
Rodriguez does not explicitly disclose that at least one of the dies (402) is a Power Management Integrated Circuit (PMIC).
However, in analogous art, Lo discloses a PMIC (50) coupled to an interposer (102). See, e.g., FIG. 3 and paragraph [0019] and [0029].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PMIC as at least one of the dies (402) of Rodriguez in accordance with the teachings of Lo according to known methods to yield predictable results, for example, to provide power to the die through a power distribution network within a semiconductor package.
Rodriguez does not explicitly disclose:
a first sense line comprising the column and a second sense comprising the ground shield, wherein the first sense line and the second sense line are coupled to a power distribution network (PDN) to monitor voltage on a power rail in a portion of the substrate beneath and adjacent to the die to provide voltage feedback to the PMIC.
However, in analogous art, Kim discloses (see generally, e.g., annotated partial FIG. 3 herein and FIG. 4) a semiconductor device (300) including a coaxial connection (312) having a column (328’), a sheath (330) surrounding the column (328’), wherein the sheath comprises a dielectric material (paragraph [0039]), and a ground shield (332) surrounding the sheath (330). Kim further discloses:
a plurality of sense lines (314’, 315’) including a first sense line (315’) and a second sense line (314’), wherein the first sense line (315’) is connected to the column (328’) and the second sense line (314’) is connected to the ground shield (332),
wherein the first sense line (315’) and the second sense line (314’) are coupled to a power distribution network (PDN). See, e.g., paragraphs [0043]-[0049].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a first sense line and a second sense line in the device of Rodriguez as taught by Kim according to known methods to yield predictable results, for example, to provide power and ground signals through a coaxial connection. See, e.g., paragraph [0039] of Kim.
While Rodriguez in view of Kang, Ganesan and Kim discloses that the first sense line and the second sense line are coupled to a power distribution network (PDN), the combination does not explicitly disclose that the first sense line and the second sense line are coupled to the power distribution network (PDN) “to monitor voltage on a power rail in a portion of the substrate beneath and adjacent to the die to provide voltage feedback to the PMIC.”
However, in analogous art, Sturcken discloses first and second sense lines (i.e., “separate supply voltage sense and ground reference sense lines”) that are coupled to a power distribution network (PDN) to monitor voltage on a power rail (“separate supply voltage sense and ground reference sense lines allow the power converter chiplet 60 to measure the output voltage at the load independent of the power delivery channel”) in a portion of the of the substrate. See, e.g., FIG. 6 and paragraph [0055].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the first and second sense lines in the device of Rodriguez (i.e., as modified in accordance with the teachings of Kang, Ganesan, Kim and Lo as detailed herein) to monitor voltage on the PDN in a portion of the substrate beneath and adjacent to the die to provide voltage feedback to the PMIC as taught by Sturcken according to known methods to yield predictable results, for example, in order to provide feedback control for an output voltage so that the output voltage equals a target output voltage. See, e.g., paragraph [0055] of Sturcken.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P CORNELY whose telephone number is (571)272-4172. The examiner can normally be reached Monday - Thursday 8:30 AM - 4:00 PM.
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812