DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 9, 2025 has been entered.
Claim Objections
Claim 19 is objected to because of the following informalities: “a” should insert before “lower”; “are” should read “is” after “layer”; and “an” should insert after “upper”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9, 10, 13-15, 19 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the specification for the claim limitations of "the second capacitor dielectric layer … is interposed between each of the plurality of bottom electrode layers and the corresponding portion of the first top electrode layer", as recited in claim 1 (note: Fig. 17 show the second capacitor dielectric layer is between each of the plurality of bottom electrode layers and the corresponding portion of the second top electrode layer; and the first capacitor dielectric layer is between each of the plurality of bottom electrode layers and the corresponding portion of the first top electrode layer). For examination purposes, the examiner has interpreted this limitation based on Fig. 17. Clarification is requested.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 10, 13-15, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitations of "sidewall surfaces of lower and middle parts of the plurality of bottom electrode layer", as recited in claim 9, is unclear as to whether said limitations are in one-to-one or multiple-to-one relationship between the sidewall surface and the lower and middle part and between the lower and middle part and the bottom electrode layer applicant refers.
The claimed limitation of "top sidewall surface", as recited in claim 9, line 17, is unclear as to whether said limitation is the same as or different from “sidewall surfaces”, as recited in claim 9, line 11.
The claimed limitation of "all sidewall surfaces of the plurality of bottom electrode layers", as recited in claim 9, is unclear as to whether said limitations is the same as or different from “sidewall surfaces of lower and middle parts of the plurality of bottom electrode layers” and/or “top sidewall surfaces of each of the plurality of the bottom electrode layers”, as recited in claim 9, line 11 and/or 17; also it is unclear as to whether said limitation is in one-to-one or multiple-to-one relationship between the sidewall surface and the bottom electrode layer applicant refers.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 10, 15, 18-20, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohuchi (2010/0155802).
As for claim 9, Ohuchi shows in Fig. 11 and related text a semiconductor memory device 111, comprising:
a substrate1/2/50-53/52a/55/56/58a-58c/60, a plurality of bottom electrode layers 11 disposed on the substrate, a first capacitor dielectric layer 5/(top one of) 77, a second capacitor dielectric layer (bottom one of) 77, a first top electrode layer (top one of) 72, and a second top electrode layer (bottom one of) 72, wherein each of the plurality of bottom electrode layers is of a columnar structure; and
wherein each of the plurality of bottom electrode layers forms a capacitor with a corresponding portion of the first capacitor dielectric layer and a corresponding portion of the first top electrode layer, and forms another capacitor with a corresponding portion of the second capacitor dielectric layer and a corresponding portion of the second top electrode layer;
wherein the second capacitor dielectric layer at least wraps sidewall surfaces of lower and middle parts of the plurality of bottom electrode layers and is interposed between each of the plurality of bottom electrode layers and the corresponding portion of the first top electrode layer, and is disposed between the second top electrode layer and the substrate;
the first capacitor dielectric layer is located above at least part of the second top electrode layer and covers an upper surface and top sidewall surfaces of each of the plurality of bottom electrode layers, and the first capacitor dielectric layer and the second capacitor dielectric layer jointly cover all sidewall surfaces of the plurality of bottom electrode layers; and
the first top electrode layer is located on an upper surface of the first capacitor dielectric layer.
As for claim 10, Ohuchi shows the substrate comprises:
a base 50; and
a coverage dielectric layer 1 on a surface of the base, wherein a plurality of storage node contacts 2 are formed in the coverage dielectric layer, and each of the plurality of bottom electrode layers is connected to each of the plurality of storage node contacts respectively (Fig. 11).
As for claim 15, Ohuchi shows the first top electrode layer comprises:
a first conductive layer located on the upper surface of the first capacitor dielectric layer ([0144], lines 4-5); and
a second conductive layer located on a surface of the first conductive layer ([0144], line 3; Fig. 11).
As for claim 18, Ohuchi shows the first capacitor dielectric layer and the first top electrode layer configured to support the plurality of bottom electrode layer (Fig. 11).
As for claim 19, Ohuchi shows lower surface of the corresponding portion of the first capacitor dielectric layer are in contact with upper surface of another portion of the second capacitor dielectric layer (Fig. 11).
As for claim 20, Ohuchi shows the first capacitor dielectric layer and the second capacitor dielectric layer are formed in different fabrication steps, and the first top electrode layer and the second top electrode layer are formed in different fabrication steps.
Regarding the process limitations ("… formed in different fabrication steps"), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Allowable Subject Matter
Claims 13-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “plurality of opening portions, each of the plurality of opening portions penetrating through the first top electrode layer and the first capacitor dielectric layer and simultaneously overlapping with corresponding multiple bottom electrode layers among the plurality of bottom electrode layers, the second capacitor dielectric layer further covering side walls of the plurality of opening portions, and the second top electrode layer filling up a gap between two adjacent bottom electrode layers among the plurality of bottom electrode layers and extending into the plurality of opening portions; and an interconnection conductive layer, the interconnection conductive layer covering the first top electrode layer and covering the second top electrode layer exposed by the first top electrode layer and electrically connecting the first top electrode layer to the second top electrode layer”, as recited in claim 13.
Claims 13 and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/MEIYA LI/Primary Examiner, Art Unit 2811