DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prosecution Reopened
In view of the appeal brief filed on 10/13/2025, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/EVA Y MONTALVO/ Supervisory Patent Examiner, Art Unit 2818
Claim Objections
Claim 3 is objected to because of the following informalities:
The Examiner suggests the following amendment to correct an apparent typographic error:
3. The semiconductor package of claim 1, wherein the leadframe includes a die pad, and wherein there are bondwires between the bond pads and the plurality of leads so that the semiconductor package is a wirebond package.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6, 20 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bai et al. (PG Pub. No. US 2015/0294929 A1).
Regarding claim 1, Bai teaches a semiconductor package (¶ 0044: 1200, including assembly 300 of fig. 3), comprising:
a semiconductor die (¶ 0030: 202) including circuitry coupled to bond pads (¶ 0029: electrodes 204), the semiconductor die mounted onto a leadframe (¶ 0030 & fig. 3: 202 mounted onto lead frame 102) including a plurality of leads (¶ 0045: 108, including external portions 1204);
a dam bar (¶ inner dam bars 116) having a transverse portion that extends between adjoining ones of the plurality of leads (fig. 3: 116 has transverse portion extending between leads 108);
the semiconductor die electrically connected to the plurality of leads (figs. 3-4: 202 electrically coupled to 108);
a raised dam pattern (¶¶ 0045-0046: 1206,1208) on the dam bar (¶ 0044 & figs. 11-13: 1206/1208 formed on severed portions of inner dam bars 116) or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die, the raised dam pattern comprising a first material that is different relative to a material of the dam bar (¶¶ 0027, 0045: 1206/108 comprises different material than 116); and
a mold material (¶ 0045: 1202) encapsulating the semiconductor die (figs. 11-12: 1202 encapsulated 202).
Regarding claim 3, Bai teaches the semiconductor package of claim 1, wherein the leadframe include a die pad (¶ 0027: 106), and wherein there are bondwires (¶ 0030: 302) between the bond pads and the plurality of leads (figs. 3-4: 302 arranged between 204 and 108) so that the semiconductor package is a wirebond package (¶ 0030).
Regarding claim 6, Bai teaches the semiconductor package of claim 1, wherein the raised dam pattern defines a rectangular shape (fig. 13: 1208 comprises a substantially rectangular shape).
Regarding claim 20, Bai teaches a semiconductor package (¶ 0044: 1200, including assembly 300 of fig. 3), comprising:
a semiconductor die (¶ 0030: 202) mounted onto a leadframe (¶ 0030 & fig. 3: 202 mounted onto lead frame 102);
the leadframe including a plurality of leads (¶ 0045: 108, including external portions 1204) and a dam bar (¶ inner dam bars 116) having a transverse portion that extends between adjoining ones of the plurality of leads (fig. 3: 116 has transverse portion extending between leads 108);
the semiconductor die electrically connected to the plurality of leads (figs. 3-4: 202 electrically coupled to 108);
a raised dam pattern (¶¶ 0045-0046: 1206,1208) on the dam bar (¶ 0044 & figs. 11-13: 1206/1208 formed on severed portions of inner dam bars 116) comprising a first material that is different relative to a material of the dam bar (¶¶ 0027, 0045: 1206/108 comprises different material than 116); and
a mold material (¶ 0045: 1202) encapsulating the semiconductor die (figs. 11-12: 1202 encapsulated 202).
Regarding claim 27, Bai teaches the semiconductor package of claim 1, wherein the leadframe comprises a leaded leadframe (¶¶ 0030, 0045 & fig. 3: leadframe 102 comprises leads 108).
Claims 21-22, 24, 26, 37-38, 40 and 42 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hori (Patent No. US 6,368,895 B1).
Regarding claim 21, Hori teaches a semiconductor package (figs. 3-5), comprising:
a semiconductor die (col. 4 line 2: chip 14);
a plurality of leads (col. 4 line 1 & fig. 3: plurality of electrodes 11), the semiconductor die electrically connected to the plurality of leads (fig. 3 & col. 4 lines 1-11: 14 electrically connected to 11 through metallic bumps 15);
a mold material (col. 4 lines 37-38: sealing resin 16) encapsulating the semiconductor die (fig. 3: 16 encapsulates at least bottom and corners of 14); and
a solder resist material (col. 3 line 62: 12) on a top surface of each of the plurality of leads outside of the mold material (fig. 3: 12 disposed on top surface of each 11 outside 16), the mold material abutting a vertical and not a horizontal surface of the solder resist material (fig. 3: 16 abuts a side surface of 12 and not top/bottom horizontal surfaces of 12).
Regarding claim 22, Hori teaches the semiconductor package of claim 21, wherein the semiconductor package comprises a flipchip package (fig. 3: chip 14 arranged with active side facing downward, meeting the broadest reasonable interpretation of a “flipchip” package).
Regarding claim 24, Hori teaches the semiconductor package of claim 21, wherein the solder resist material extends away from the mold compound (fig. 3: 12 extends away from 18).
Regarding claim 26, Hori teaches the semiconductor package of claim 25, wherein a length of the solder resist material is less than a total length of a lead extending away from the mold compound (fig. 3: length of 12 less than length of 11 extending away from 16).
Regarding claim 37, Hori teaches a semiconductor package (figs. 3-5), comprising:
a semiconductor die (col. 4 line 2: chip 14);
a plurality of leads (col. 4 line 1 & fig. 3: plurality of electrodes 11), the semiconductor die attached to a portion of the plurality of leads (fig. 3 & col. 4 lines 1-11: 14 physically and/or electrically attached to portions of 11);
a mold material (col. 4 lines 37-38: sealing resin 16) encapsulating the semiconductor die and the portion of plurality of leads (fig. 3: 16 encapsulates at least bottom and corners of 14 and portions of 11 attached to 14); and
a solder resist material (col. 3 line 62: 12) on a top surface of each of the plurality of leads outside of the mold material (fig. 3: 12 disposed on top surface of each 11 outside 16), the mold material abutting a side and not a top surface of the solder resist material (fig. 3: 16 abuts a side surface of 12 and not top surface of 12).
Regarding claim 38, Hori teaches the semiconductor package of claim 37, wherein the semiconductor package comprises a flipchip package (fig. 3: package includes die 14 configured with active surface facing downward, meeting the broadest reasobale interpretation of a “flipchip” package).
Regarding claim 40, Hori teaches the semiconductor package of claim 37, wherein the solder resist material extends away from the mold compound (fig. 3: 12 extends away from 18).
Regarding claim 42, Hori teaches the semiconductor package of claim 37, wherein a length of the solder resist material is less than a total length of a lead extending away from the mold compound (fig. 3: length of 12 less than total length of 11 extending away from 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Bai as applied to claim 1 above, and further in view of Karnezos (PG Pub. No. US 2008/0220563 A1).
Regarding claim 2, Bai teaches the semiconductor package of claim 1, comprising a semiconductor package (1200).
Bai does not teach wherein the semiconductor package comprises a flipchip package.
Karnezos teaches semiconductor packages (figs. 20-21: 2000, 2100) in wire bond (¶ 0106: 1610, similar to that of Bai) or flip chip (¶ 0106: 1710) configurations.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Bai in a flipchip arrangement, as a means to provide a package with higher speed applications, such as in mobile communications applications (Karnezos, ¶ 0085).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Bai as applied to claim 1 above, and further in view of Hori.
Regarding claim 4, Bai teaches the semiconductor package of claim 1, comprising a raised dam pattern (1206, 1208).
Bai is silent to wherein a height of the raised dam pattern is 10 to 30 um.
Hori teaches a semiconductor package (fig. 3) including a raised dam pattern (col. 4 lines 12-14: 12, configured to prevent resin flow) on a plurality of leads (col. 3 line 60: 11), wherein a height of the raised dam pattern is 10 to 50 um (col. 4 lines 25-27: 12 formed with a height of 10 to 50 um).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the dam pattern of Bai with the height of Hori, as a means to allow for introduction of resin while retaining resin in a desired enclosure region (Hori, col. 4 lines 12-53).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “10 to 30 um” lies inside the range disclosed by Hori.
Regarding claim 5, Bai teaches the semiconductor package of claim 1, comprising a first material (1206, 1208).
Bai does not teach wherein the first material comprises solder resist (SR).
Hori teaches a semiconductor package (fig. 3) including a raised dam pattern (col. 4 lines 12-14: 12, configured to prevent resin flow) on a plurality of leads (col. 3 line 60: 11), wherein a material of the raised dam pattern comprises solder resist (col. 3 line 62: 12 comprises solder resist). Hori further teaches the solder resist comprises a gate (18a) for casting a resin (col. 4 lines 30-31).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the raised dam pattern of Bai with the material of Hori, as a means to retain resin in a desired enclosure region (Hori, col. 4 lines 12-53).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Bai as applied to claim 1 above, and further in view of Letterman et al (PG Pub. No. US 2010/0019367 A1).
Regarding claim 7, Bai teaches the semiconductor package of claim 1, comprising a semiconductor package.
Bai does not teach where the semiconductor package includes the top side clip.
Letterman teaches a semiconductor package (fig. 4) including a top side clip (¶ 0034: 62).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Bai with a top side clip, as a means to electrically connect electronic chips 59 to the conductive leads (Letterman, ¶ 0034).
Regarding claim 8, Bai in view of Letterman teaches the semiconductor package of claim 7, wherein the leadframe comprises a leadless leadframe (Letterman, ¶ 0046).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bai as applied to claim 1 above, and further in view of Bai et al. (PG Pub. No. US 2019/0074254 A1, hereinafter referenced as ‘Bai-254).
Regarding claim 9, Bai teaches the semiconductor package of claim 1, comprising a semiconductor die (202).
Bai is silent to wherein the semiconductor die comprises an integrated circuit (IC).
Bai-254 teaches semiconductor package (fig. 6) including a semiconductor die (¶ 0026: 52) comprising an integrated circuit (IC) (¶ 0016).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor die of Bai to comprise an integrated circuit, as a means to utilize mature infrastructure of manufacturing tools and materials, as well as lower cost, and/or increase package functionality.
Claims 23, 28, 39 and 44 are rejected under 35 U.S.C. 103 as being unpatentable over Hori as applied to claim 21 above, and further in view of Karnezos.
Regarding claims 23, 28, 39 and 44, Hori teaches the semiconductor packages of claims 21 and 37, including a semiconductor die (14) and a plurality of leads (11).
Hori does not teach wherein there are bondwires between bond pads on the semiconductor die and the plurality of leads so that the semiconductor package is a wirebond package (as recited in claim 23),
wherein wirebonds electrically connect bond pads coupled to circuitry in the semiconductor die to the leads (as recited in claim 28),
wherein there are bondwires between bond pads on the semiconductor die and the plurality of leads so that the semiconductor package is a wirebond package (as recited in claim 39), or
wherein the wirebonds electrically connect circuitry in the semiconductor die to the leads (as recited in claim 44).
Karnezos teaches a semiconductor package (¶ 0062: 1) including bond pads on a semiconductor die (fig. 1: unlabeled bond pads on top surface of die 114) including circuitry (¶ 0085: processor chip), wherein there are bondwires between the bond pads and a plurality of package leads (¶ 0062-0063 & fig. 1: wire bond 116 arranged between bond pads of 114 and conductive pattern 121) so that the semiconductor package is a wirebond package (¶ 0008), wherein the wirebonds electrically connect circuitry in the semiconductor die to the leads (¶ 0063: 116 electrically connected to circuitry of 114).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Hori with bondwires, as a means to package one or more die in a respective package using the most efficient first level interconnect technology, maximizing performance and minimizing cost (Karnezos, ¶ 0008).
Claims 25, 41 and 43 are rejected under 35 U.S.C. 103 as being unpatentable over Hori as applied to claims 21 and 37 above, and further in view of Kawahara et al. (Patent No. US 6,379,997 B1).
Regarding claims 25, 41 and 43, Hori teaches the semiconductor packages of claims 21 and 37, comprising solder resist material (12) covering the top surface of each of the plurality of leads outside of the mold material (fig. 3: 12 covers top surface of each 11 outside 16).
Hori does not teach wherein the solder resist material covers some, but not all, of the top surface of each of the plurality of leads outside of the mold material (as recited in claims 25 and 41), or
wherein the solder resist material covers less than a majority of the top surface of each of the plurality of leads outside of the mold material (as recited in claim 43).
Kawahara teaches a semiconductor package (fig. 125L: 500) including dam member (col. 63 line 67 – col. 64 line 1: 515) covering less than a majority of top surfaces of each of a plurality of leads outside a mold material (col. 63 lines 53-60 & fig. 125L: 515 covers less than a majority of top surfaces of each of a plurality of leads 511 outside mold material 503). In at least one embodiment, Kawahara teaches dam members comprising solder resist (col. 53 lines 5-6).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the solder resist material of Hori with the lead coverage of Kawahara, as a means to provide an amount of solder resist material sufficient to prevent the flow of encapsulating resin (Kawahara, col. 64 lines 2-3) while minimizing manufacturing costs (col. 70 lines 3-4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishimura et al. (PG Pub. No. US 20080179738 A1) teaches a semiconductor package (fig. 6) including a solder resist material (56) on a top surface of each of a plurality of leads (53) outside of a mold material (A), the mold material abutting a vertical and not a horizontal surface of the solder resist material (fig. 6: A abuts side surface of 56 and not top surface of 56).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818