DETAILED ACTION
Email Communication
Applicant is encouraged to authorize the Examiner to communicate via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502, 502.03.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to Office Action mailed on 09/24/2025, Applicant has amended claim 1. However, Applicant’s amendment does not place the Application in condition for allowance.
Status of the Rejections
Due to Applicant’s amendment of claim 1, all rejections from the previous office action are withdrawn. However, upon further consideration, a new ground of rejection is presented below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4, 6 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1).
Regarding claim 1, Pomerene discloses a semiconductor device (figures 2c-2g), comprising:
a semiconductor substrate (28, fig. 2d, 3:5-7) having a first surface (bottom surface) and a second surface (top surface) opposite the first surface (bottom surface) (3:23-27),
wherein the semiconductor substrate comprises an active region containing a plurality of transistors (active circuitry such as transistors in the passivation layer 23, see figures 2b, 2:25-46);
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a through-semiconductor via structure (N+ and P+ regions, figs. 2e-2f, 3:7-34) extending completely through the semiconductor substrate (28) from the first surface to the second surface (see figs. 2e-2f) (see annotated figure below) and disposed in a vicinity of the active region (active circuitry such as transistors in the passivation layer 23, see figures 2b, 2:25-46),
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the through-semiconductor via structure comprising a first through-semiconductor via (N+ region) containing a first conductivity type material (n-type) and a second through-semiconductor via (P+ region) containing a second conductivity type material (p-type) opposite the first conductivity type material (n-type) (figs. 2e-2f, 3:7-34) and
a first conductive layer (conductive layer 27, fig. 2c, 2-65-66) on the first surface (bottom surface) of the semiconductor substrate (28) and comprising a first portion (middle portion) coupled to a first end (bottom end) of the first through-semiconductor via (N+ region) and a first end (bottom end) of the second through-semiconductor via (P+ region) (see figure 2f).
Pomerene further discloses that the semiconductor substrate (28) is bismuth telluride, lead telluride or chalcogenide (3:5-7). However, Pomerene does not explicitly disclose that the semiconductor substrate is a silicon substrate.
Tan is directed to a semiconductor device ([0045], last sentence) wherein substrate (101) is made of Si or lead telluride ([0045]). Thus, Tan explicitly discloses that the Si and lead telluride are art-recognized equivalent semiconductor material that can be used to form substrate of a semiconductor device.
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the Si material as taught by Tan to form the substrate of Pomerene because substituting equivalents known for the same purpose is obvious. See MPEP §2144.06 (II).
Regarding claim 2, Pomerene further discloses a second conductive layer (conductive layer 31, fig. 2f and 3:35-45) on the second surface (top surface) of the substrate (28) and comprising a first portion (portion that is connected to middle N+ region) coupled to a second end (top end) of the first through-silicon via (N+ region) and a second portion (portion that is connected to middle P+ region) coupled to a second end (top end) of the second through-silicon via (P+ region), the first and second portions of the second conductive layer (38) being electrically isolated from each other (the conductive layer 31 is patterned to have isolated portions) (figure 2f and 3:35-38).
Regarding claim 4, Pomerene further discloses the through-silicon via structure further comprises: a third through-silicon via (N+ region) containing the first conductivity type material (n-type) and having a first end (bottom end) and a second end (top end) opposite the first end; a fourth through-silicon via (P+ region) containing the second conductivity type material (p-type) and having a first end (bottom end) and a second end (top end) opposite the first end (see figure 2f that shows plurality of N+ and P+ regions); the first conductive layer (27) comprising a second portion (right portion, see fig. 2f) coupled to the first end (bottom end) of the third through-silicon via (N+ regions) and the first end (bottom end) of the fourth through-silicon via (P+ regions); and the second portion (right portion) of the second conductive layer (31) coupled to the second end (top end) of the third through-silicon via (N+ region) (see fig. 2f).
Regarding claim 6, Pomerene further discloses a conformal liner (formed by substrate 28) on sidewalls of the through-silicon via structure (see fig. 2f).
Regarding claim 8, Pomerene as modified by Tan discloses the semiconductor substrate (28) is a bulk silicon substrate (see [0045] of Tan).
Regarding claim 9, Pomerene further discloses a plurality of electronic devices (37 and 38) on the first surface (bottom surface) and in a vicinity of the through-silicon via structure (see fig. 2i).
Regarding claim 10, Pomerene further discloses that each of the first and second through-silicon vias (N+ and P+ regions) comprises a rectangular cross-section (see figs. 2e and 2f).
Regarding claim 11, Pomerene discloses a semiconductor device (fig. 2g) according to instant claim, and thus it must be configured to operate as a temperature sensor as in the case of the instant application.
Regarding claim 12, Pomerene further discloses a second through-silicon via structure extending through the semiconductor substrate (see figure 2f that shows multiple via structures forming 3 pairs of N+/P+ regions), the second through-silicon via structure comprising a fifth through-silicon via (N+ region) containing the first conductivity type material (n-type material) and a sixth through-silicon via (P+ region) containing the second conductivity type material (p-type material) opposite the first conductivity type material (see fig. 2f), wherein the fifth through-silicon via is coupled to a first terminal (34, fig. 2h) of a power supply (current source, 3:46-49), and the sixth through-silicon via is coupled to a second terminal (34, fig. 2h) of the power supply (3:46-56).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1) as applied above, and further in view of Tan et al. (US 2015/0179543 A1) (hereafter referred as “Tan II”).
Regarding claim 3, Pomerene is silent as to a first solder bump coupled to the first portion of the second conductive layer; and a second solder bump coupled to the second portion of the second conductive layer.
Tan II discloses a semiconductor device wherein solder bumps used as means to connect p-type and n-type regions to the conductive layers ([0022]).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the solder bumps as taught by Tan II to connect the p-type and n-type regions of Pomerene with the conductive layers, as shown by Tan II and also desired by Pomerene.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1) as applied above, and further in view of Boukai et al. (US 2018/0351069 A1).
Regarding claim 5, Pomerene is silent as to a metal silicide layer having a first silicide portion disposed on an upper surface of the first through-silicon via, and a second silicide portion disposed on an upper surface of the second through-silicon via.
Boukai discloses a metal silicide layer is formed on the semiconductor regions to reduce the contact resistance between metal contact and other layers ([0200]).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the metal silicide layer as taught by Boukai on the upper surfaces of the semiconductor regions of Pomerene to reduce the contact resistance, as shown by Boukai.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1) as applied above, and further in view of Nagakubo et al. (US 5,515,682).
Regarding claim 7, Pomerene is silent as to a detection circuit configured to determine an electrical signal that is a function of a temperature difference between the first and second surfaces of the semiconductor substrate.
Nagakubo discloses a Peltier device, similar to Pomerene, that comprises a detection circuit (Peltier control circuit that detects temperature, abstract) configured to determine an electrical signal that is a function of a temperature difference between first and second surfaces of a substrate (Abstract and claim 1).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the Peltier control circuit as taught by Nagakubo in the device of Pomerene such that the temperature of the device can detected, as shown by Nagakubo.
Response to Arguments
Applicant's arguments with respect to claims 1-12 have been considered but are moot in view of the new ground(s) of rejection as necessitated by the amendments.
Applicant argues that Pomerene does not disclose that the substrate comprises an active region comprising a plurality of transistors.
The examiner respectfully disagrees. Pomerene discloses that the substrate comprises an active region comprising active circuitry such as transistors in the passivation layer 23 (see figures 2b, 2:25-46).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 6,800,933 B1 teaches a semiconductor device that reads on claim 1.
US 6,800,933 B1 discloses a semiconductor device (figures 4-6), comprising:
a semiconductor substrate (60, fig. 4 and 4:29-38) having a first surface (bottom surface) and a second surface (top surface) opposite the first surface (bottom surface);
a through-silicon via structure (impurity regions 50, 46, 52 and 48, figures 5 and 6, 4:38-67) extending through the semiconductor substrate (60), the through-silicon via structure comprising a first through-silicon via (n-type impurity region 46 or 48) containing a first conductivity type material (n-type silicon, 4:28-65) and a second through-silicon via (p-type impurity region 50 or 52) containing a second conductivity type material (p-type silicon, 4:28-51) opposite the first conductivity type material (n-type silicon); and
a first conductive layer (interconnect layer 38) on the first surface (bottom surface) of the semiconductor substrate (60) and comprising a first portion (middle portion of patterned interconnect layer 38, see figure 6) coupled to a first end (bottom end) of the first through-silicon via (46) and a first end (bottom end) of the second through-silicon via (52) (see figure 6) (4:28-67).
However, the reference subsequently removes the semiconductor substrate (see figs. 7-8), and thus would not read on claim 2.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Correspondence/Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM MOWLA whose telephone number is (571)270-5268. The examiner can normally be reached on M-Th, 7am - 4pm.
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/GOLAM MOWLA/Primary Examiner, Art Unit 1721