Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 30 October 2025.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3,8-10,15-17,21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Northcott (US PG PUB No. 9021336 ) in view of Kannan (US PG PUB No. 20210334157) and Paley (US PG PUB No. 20200264792).
As per claim [1,8,15], a solid state drive (SSD) (see Northcott COL 2 LINES 30-35: “SSD”) comprising:
a device controller (see Northcott FIG 13: 1304);
a chip controller (see Northcott FIG 13: 1312); and
a NAND memory containing a plurality of dies (see Northcott FIG 13: 1316a-d), wherein one or more of the device controller or the chip controller include logic coupled to one or more substrates (see Northcott FIG 13: 1318a-d), the logic to:
detect a request to program the NAND memory (See Northcott FIG 2: 202), and
program the NAND memory on a stripe-by-stripe basis (see Northcott COL 30 LINES 8-15 AND COL 19 LINES 64-66: “A page stripe should be made up of pages on different flash planes or, preferably, different dies”),
wherein pages of the plurality of dies are organized according to a plurality of dies and includes multiple types of pages (see Northcott COL 30 LINE 23-30); and
wherein each die of the plurality of dies includes a plurality of pages each of which is allocated to a distinct stripe of the plurality of stripes (see Northcott COL 30 LINES 23-30)
However, Northcott does not expressly disclose but in the same field of endeavor Kanan discloses
wherein each stripe spans the plurality of dies and includes multiple types of pages (see Kanan FIG 6A and [0218]).
It would have been obvious before the effective filing date of the invention to modify Northcott to further implement mixed ordering as taught by Kanan.
The suggestion/motivation for doing so would have been for the benefit of improving reliability (See Kanan [0218]).
Therefore it would have been obvious before the effective filing date of the invention to modify Northcott to further implement mixed ordering as taught by Kanan to arrive at the invention as specified in the claims.
However, Northcott does not expressly disclose but in the same field of endeavor Paley discloses
wherein each die has a respective type of pages corresponding to a distinct bit of a plurality of data bits included in multi-level NAND cells of the NAND memory (see Paley [0035]: “The manner in which NVMs 128a - n are partitioned is a design choice . For example , some NVMs can be dedicated solely as a SLC partition , such as partition 132a , and other NVMs can be”).
It would have been obvious before the effective filing date of the invention to modify Northcott to implement a SLC and MLC partition scheme as taught by Paley.
The suggestion/motivation for doing so would have been for the benefit of dynamic configuration for design constraints (See Paley [0035]).
Therefore it would have been obvious before the effective filing date of the invention to modify Kanan to further implement a SLC and MLC partition scheme as taught by Paley for the benefit of configurability to arrive at the invention as specified in the claims.
As per claim [2,9,16], the SSD of claim 1,
wherein each stripe is programmed to include the multiple types of pages to reduce a program time variability across the stripes (see Northcott COL 30 LINES 23-30 and Ojavo [0031])
[Northcott discloses each stripe can include multiple pages per lane (see Northcott FIG 6: 55a). Ojavo further discloses the programming to reduce program time variability across stripes.]
As per claim [3,10,17], the SSD of claim 1,
wherein each stripe is programmed to include the multiple types of pages to reduce an error susceptibility of the NAND memory (Northcott COL 20 LINES 60-65)
As per claim [21,22], the SSD of claim 1,
wherein the multiple types of pages of each of the plurality of stirpes include two or more of an extra page, an upper page, and a lower page (Northcott COL 18 LINES 60-67: “MLC” and Kannan FIG 6a: 606,608)
[Northcott discloses the pages include extra page, an upper page, and a lower page because Northcott discloses using an MLC memory.]
Claim 4,11,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Northcott (US PG PUB No. 9021336 ) in view of Kannan (US PG PUB No. 20210334157) and Paley (US PG PUB No. 20200264792) as applied to claim 1,8 and 15 above and further in view of Gonzalez (US PG PUB No. 2005/0144516)
As per claim [4,11,18], the SSD of claim 1, wherein to program the NAND memory on the stripe-by-stripe basis, the logic is to:
However, Northcott does not expressly disclose but in the same field of endeavor Gonzalez discloses
reorder logical page addresses in a first die of the plurality of dies in accordance with a first configuration, and reorder logical page addresses in a second die of the plurality of dies in accordance with a second configuration, wherein the first configuration is different from the second configuration (see Gonzalez [0075]: “In a preferred embodiment, it is preferable to re-link blocks only within the same die or chip”)
[Relinking blocks is taken as reordering logical page addresses to the extent a page address comprises block address (see Gonzalez [0045]).
It would have been obvious before the effective filing date of the invention to further implement spare page types.
The suggestion/motivation for doing so would have been for the benefit of bad block management.
Therefore it would have been obvious before the effective filing date of the invention to further implement spare page types for the benefit of bad block management to arrive at the invention as specified in the claims.
Claim 5-6,12-13,19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Northcott (US PG PUB No. 9021336 ) in view of Kannan (US PG PUB No. 20210334157) and Paley (US PG PUB No. 20200264792) as applied to claim 1, 8 and 15 above and further in view of Opastrakoon (US Pat No. 11,507,304).
As per claim [5,12,19] the SSD of claim 1, wherein to program the NAND memory on the stripe-by-stripe basis, the logic is to:
However, Northcott does not expressly disclose but in the same field of endeavor Opastrakoon discloses
start a first program operation in a first die of the plurality of dies at a first wordline position, and start a second program operation in a second die of the plurality of dies at a second wordline position, wherein the first wordline position is different from the second wordline position, and wherein each stripe includes pages from multiple wordline locations (see Opastrakoon FIG 3A: 310A, 310B and COL 10 LINES 20-25).
It would have been obvious before the effective filing date of the invention to further modify Northcott to implement diagonal stripes.
The suggestion/motivation for doing so would have been for the benefit of increasing fault tolerance (see Opastrakoon COL 3 LINES 10-15).
Therefore it would have been obvious before the effective filing date of the invention to further implement diagonal stripes as taught by Opastrakoon for the benefit of improving fault tolerance to arrive at the invention as specified in the claims.
As per claim [6,13,20] the SSD of claim 1, wherein the logic is to:
prefill a first die in the plurality of dies with dummy data to a first logical page address, and prefill a second die in the plurality of dies with dummy data to a second logical page address (see Kanan [0219]: “Unused pages 624, such as pages that are passed over because of an address interval or offset, could be filled with dummy data.”),
However, Northcott does not expressly disclose but in the same field of endeavor Opastrakoon discloses
wherein the first logical page address is different from the second logical page address, and wherein each stripe includes pages from multiple wordline locations (see Opastrakoon FIG 3A: 310A, 310B and COL 10 LINES 20-25).
It would have been obvious before the effective filing date of the invention to further modify Northcott to implement diagonal stripes.
The suggestion/motivation for doing so would have been for the benefit of increasing fault tolerance (see Opastrakoon COL 3 LINES 10-15).
Therefore it would have been obvious before the effective filing date of the invention to further implement diagonal stripes as taught by Opastrakoon for the benefit of improving fault tolerance to arrive at the invention as specified in the claims.
REMARKS
The rejection of claims under Ojalvo in view of Kanna is withdrawn in view of Applicant’s amendments and accompanying arguments.
1st ARGUMENT:
As shown above, Northcott discloses that "a page grid 600 is made up of four page stripes 550a, 550b, 550c, 640 having a rank of 4 each, thus the page grid 600 has 16 pages 612, 614, 616, 618, 622, 624, 626, 628, 632, 634, 636, 638, 642, 644, 646, 648 from 16 different die.' See Northcott at col. 30, 11. 23-30. However, no two pages of these 16 pages shown in FIG. 6 of Northcott belong to the same page stripe (e.g., 550a, 550b, 550c). Thus Northcott does not teach or suggest that "each die of the plurality of dies includes a plurality of pages each of which is allocated to a distinct stripe of the plurality of stripes" as recited in claim 1 as amended.
Examiner maintains Northcott discloses the subject matter to the extent Northcott discloses pages in the die can be part of different stripes. The claim should recite ‘wherein each page within each die is allocated to a different stripe of the plurality of stripes.’ As written the claim appears to encompass different pages in a die belong to different stripes and also different pages in a die belong to a given stripe. Examiner further notes Kanan discloses the stripe may comprise a page wise stripe (see Kanan FIG 6a).
2nd ARGUMENT:
As shown above, Kannan discloses that "heterogeneous solid-state memory has MLC memory with two bits per cell, QLC memory with four bits per cell, and TLC memory with three bits per cell (QLC and TLC may also be designated types of MLC)." See Kannan at para. 30. Kannan further explains that "Logical pages 604 of the RAID stripe 602 are mapped with a mixed ordering into pages of atomic write page groups 606, 608, 610 of the various types of solid-state memory." See id. However, Kannan does not mention "die," nor does it explain dies of a stripe are organized based on different bits in multi-level cells for programming. Thus, Kannan does not teach or suggest at least "each die has a respective_type of page corresponding to a distinct bit of a plurality of data bits included in multi-level NAND cells of the NAND memory" as recited in claim 1 as amended.
Examiner maintains Kanan discloses dies at multiple paragraphs (See e.g., Kanan [0094]) and further notes Paley is relied upon to teach a die comprising a respective page.
3rd ARGUMENT:
Ojavo is cited for teaching "prefill a first die in the plurality of dies with dummy data to a first logical page address, and prefill a second die in the plurality of dies with dummy data to a second logical page address (see Ojavo FIG 3: 60)." See Office action at p. 6. Ojavo discloses "a method for parallel data storage" and that "[t]he method begins with assessing the programming durations of the various Flash dies, at a TPROG estimation step 60." See Ojavo at para. 43. In view of the disclosure, Ojavo is silent regarding whether any prefilling occurs while "the programming durations of the various flash dies" are assessed at the "TPROG estimation step 60." Thus, Ojavo does not teach or suggest "prefill a first die in the plurality of dies with dummy data to a first logical page address" or "prefill a second die in the plurality of dies with dummy data to a second logical page address" as recited in claim 6.
Examiner notes Kanan is relied upon to teach filling empty pages with dummy data as might occurring in a mixed ordering.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137