Prosecution Insights
Prosecution Insights
12 pending office actions • 12 art units • 12 examiners • 12 of 12 (100%) have an AI response strategy ready • 37 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 12 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 12 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (25%) |
| §102 only | 3 (25%) |
| Multi-statute (no §101) | 6 (50%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| HAN, JONATHAN | 1 | 83.4% | +9.5% |
| BERNSTEIN, ALLISON | 1 | 81.0% | +2.7% |
| LOONAN, ERIC T | 1 | 64.3% | +26.6% |
| LAPPAS, JASON | 1 | 91.0% | +8.1% |
| CHEN, JACK S J | 1 | 76.6% | +5.7% |
| LEE, ALVIN LYNGHI | 1 | 89.0% | +8.7% |
| CHO, SUNG IL | 1 | 91.4% | +8.1% |
| NEWTON, VALERIE N | 1 | 84.0% | +5.8% |
| HSIEH, HSIN YI | 1 | 51.2% | +5.8% |
| SAIN, GAUTAM | 1 | 67.0% | +24.4% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18084100 | NAND DUTY CYCLE CORRECTION FOR DATA INPUT WRITE PATH | LAPPAS, JASON | 5d overdue |
| 17817857 | GAP-FILL FOR 3D NAND STAIRCASE | NEWTON, VALERIE N | 35d |
| 18237077 | PREVENTION OF FLOATING GATE 3D-NAND CELL RESIDUAL BY USING HYBRID PLUG PROCESS IN SUPER-DECK STRUCTURE | BERNSTEIN, ALLISON | 65d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17123451 | VERTICAL CHANNEL WITH CONDUCTIVE STRUCTURES TO IMPROVE STRING CURRENT | CHEN, YU | 28d overdue |
| 18086315 | MULTI-DECK NAND MEMORY WITH HYBRID DECK SLC | LOONAN, ERIC T | 4d overdue |
| 18368787 | FLOATING GATE NAND CELL – METHODS AND APPROACHES FOR FABRICATION | HAN, JONATHAN | 3d overdue |
| 18047097 | WORD LINE VOLTAGE DETECTION CIRCUIT FOR ENCHANCED READ OPERATION | CHO, SUNG IL | 2d overdue |
| 18047094 | STRUCTURE AND METHOD OF INCREASING SUBTRACTIVE BITLINE AIR GAP HEIGHT | LEE, ALVIN LYNGHI | 12d |
| 17791175 | VARYING CHANNEL WIDTH IN THREE-DIMENSIONAL MEMORY ARRAY | HSIEH, HSIN YI | 14d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18086315 | MULTI-DECK NAND MEMORY WITH HYBRID DECK SLC | LOONAN, ERIC T | 4d overdue |
| 17705051 | INTERFACE FOR DIFFERENT INTERNAL AND EXTERNAL MEMORY IO PATHS | SAIN, GAUTAM | 14d |
| Art Unit | Apps |
|---|---|
| 2818 | 1 |
| 2824 | 1 |
| 2137 | 1 |
| 2827 | 1 |
| 2893 | 1 |
| 2813 | 1 |
| 2825 | 1 |
| 2897 | 1 |
| 2899 | 1 |
| 2135 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18368787 | FLOATING GATE NAND CELL – METHODS AND APPROACHES FOR FABRICATION | HAN, JONATHAN | 2818 | §102§103§112 | Non-Final OA | 3d overdue | AI Ready | Sep 15, 2023 |
| 18237077 | PREVENTION OF FLOATING GATE 3D-NAND CELL RESIDUAL BY USING HYBRID PLUG PROCESS IN SUPER-DECK STRUCTURE | BERNSTEIN, ALLISON | 2824 | §102 | Non-Final OA | 65d | AI Ready | Aug 23, 2023 |
| 18086315 | MULTI-DECK NAND MEMORY WITH HYBRID DECK SLC | LOONAN, ERIC T | 2137 | §102§103 | Non-Final OA | 4d overdue | AI Ready | Dec 21, 2022 |
| 18084100 | NAND DUTY CYCLE CORRECTION FOR DATA INPUT WRITE PATH | LAPPAS, JASON | 2827 | §102 | Non-Final OA | 5d overdue | AI Ready | Dec 19, 2022 |
| 17919730 | ORGANIC SPACER FOR INTEGRATED CIRCUITS | CHEN, JACK S J | 2893 | §102 | Non-Final OA | 15d overdue | AI Ready | Oct 18, 2022 |
| 18047094 | STRUCTURE AND METHOD OF INCREASING SUBTRACTIVE BITLINE AIR GAP HEIGHT | LEE, ALVIN LYNGHI | 2813 | §102§103 | Non-Final OA | 12d | AI Ready | Oct 17, 2022 |
| 18047097 | WORD LINE VOLTAGE DETECTION CIRCUIT FOR ENCHANCED READ OPERATION | CHO, SUNG IL | 2825 | §102§103 | Non-Final OA | 2d overdue | AI Ready | Oct 17, 2022 |
| 17817857 | GAP-FILL FOR 3D NAND STAIRCASE | NEWTON, VALERIE N | 2897 | §103 | Non-Final OA | 35d | AI Ready | Aug 05, 2022 |
| 17791175 | VARYING CHANNEL WIDTH IN THREE-DIMENSIONAL MEMORY ARRAY | HSIEH, HSIN YI | 2899 | §103§112 | Non-Final OA | 14d | AI Ready | Jul 06, 2022 |
| 17705051 | INTERFACE FOR DIFFERENT INTERNAL AND EXTERNAL MEMORY IO PATHS | SAIN, GAUTAM | 2135 | §103 | Non-Final OA | 14d | AI Ready | Mar 25, 2022 |
| 17551018 | 3D NAND MEMORY CELL WITH FLAT TRAP BASE PROFILE | SMITH, SAMUEL JONATHAN | 2817 | §103 | Final Rejection | 34d | AI Ready | Dec 14, 2021 |
| 17123451 | VERTICAL CHANNEL WITH CONDUCTIVE STRUCTURES TO IMPROVE STRING CURRENT | CHEN, YU | 2896 | §102§112 | Final Rejection | 28d overdue | AI Ready | Dec 16, 2020 |
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