DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2 June 2026 has been entered.
Status of the Claims
Amendment filed 2 June 2026 is acknowledged. Claims 1, 9-14, and 18-20 have been amended. Claims 1-20 are pending.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claims 1, 4-9, 14, 16, 17, 19, and 20, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area” and “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area” in combination with “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate” in combination with “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar” in combination with “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” “comprising a first contact hole positioned above the first conductive region, wherein the first contact hole includes a periphery surrounded by a circumference of the first conductive region” in combination with “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” and, “a third transistor in the plurality of transistors is connected to a source region or a drain region of the third transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the subject matter of claims 1, 4-9, 14, 16, 17, 19, and 20, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate,” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area” and “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area” in combination with “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate,” in combination with “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar” in combination with “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” “comprising a first contact hole positioned above the first conductive region, wherein the first contact hole includes a periphery surrounded by a circumference of the first conductive region” in combination with “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” and, “a third transistor in the plurality of transistors is connected to a source region or a drain region of the third transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” must find support in the specification.
Claim Objections
Claims 1, 9, 14, 18, and 19 are objected to because of the following informalities:
Claims 1, 9, and 18 recite the limitations, “a first insulating material within the first trench and covers bottom side of the first trench,” and, “a second insulating material is within the second trench and covers bottom side of the second trench.” These appear to contain a typographical error and may be corrected as, “a first insulating material within the first trench and covers a bottom side of the first trench,” and, “a second insulating material is within the second trench and covers a bottom side of the second trench.”
Claim 14 recites the limitation, “wherein the first epitaxial semiconductor pillar is formed in a first dielectric layer covering the plurality of transistors, and the second epitaxial semiconductor pillar is formed in a second dielectric layer covering the first dielectric layer, wherein the first metal layer is disposed between the first and second dielectric layer, and a lower surface of the first metal layer is coplanar with a top surface of the first epitaxial semiconductor pillar.” This appears to contain a typographical error and may be corrected as, “wherein the first epitaxial semiconductor pillar is formed in a first dielectric layer covering the plurality of transistors, and the second epitaxial semiconductor pillar is formed in a second dielectric layer covering the first dielectric layer, and wherein the first metal layer is disposed between the first and second dielectric layer, and a lower surface of the first metal layer is coplanar with a top surface of the first epitaxial semiconductor pillar.”
Claim 18 recites the limitation, “wherein the lightly doped area of the first conductive region of the NMOS transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and the lightly doped area of the second conductive region of the PMOS transistor is extended from a second revealed sidewall of the substrate revealed by the second trench; wherein an edge of the first conductive region and an edge of the second conductive region are substantially parallel and opposite to each other.” This appears to contain a typographical error and may be corrected as, “wherein the lightly doped area of the first conductive region of the NMOS transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and the lightly doped area of the second conductive region of the PMOS transistor is extended from a second revealed sidewall of the substrate revealed by the second trench; and wherein an edge of the first conductive region and an edge of the second conductive region are substantially parallel and opposite to each other.”
Claim 19 recites the limitation, “comprising a first contact hole above the first conductive region.” Because this dependent claim is adding elements to the independent claim, the claim should be corrected as, “further comprising a first contact hole above the first conductive region.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-17, 19, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitations, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” and, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 1 recites the limitations, “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate,” and, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate,” is disclosed in at least FIGs. 25-30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 4 recites the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” This limitation is not supported in combination with at least the limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” of claim 1 from which the claim depends. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30 which do not show the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 5 recites the limitation, “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed.” This limitation is not supported in combination with at least the limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed,” is disclosed in at least FIGs. 27 and 30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 6 recites the limitation, “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region.” This limitation is not supported in combination with at least the limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19 which do not show the limitation, “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 7 recites the limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator.” This limitation is not supported in combination with at least the limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. The limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator,” is disclosed in at least FIGs. 25 and 28. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 8 recites the limitation, “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer.” This limitation is not supported in combination with at least the limitations, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” and, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. Neither of these limitations are disclosed with, “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer.” As best understood by Examiner, these features are not disclosed in combination.
Claim 9 recites the limitations, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” and, “wherein a top surface of the STI region is higher than a top surface of a gate conductive region.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30. The limitation, “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 9 recites the limitation, “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate,” and, “wherein a top surface of the STI region is higher than a top surface of a gate conductive region.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “a first insulating material [ ] to form a first localized isolation structure under the source region of the first transistor, and a second insulating material [ ] to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate,” is disclosed in at least FIGs. 25-30. The limitation, “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 14 recites the limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” and, “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” is disclosed in at least FIGs. 20-24 which do not show the limitation, “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 16 recites the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” This limitation is not supported in combination with at least the limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” of claim 14 from which the claim depends. The limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” is disclosed in at least FIGs. 20-24 which do not show the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 17 recites the limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator.” This limitation is not supported in combination with at least the limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” of claim 14 from which the claim depends. The limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” is disclosed in at least FIGs. 20-24. The limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator,” is disclosed in at least FIGs. 25 and 28. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 19 recites the limitation, “comprising a first contact hole positioned above the first conductive region, wherein the first contact hole includes a periphery surrounded by a circumference of the first conductive region.” This limitation is not supported in combination with at least the limitation, “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” of claim 18 off which the claim depends. The limitation, “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30 which do not show the limitation, “comprising a first contact hole positioned above the first conductive region, wherein the first contact hole includes a periphery surrounded by a circumference of the first conductive region.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 20 recites the limitation, “a third transistor in the plurality of transistors is connected to a source region or a drain region of the third transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” This limitation is not supported in combination with at least the limitation, “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” of claim 18 off which the claim depends. The limitation, “wherein the [ ] conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30 which do not show the limitation, “a third transistor in the plurality of transistors is connected to a source region or a drain region of the third transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” As best understood by Examiner, these two features are not disclosed in combination.
Claims 2, 3, 10-13, and 15 are rejected for merely containing the flaws of the parent claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitations, “a first insulator,” and, “a second insulator.” It is unclear whether these elements as the same as, or distinct from, the previously-recited, “first localized isolation structure,” and, “second localized isolation structure,” of claim 1 off which the claim depends. For the purposes of applying art, these features will be considered one in the same.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US Patent Application Publication 2016/0240541, hereinafter Liaw ‘541) in view of Subbanna (US Patent 5,338,698, hereinafter Subbanna ‘698), Esaki (US Patent Application Publication 2001/0050395, hereinafter Esaki ‘395), and Hamaguchi (US Patent Application Publication 2006/0131657, hereinafter Hamaguchi ‘657), all four of record.
With respect to claim 1, Liaw ‘541 teaches (FIGs. 1, 2, and 5-7) a SRAM cell substantially as claimed, comprising:
a substrate (11) having a horizontal surface ([0031]);
a plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) within the substrate (11), each of the transistors includes a source region (“source and drain regions”), a drain region (“source and drain regions”) and a gate structure (“gate”) located between the source region and the drain region ([0022, 0031]);
a first shallow trench isolation (STI) region (17) disposed next to the source region of a first transistor of the plurality of transistors ([0032]);
a second STI region (17) disposed next to the drain region of the first transistor of the plurality of transistors ([0032]);
a set of contacts (gate and Contact-1) coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0034-0035]);
a word-line (WL) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0024]);
a bit-line (BL) and a bit line bar (BLB) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]);
a VDD contacting line (Vdd) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]); and
a VSS contacting line (Vss) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]).
Thus, Liaw ‘541 is shown to teach all the features of the claim with the exception of:
wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area horizontally connected to the heavily doped area;
wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region of the gate structure of the first transistor;
wherein first and second trenches are within the substrate, a first insulating material is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the source region of the first transistor, and a second insulating material is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate; and
wherein the lightly doped area of the source region of the first transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and the lightly doped area of the drain region of the first transistor is extended from a second revealed sidewall of the substrate revealed by the second trench.
However, Subbanna ‘698 teaches (FIG. 3) each of a drain region (33 and 34) and a source region (33 and 34) of a transistor (30) including a heavily doped area (34) and a metal area (33) horizontally connected to the heavily doped area (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Further, Esaki ‘395 teaches (FIG. 1A) first and second STI regions (10) having a top surface higher than a top surface of a gate conductive region (3) of a gate structure (14) to fully isolate transistors in a process that allows for self-alignment of said STI regions ([0107]); and each of a drain region (5 and 12) and a source region (5 and 12) of a transistor including a lightly doped area (5) and a heavily doped area (12) laterally extended from a most lateral sidewall of the lightly doped area ([0107]) to prevent short channel effect ([0041]).
Still further, Hamaguchi ‘657 teaches (FIG. 1) first and second trenches (both defined by 17, 21, and 27) within a substrate (40), a first insulating material (one of 17) is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under a source region (one of 21 and 27) of a first transistor (43), and a second insulating material (another of 17) is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under a drain region (another of 21 and 27) of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate; wherein a lightly doped area (one of 21) of the source region of the first transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and a lightly doped area (another of 21) of the drain region of the first transistor is extended from a second revealed sidewall of the substrate revealed by the second trench to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 including a heavily doped area and a metal area horizontally connected to the heavily doped area as taught by Subbanna ‘698 to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced; to have formed the first and second STI regions respectively of Liaw ‘541 having a top surface higher than a top surface of a gate conductive region of the gate structure of the first transistor as taught by Esaki ‘395 to fully isolate transistors in a process that allows for self-alignment of said STI regions; to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 and Subbanna ‘698 including a lightly doped area and a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area as taught by Esaki ‘395 to prevent short channel effect; and to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, and Esaki ‘395 wherein first and second trenches are within the substrate, a first insulating material is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the source region of the first transistor, and a second insulating material is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate, and wherein the lightly doped area of the source region of the first transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and the lightly doped area of the drain region of the first transistor is extended from a second revealed sidewall of the substrate revealed by the second trench as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region.
With respect to claim 6, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 teach the device as described in claim 1 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitation wherein a first contact hole for one of the contacts is disposed between the first STI region and a side of the gate structure of the first transistor, and a second contact hole for another one of the contacts is disposed between the second STI region and an opposite side of the gate structure of the first transistor, wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region.
However, Esaki ‘395 teaches (FIG. 1A) a first contact hole (hole for left contact 13) for one of contacts (13) disposed between a first STI region (left STI 10) and a side of a gate structure (14) of a first transistor, and a second contact hole (hole for right contact 13) for another one of the contacts is disposed between a second STI region (right STI 10) and an opposite side of the gate structure of the first transistor to provide isolated electrical contact to the source and drain of the transistor ([0107]).
Further, Subbanna ‘698 teaches (FIG. 3) contacts (S and D) corresponding to metal areas (33) of the source and drain regions (33 and 34) (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 wherein a first contact hole for one of the contacts is disposed between the first STI region and a side of the gate structure of the first transistor, and a second contact hole for another one of the contacts is disposed between the second STI region and an opposite side of the gate structure of the first transistor as taught by Esaki ‘395 to provide isolated electrical contact to the source and drain of the transistor; and to have formed the first contact hole and the second contact hole of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 corresponding to the metal area of the source region and to the metal area of the drain region respectively as taught by Subbanna ‘698 to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced.
With respect to claim 8, Liaw ‘541 teaches wherein the set of contacts (gate and Contact-1) comprise a set of first contacts (gate) and a set of second contacts (Contact-1), the set of first contacts are connected to a first metal layer (Gate_CO), and the set of second contacts are connected to a second metal layer (Contact-2) but disconnected from the first metal layer ([0036]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 as applied to claim 1 above, and further in view of Blatchford (US Patent Application Publication 2013/0069168, hereinafter Blatchford ‘168) of record.
With respect to claim 2, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 teach the device as described in claim 1 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitation wherein as a minimum feature size (λ) of the SRAM cell gradually decreases from 28nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ2) is the same or substantially the same, when λ is decreased from 28nm to 5nm, the area size of the SRAM cell is between 84λ2~102λ2.
However, Liaw ‘541 teaches SRAM nodes below 28nm, including 22nm, 20nm, and 14nm using existing photolithographic tools with corresponding limits on lithography and feature sizes, thus produced at a lowered cost ([0061]). Process nodes between 5nm-28nm have been developed before the effective filing date of the claimed invention. Maintaining an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same is merely a matter of scalability and change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). One of ordinary skill in the art would be motivated to maintain an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same to develop denser memory allowing more storage on a smaller footprint.
Further, Blatchford ‘168 teaches (FIG. 1) an area size of an SRAM cell in terms of square of a minimum feature size (λ) of about 150λ2 for a feature size 20nm to provide a very significant area savings for integrated circuits with large SRAM memory arrays ([0032]). This falls within the disclosed dimensions of an area size of an SRAM cell in terms of square of a minimum feature size (λ) between 84λ2-672λ2 for feature sizes between 5nm-28nm. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 wherein as a minimum feature size (λ) of the SRAM cell gradually decreases from 28nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ2) is the same or substantially the same, when λ is decreased from 28nm to 5nm, the area size of the SRAM cell is between 84λ2~102λ2 as taught by Blatchford ‘168 because this is merely a matter of scalability and obvious change in size to develop denser memory allowing more storage on a smaller footprint, and to provide a very significant area savings for integrated circuits with large SRAM memory arrays.
Applicant is reminded that any features critical to achieving the claimed dimensions must be claimed.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, Esaki ‘395, Hamaguchi ‘657, and Blatchford ‘168 as applied to claim 2 above, and further in view of Yoon et al. (US Patent Application Publication 2010/0289084, hereinafter Yoon ‘084) of record.
With respect to claim 3, Liaw ‘541, Subbanna ‘698, Esaki ‘395, Hamaguchi ‘657, and Blatchford ‘168 teach the device as described in claim 2 above with the exception of the additional limitation wherein a length of one transistor is between 3~4λ.
However, Yoon ‘084 teaches (FIG. 4A) a length of one transistor is between 3~4λ as art-recognized dimensions for transistors used in an SRAM. Further, this dimension represents a mere change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a length of one transistor of Liaw ‘541, Subbanna ‘698, Esaki ‘395, Hamaguchi ‘657, and Blatchford ‘168 between 3~4λ as taught by Yoon ‘084 because this represents art-recognized dimensions for transistors used in an SRAM, and because this is merely a matter of scalability and obvious change in size.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 as applied to claim 1 above, and further in view of Ariizumi et al. (US Patent 4,578,694, hereinafter Ariizumi ‘694).
With respect to claim 4, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 teach the device as described in claim 1 above with the exception of the additional limitation wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.
However, Ariizumi ‘694 teaches (FIGs. 3 and 4) a gate region (23 or 24) of a transistor connected to a source region (15 or 17) or a drain region (15 or 17) of the transistor directly through a first metal interconnection (central portion of gate electrode) without another metal layer lower than the first metal interconnection to protect a load transistor (col. 3, ln. 4-30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a gate region of one transistor in the plurality of transistors of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection as taught by Ariizumi ‘694 to protect a load transistor.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 as applied to claim 1 above, and further in view of Do et al. (US Patent Application Publication 2022/0059460, hereinafter Do ‘460) of record.
With respect to claim 5, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 teach the device as described in claim 1 above with the exception of the additional limitation wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed.
However, Do ‘460 teaches (FIGs. 10A and 11) a VDD contacting line or a VSS contacting line (BP) distributed under a horizontal surface of a substrate (101) from which a plurality of transistors are formed so wiring lines may be designed more freely, and a standard cell having the same number of tracks (a number of wiring lines or the like) may be implemented to have a relatively smaller cell height, or a relatively larger number of tracks may be guaranteed in a standard cell having the same cell height ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the VDD contacting line or the VSS contacting line of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 distributed under the horizontal surface of the substrate from which the plurality of transistors are formed as taught by Do ‘460 so wiring lines may be designed more freely, and a standard cell having the same number of tracks (a number of wiring lines or the like) may be implemented to have a relatively smaller cell height, or a relatively larger number of tracks may be guaranteed in a standard cell having the same cell height.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 as applied to claim 1 above, and further in view of Yoon ‘084.
With respect to claim 7, as best understood by Examiner, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 teach the device as described in claim 1 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitation wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator, and a third STI region is between the NMOS transistor and the PMOS transistor, and an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ~4λ.
However, Hamaguchi ‘657 teaches (FIG. 1) a bottom surface of a n+ region (27) of a NMOS transistor (43) is fully isolated by a first insulator (17), and a bottom surface of a p+ region (27) of a PMOS transistor (44) is fully isolated by a second insulator (17) to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Further, Hamaguchi ‘657 teaches (FIG. 1) a third STI region (11) between an NMOS transistor and a PMOS transistor to isolate said NMOS transistor from said PMOS transistor ([0029]).
Still further, Yoon ‘084 teaches (FIG. 4A) a length of one transistor is between 3~4λ as art-recognized dimensions for transistors used in an SRAM. Knowing this dimension for a length of one transistor, one of ordinary skill in the art could readily establish an edge distance between an n+ region of an NMOS transistor and a p+ region of a PMOS transistor between 2λ~4λ without undue experimentation. Further, this dimension represents a mere change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region; to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 further comprising a third STI region is between the NMOS transistor and the PMOS transistor as taught by Hamaguchi ‘657 to isolate said NMOS transistor from said PMOS transistor; and to have formed an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 between 2λ~4λ as taught by Yoon ‘084 because this represents art-recognized dimensions for transistor components used in an SRAM, and because this is merely a matter of scalability and obvious change in size.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541 in view of Hamaguchi ‘657, Subbanna ‘698, and Esaki ‘395.
With respect to claim 9, Liaw ‘541 teaches (FIGs. 1, 2, and 5-7) a SRAM cell substantially as claimed, comprising:
a plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2), wherein a shallow trench isolation (STI) region (17) surrounds a first transistor of the plurality of transistors, and each of the first transistor and a second transistor includes a source region (“source and drain regions”), a drain region (“source and drain regions”) and a gate structure (“gate”) located between the source region and the drain region ([0022, 0031-0032]);
a set of contacts (gate and Contact-1) coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0034-0035]);
a word-line (WL) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0024]);
a bit-line (BL) and a bit line bar (BLB) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]);
a VDD contacting line (Vdd) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]); and
a VSS contacting line (Vss) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]).
Thus, Liaw ‘541 is shown to teach all the features of the claim with the exception of:
wherein the shallow trench isolation (STI) region surrounds a first transistor and a second transistor of the plurality of transistors;
wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area horizontally connected to the heavily doped area;
wherein a top surface of the STI region is higher than a top surface of a gate conductive region of the gate structures of the first transistor and the second transistor, and a first sidewall of the source region or drain region of the first transistor is parallel or substantially parallel to a second sidewall of the source region or drain region of the second transistor, wherein the first sidewall of the source region or drain region of the first transistor faces to the second sidewall of the source region or drain region of the second transistor; and
wherein first and second trenches are within the substrate, a first insulating material is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the source region of the first transistor, and a second insulating material is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate.
However, Hamaguchi ‘657 teaches (FIG. 1) a shallow trench isolation (STI) region (11) surrounding a first transistor (43) and a second transistor (44) of a plurality of transistors; a first sidewall of a source region (one of 21 and 27) or drain region (another of 21 and 27) of the first transistor is parallel or substantially parallel to a second sidewall of a source region (one of 21 and 27) or drain region (another of 21 and 27) of the second transistor, wherein the first sidewall of the source region or drain region of the first transistor faces to the second sidewall of the source region or drain region of the second transistor; and first and second trenches (both defined by 17, 21, and 27) within a substrate (40), a first insulating material (one of 17) is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the source region of the first transistor, and a second insulating material (another of 17) is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Further, Subbanna ‘698 teaches (FIG. 3) each of a drain region (33 and 34) and a source region (33 and 34) of a transistor (30) including a heavily doped area (34) and a metal area (33) horizontally connected to the heavily doped area (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Still further, Esaki ‘395 teaches (FIG. 1A) a top surface of STI regions (10) higher than a top surface of a gate conductive region (3) of a gate structure (14) to fully isolate transistors in a process that allows for self-alignment of said STI regions ([0107]); and each of a drain region (5 and 12) and a source region (5 and 12) of a transistor including a lightly doped area (5) and a heavily doped area (12) laterally extended from a most lateral sidewall of the lightly doped area ([0107]) to prevent short channel effect ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the shallow trench isolation (STI) region of Liaw ‘541 surrounding a first transistor and a second transistor of the plurality of transistors, and further comprising a first sidewall of the source region or drain region of the first transistor is parallel or substantially parallel to a second sidewall of the source region or drain region of the second transistor, wherein the first sidewall of the source region or drain region of the first transistor faces to the second sidewall of the source region or drain region of the second transistor, and wherein first and second trenches are within the substrate, a first insulating material is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the source region of the first transistor, and a second insulating material is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the drain region of the first transistor, so that the bottom sides of the source region and the drain region of the first transistor are isolated from the substrate as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region; to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 including a heavily doped area and a metal area horizontally connected to the heavily doped area as taught by Subbanna ‘698 to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced; to have formed a top surface of the STI region of Liaw ‘541 higher than a top surface of a gate conductive region of the gate structures of the first transistor and the second transistor as taught by Esaki ‘395 to fully isolate transistors in a process that allows for self-alignment of said STI regions; and to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 and Subbanna ‘698 including a lightly doped area and a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area as taught by Esaki ‘395 to prevent short channel effect.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Hamaguchi ‘657, Subbanna ‘698, and Esaki ‘395 as applied to claim 9 above, and further in view of Blatchford ‘168.
With respect to claims 10-13, Liaw ‘541, Hamaguchi ‘657, Subbanna ‘698, and Esaki ‘395 teach the device as described in claim 9 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitations wherein an area of the SRAM cell is within the range of 84λ2~672λ2 when a minimum feature size is 5nm; wherein an area of the SRAM cell is within the range of 84λ2~440λ2 when a minimum feature size is 7nm; wherein when a minimum feature size is between 10nm to 16nm, an area of the SRAM cell is within the range of 84λ2~204λ2; and wherein when a minimum feature size λ is between 22nm to 28nm, an area of the SRAM cell is within the range of 84λ2~139λ2.
However, Liaw ‘541 teaches SRAM nodes below 28nm, including 22nm, 20nm, and 14nm using existing photolithographic tools with corresponding limits on lithography and feature sizes, thus produced at a lowered cost ([0061]). Process nodes between 5nm-28nm have been developed before the effective filing date of the claimed invention. Maintaining an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same is merely a matter of scalability and change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). One of ordinary skill in the art would be motivated to maintain an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same to develop denser memory allowing more storage on a smaller footprint.
Further, Blatchford ‘168 teaches (FIG. 1) an area size of an SRAM cell in terms of square of a minimum feature size (λ) of about 150λ2 for a feature size 20nm to provide a very significant area savings for integrated circuits with large SRAM memory arrays ([0032]). This falls within the disclosed dimensions of an area size of an SRAM cell in terms of square of a minimum feature size (λ) between 84λ2-672λ2 for feature sizes between 5nm-28nm. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Hamaguchi ‘657, Subbanna ‘698, and Esaki ‘395 wherein an area of the SRAM cell is within the range of 84λ2~672λ2 when a minimum feature size is 5nm; wherein an area of the SRAM cell is within the range of 84λ2~440λ2 when a minimum feature size is 7nm; wherein when a minimum feature size is between 10nm to 16nm, an area of the SRAM cell is within the range of 84λ2~204λ2; and wherein when a minimum feature size λ is between 22nm to 28nm, an area of the SRAM cell is within the range of 84λ2~139λ2 as taught by Blatchford ‘168 because this is merely a matter of scalability and obvious change in size to develop denser memory allowing more storage on a smaller footprint, and to provide a very significant area savings for integrated circuits with large SRAM memory arrays.
Applicant is reminded that any features critical to achieving the claimed dimensions must be claimed.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US Patent Application Publication 2015/0357282, hereinafter Lau ‘282) of record in view of Yamamoto et al. (Japanese Kokai Publication H10-27887, hereinafter Yamamoto ‘887) of record and Yuki (US Patent Application Publication 2008/0116583, hereinafter Yuki ‘583).
With respect to claim 14, Lau ‘282 teaches (FIGs. 4-5C) a SRAM cell as substantially as claimed, comprising:
a plurality of transistors (defined within AC3 of logic cell 300) ([0105-0106]);
a plurality of contacts (AP1-AP5) coupled to the plurality of transistors ([0108]);
a first metal layer (M1) horizontally extended and disposed above and electrically coupled to the plurality of transistors ([0110]);
a second metal layer (M2) disposed above the first metal layer (M1) and electrically coupled to the plurality of transistors ([0101]); and
a third metal layer (M3) disposed above the second metal layer (M2) and electrically coupled to the plurality of transistors ([0112]);
wherein the plurality of contacts (AP1-AP5) comprise a set of first contacts (AP1 and AP2) and a set of second contacts (AP3-AP5), the set of first contacts are connected to the first metal layer (M1), and the set of second contacts are directly connected to the second metal layer (M2) but disconnected from the first metal layer ([0109]).
Thus, Lau ‘282 is shown to teach all the features of the claim with the exception of:
wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar, wherein a top of the second epitaxial semiconductor pillar is higher than an upper surface of the first metal layer,
wherein the first epitaxial semiconductor pillar is formed in a first dielectric layer covering the plurality of transistors, and the second epitaxial semiconductor pillar is formed in a second dielectric layer covering the first dielectric layer, and
wherein the first metal layer is disposed between the first and second dielectric layer, and a lower surface of the first metal layer is coplanar with a top surface of the first epitaxial semiconductor pillar.
However, Yamamoto ‘887 teaches (FIG. 7(b)) a second contact including a first epitaxial semiconductor pillar (711) and a second epitaxial semiconductor pillar (712) stacked on the first epitaxial semiconductor pillar, wherein a top of the second epitaxial semiconductor pillar is higher than an upper surface of a first metal layer (622), wherein the first epitaxial semiconductor pillar is formed in a first dielectric layer (507) covering a transistor (503), and the second epitaxial semiconductor pillar is formed in a second dielectric layer (621) covering the first dielectric layer, and wherein the first metal layer is disposed between the first and second dielectric layer ([0009]) to prevent punch-through ([0013]).
Further, Yuki ‘583 teaches (FIG. 3) a lower surface of a first metal layer (left 9A and 9B) is coplanar with a top surface of a first epitaxial semiconductor pillar (8b) ([0073]) to suppress short channel effects ([0128]) and to reduce contact resistance ([0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the set of second contacts of Lau ‘282 including a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar, wherein a top of the second epitaxial semiconductor pillar is higher than an upper surface of the first metal layer, wherein the first epitaxial semiconductor pillar is formed in a first dielectric layer covering the plurality of transistors, and the second epitaxial semiconductor pillar is formed in a second dielectric layer covering the first dielectric layer, and wherein the first metal layer is disposed between the first and second dielectric layer as taught by Yamamoto ‘887 to prevent punch-through; and to have formed a lower surface of the first metal layer of Lau ‘282 and Yamamoto ‘887 coplanar with a top surface of the first epitaxial semiconductor pillar as taught by Yuki ‘583 to suppress short channel effects and to reduce contact resistance.
With respect to claim 15, Lau ‘282 teaches wherein a vertical length of the set of first contacts (AP1 and AP2) is shorter than that of the set of second contacts (AP3-AP5) ([0109]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lau ‘282, Yamamoto ‘887, and Yuki ‘583 as applied to claim 14 above, and further in view of Ariizumi ‘694.
With respect to claim 16, Lau ‘282, Yamamoto ‘887, and Yuki ‘583 teach the device as described in claim 14 above with the exception of the additional limitation wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.
However, Ariizumi ‘694 teaches (FIGs. 3 and 4) a gate region (23 or 24) of a transistor connected to a source region (15 or 17) or a drain region (15 or 17) of the transistor directly through a first metal interconnection (central portion of gate electrode) without another metal layer lower than the first metal interconnection to protect a load transistor (col. 3, ln. 4-30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a gate region of one transistor in the plurality of transistors of Lau ‘282, Yamamoto ‘887, and Yuki ‘583 connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection as taught by Ariizumi ‘694 to protect a load transistor.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lau ‘282, Yamamoto ‘887, and Yuki ‘583 as applied to claim 14 above, and further in view of Hamaguchi ‘657 and Yoon ‘084.
With respect to claim 17, Lau ‘282, Yamamoto ‘887, and Yuki ‘583 teach the device as described in claim 14 above with the exception of the additional limitation wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator, and wherein an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ~4λ.
However, Hamaguchi ‘657 teaches (FIG. 1) a bottom surface of a n+ region (27) of a NMOS transistor (43) is fully isolated by a first insulator (17), and a bottom surface of a p+ region (27) of a PMOS transistor (44) is fully isolated by a second insulator (17) to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Further, Yoon ‘084 teaches (FIG. 4A) a length of one transistor is between 3~4λ as art-recognized dimensions for transistors used in an SRAM. Knowing this dimension for a length of one transistor, one of ordinary skill in the art could readily establish an edge distance between an n+ region of an NMOS transistor and a p+ region of a PMOS transistor between 2λ~4λ without undue experimentation. Further, this dimension represents a mere change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Lau ‘282, Yamamoto ‘887, and Yuki ‘583 wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region; and to have formed an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor of Lau ‘282, Yamamoto ‘887, Yuki ‘583, and Hamaguchi ‘657 between 2λ~4λ as taught by Yoon ‘084 because this represents art-recognized dimensions for transistor components used in an SRAM, and because this is merely a matter of scalability and obvious change in size.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bohr et al. (US Patent Application Publication 2011/0156107, hereinafter Bohr ‘107) of record in view of Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657.
With respect to claim 18, Bohr ‘107 teaches (FIG. 2B) a SRAM cell substantially as claimed, comprising:
a plurality of transistors (101) including a first transistor (left 101) and a second transistor (right 101) ([0019, 0029-0030]), wherein the first transistor (left 101) comprises:
a first gate structure (102) with a length ([0019]);
a first channel region (regions of substrate 100 between diffusion regions 106 and below gate 102) ([0019]); and
a first conductive region (106) electrically coupled to the first channel region ([0019]);
wherein the second transistor (right 101) comprises:
a second gate structure (102) with the length ([0019]);
a second channel region (regions of substrate 100 between diffusion regions 106 and below gate 102) ([0019]); and
a second conductive region (106) electrically coupled to the second channel region ([0019]);
wherein an edge (any edge, but in particular the bottom edge) of the first conductive region (106) and an edge of the second conductive region (106) are substantially parallel and opposite to each other ([0019]).
Thus, Bohr ‘107 is shown to teach all the features of the claim with the exception of:
wherein the plurality of transistors include a NMOS transistor and a PMOS transistor, wherein the first transistor is the NMOS transistor and the second transistor is the PMOS transistor;
wherein the first conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area horizontally connected to the heavily doped area of the first conductive region;
wherein the second conductive region includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area horizontally connected to the heavily doped area of the second conductive region;
wherein first and second trenches are within a substrate for carrying the plurality of transistors, a first insulating material is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the first conductive region of the NMOS transistor, and a second insulating material is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the second conductive region of the PMOS transistor, so that the bottom sides of the first and second conductive regions of transistors are isolated from the substrate; and
wherein the lightly doped area of the first conductive region of the NMOS transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and the lightly doped area of the second conductive region of the PMOS transistor is extended from a second revealed sidewall of the substrate revealed by the second trench.
However, Subbanna ‘698 teaches (FIG. 3) CMOS transistors (CMOS integrated circuits) comprising NMOS (doped p-type) and PMOS (doped n-type) transistors (col. 6, ln. 21-37), wherein a first conductive region (33 and 34) includes a heavily doped area (34) and a metal area (33) horizontally connected to the heavily doped area of the first conductive region, and wherein a second conductive region (33 and 34) includes a heavily doped area (34) and a metal area (33) horizontally connected to the heavily doped area of the second conductive region (col. 5, ln. 7-64) to provide ultra-short channel CMOS FET structures in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Further, Esaki ‘395 teaches (FIG. 1A) first and second conductive regions (5 and 12) including a lightly doped area (5) and a heavily doped area (12) laterally extended from a most lateral sidewall of the lightly doped area ([0107]) to prevent short channel effect ([0041]).
Still further, Hamaguchi ‘657 teaches (FIG. 1) first and second trenches (both defined by 17, 21, and 27) within a substrate (40) for carrying a plurality of transistors (43 and 44), a first insulating material (one of 17) is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under a first conductive region (one of 21 and 27) of a NMOS transistor (43), and a second insulating material (another of 17) is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under a second conductive region (another of 21 and 27) of a PMOS transistor (44), so that the bottom sides of the first and second conductive regions of the transistors are isolated from the substrate; wherein a lightly doped area (one of 21) of the first conductive region of the NMOS transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and a lightly doped area (another of 21) of the second conductive region of the PMOS transistor is extended from a second revealed sidewall of the substrate revealed by the second trench to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of transistors of Bohr ‘107 including a NMOS transistor and a PMOS transistor, wherein the first transistor is the NMOS transistor and the second transistor is the PMOS transistor, wherein the first conductive region includes a heavily doped area and a metal area horizontally connected to the heavily doped area of the first conductive region, and wherein the second conductive region includes a heavily doped area and a metal area horizontally connected to the heavily doped area of the second conductive region as taught by Subbanna ‘698 to provide ultra-short channel CMOS FET structures in which both short channel effect and series resistance are reduced; to have formed the first conductive region and the second conductive region of Bohr ‘107 and Subbanna ‘698 including a lightly doped area and a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area as taught by Esaki ‘395 to prevent short channel effect; and to have formed the SRAM cell of Bohr ‘107, Subbanna ‘698, and Esaki ‘395 wherein first and second trenches are within a substrate for carrying the plurality of transistors, a first insulating material is within the first trench and covers bottom side of the first trench to form a first localized isolation structure under the first conductive region of the NMOS transistor, and a second insulating material is within the second trench and covers bottom side of the second trench to form a second localized isolation structure under the second conductive region of the PMOS transistor, so that the bottom sides of the first and second conductive regions of transistors are isolated from the substrate, and wherein the lightly doped area of the first conductive region of the NMOS transistor is extended from a first revealed sidewall of the substrate revealed by the first trench, and the lightly doped area of the second conductive region of the PMOS transistor is extended from a second revealed sidewall of the substrate revealed by the second trench as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region.
With respect to claim 19, Bohr ‘107 teaches comprising a first contact hole (hole housing contact 200) above the first conductive region (106), wherein the first contact hole includes a periphery surrounded by a circumference of the first conductive region ([0020]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bohr ‘107, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 as applied to claim 18 above, and further in view of Ariizumi ‘694.
With respect to claim 20, Bohr ‘107, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 teach the device as described in claim 18 above with the exception of the additional limitation wherein a gate region of a third transistor in the plurality of transistors is connected to a source region or a drain region of the third transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.
However, Ariizumi ‘694 teaches (FIGs. 3 and 4) a gate region (23 or 24) of a transistor connected to a source region (15 or 17) or a drain region (15 or 17) of the transistor directly through a first metal interconnection (central portion of gate electrode) without another metal layer lower than the first metal interconnection to protect a load transistor (col. 3, ln. 4-30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the device of Bohr ‘107, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 wherein a gate region of a third transistor in the plurality of transistors is connected to a source region or a drain region of the third transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection as taught by Ariizumi ‘694 to protect a load transistor.
Response to Arguments
Applicant's arguments filed 2 June 2026 with respect to the 35 U.S.C. 112(a) rejections of claims 1-17 and the related objections to the drawings and the specification have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 20) that under 37 C.F.R. 1.83(a) and MPEP 608.02, the requirement is that the drawings must, “show every feature of the invention specified in the claims,” but there is no requirement that all features of one claim appear within a single figure. Applicant has provided a detailed mapping identifying where each feature is shown in the specification and drawings. The figures therefore comply with 37 C.F.R. 1.83(a) because the drawings, taken as a whole, show every claimed feature. Applicant further argues (remarks, p. 21) that under MPEP 608.01(o), antecedent basis requires that the specification reasonably convey possession of the claimed subject matter; it does not require that all features in one claim be described or depicted in a single location or single figure. The present specification provides explicit disclosure for each element, and the terminology used in the claims is supported by corresponding language in the description. Applicant further argues (remarks, pp. 23-24) that under MPEP 2163, the written description requirement is satisfied when the specification reasonably conveys to a person of ordinary skill in the art that the inventor had possession of the claimed invention as of the filing date. Importantly, the MPEP does not require that every claimed feature must be described in the specification as part of a single embodiment, figure, or passage. Instead, the written description may be supported by the specification as a whole, including multiple sections and multiple figures. Neither 35 U.S.C. 112(a) nor the MPEP requires the specification to explicitly describe the simultaneous practice or explicit combination of every claimed feature within a single paragraph or illustration. Applicant cites at least paragraphs [0100] and [0103] of the specification to allegedly show that the specification does not describe isolated unrelated embodiments, but instead describes interoperable features of the same SRAM architecture. Moreover, the written description requirement does not require ipsissimis verbis support, nor does it require that every claimed combination be illustrated in one figure exactly as claimed. A person of ordinary skill in the art would readily understand from the disclosure that the disclosed transistor structures, direct interconnect structures, STI/isolation structures, and SRAM routing structures are intended to be combinable portions of the same SRAM design framework. The claims merely recite combinations that are expressly or inherently supported by the integrated teachings of the specification and drawings. The specification repeatedly describes the disclosed technologies as improvements directed toward the same objective of SRAM scaling reduction and routing optimization. The disclosure therefore provides more than sufficient “blaze marks” directing a skilled artisan toward the presently claimed combinations. Examiner respectfully disagrees.
The outstanding 35 U.S.C. 112(a) rejections are raised not merely because the claimed features are not described in the specification or shown in the same figure as part of a single embodiment, but rather because there is no suggestion in the original disclosure that Applicant had in his or her possession the claimed subject matter in the combination of elements as claimed at the time the application was effectively filed. Although some of these claimed elements may be disclosed individually, there is insufficient disclosure to demonstrate that Applicant had in his or her possession each of the cited claimed elements in combination.
Examiner agrees that there is no requirement that all features of one claim appear within a single figure, or that all features of a claim be described or depicted in a single location. However, the written description must convey to one of ordinary skill in the art that the inventor had possession of the claimed invention. The claims above-rejected under 35 U.S.C. 112(a) are directed to varying elements not disclosed in combination. In fact, some claimed elements are disclosed in contradiction to other claimed elements. For example, claim 1 requires both “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” and, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region.” FIGs. 25-30 disclosing “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area,” also disclose wherein the first and second STI regions (491 and 492) have a top surface lower than a top surface of a gate conductive region (33). This is the opposite of what’s claimed. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is instead disclosed in FIGs. 13-19 which disclose only a single-element source (1704) and drain (1706). One of ordinary skill in the art would not presume that every possible permutation of every possible combination of elements described in the lengthy description, even those in contradiction to elements explicitly disclosed, had been conceived by Applicant. Rather, one of ordinary skill in the art would presume that Applicant had in their possession the subject matter explicitly disclosed.
The corresponding objection to the specification for lacking antecedent basis for the claimed subject matter is supplied for similar reasons, namely that the specification fails to provide support for the claimed subject matter in the combination of elements as claimed.
The drawing[s] [ ] must show every feature of the invention specified in the claims. 37 C.F.R. 1.83(a). The outstanding objection to the drawings is maintained for failing to show the claimed subject matter in the combination of elements as claimed. Any structural detail that is of sufficient importance to be described should be shown in the drawing. Ex parte Good, 1911 C.D. 43, 164 OG 739 (Comm'r Pat. 1911).
Applicant’s amendments to claims 19 and 20 are sufficient to overcome the 35 U.S.C. 112(b) rejections of claims 19 and 20 made in the final rejection filed 2 March 2026. The 35 U.S.C. 112(b) rejections of claims 19 and 20 have been withdrawn.
Applicant's arguments filed 2 June 2026 with respect to the 35 U.S.C. 103 rejections of claims 1, 9, and 18 have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 26) that the prior art of record fails to teach the newly-presented limitations of claims 1, 9, and 18. Specifically, Applicant argues (remarks, p. 29) that Hamaguchi ‘657 merely teaches that the source/drain region (27) is formed of a single material, namely polysilicon (21). Hamaguchi ‘657 does not disclose or suggest that the source/drain region includes a composite structure formed by different materials in different sites. More specifically, in Hamaguchi ‘657, no metal material is formed within the trenches, no lightly doped/heavily doped/metal composite configuration is disclosed, and no trench-defined composite source/drain structure formed over localized isolation structures is taught or suggested. Rather, Hamaguchi ‘657 merely discloses a conventional polysilicon source/drain structure disposed over the insulating film (17). Furthermore, Hamaguchi ‘657 does not disclose or suggest that, “each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area horizontally connected to the heavily doped area,” as claimed. Examiner respectfully disagrees.
Hamaguchi ‘657 teaches the newly-presented limitations of claims 1, 9, and 18 as set forth in the above rejection. Subbanna ‘698 and Esaki ‘395 are cited to address the source/drain region including a composite structure formed by different materials in different sites as recited in the limitation, “each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area laterally extended from a most lateral sidewall of the lightly doped area and a metal area horizontally connected to the heavily doped area.” One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues (remarks, p. 30) that Subbanna ‘698 and Esaki ‘395 disclose fundamentally different transistor architectures that cannot be readily combined. Subbanna ‘698 relies on metal source/drain deposits (33) disposed over the substrate to form a horizontal metal-semiconductor structure for reducing short-channel effects and series resistance. In contrast, Esaki ‘395 relies on conventional doped source/drain regions directly formed in the substrate and does not disclose or suggest any horizontal lightly doped/heavily doped/metal-composite region. Examiner respectfully disagrees.
Subbanna ‘698 teaches (FIG. 3) each of a drain region (33 and 34) and a source region (33 and 34) of a transistor (30) including a heavily doped area (34) and a metal area (33) horizontally connected to the heavily doped area (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20). Esaki ‘395 teaches (FIG. 1A) a drain region (5 and 12) and a source region (5 and 12) including a lightly doped area (5) and a heavily doped area (12) adjacent to the lightly doped area ([0107]) to prevent short channel effect ([0041]). Subbanna ‘698 and Esaki ‘395 are analogous art in the field of forming source/drain regions of a semiconductor device. One of ordinary skill in the art could combine the source/drain components of Subbanna ‘698 and Esaki ‘395 with a reasonable expectation of success.
Applicant’s arguments with respect to the 35 U.S.C. 103 rejection of claim(s) 4, 14, 16, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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