DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 23 December 2025 is acknowledged. Claims 1, 9, 14, and 18 have been amended. Claims 1-20 are pending.
Information Disclosure Statement
Information disclosure statement (IDS) filed 22 January 2026 has been fully considered.
Examiner identifies three non-patent literature (NPL) documents filed 22 January 2026 that were neither cited in the corresponding IDS nor any other IDS: a decision of refusal for Japanese Patent Application No. 2024-125159, a communication pursuant to Article 94(3) EPC for European Patent Application No. 22 160 535.5, and a final rejection for US Patent Application No. 17/528481.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claims 1, 4-9, 14, 16, 17, and 20, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area” and “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area” in combination with “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar” in combination with “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” and, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the first conductive region includes a doped area and a metal area” and “wherein the second conductive region includes a doped area and a metal area,” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the subject matter of claims 1, 4-9, 14, 16, 17, and 20, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer” in combination with “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area” and “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area” in combination with “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar” in combination with “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer,” “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator” in combination with “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” and, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection” in combination with “wherein the first conductive region includes a doped area and a metal area” and “wherein the second conductive region includes a doped area and a metal area,” must find support in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitations, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” and, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 4 recites the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” This limitation is not supported in combination with the limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” of claim 1 from which the claim depends. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30 which do not show the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 5 recites the limitation, “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed.” This limitation is not supported in combination with the limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed,” is disclosed in at least FIGs. 27 and 30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 6 recites the limitation, “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region.” This limitation is not supported in combination with the limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19 which do not show the limitation, “wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 7 recites the limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator.” This limitation is not supported in combination with the limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. The limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator,” is disclosed in at least FIGs. 25 and 28. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 8 recites the limitation, “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer.” This limitation is not supported in combination with the limitations, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” and, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” of claim 1 from which the claim depends. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30. The limitation, “wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. Neither of these limitations are disclosed with, “the set of first contacts are connected to a first metal layer, and the set of second contacts are connected to a second metal layer but disconnected from the first metal layer.” As best understood by Examiner, these features are not disclosed in combination.
Claim 9 recites the limitations, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” and, “wherein a top surface of the STI region is higher than a top surface of a gate conductive region.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area,” is disclosed in at least FIGs. 25-30. The limitation, “wherein a top surface of the STI region is higher than a top surface of a gate conductive region,” is disclosed in at least FIGs. 13-19. However, as best understood by Examiner, these two features are not disclosed in combination.
Claim 14 recites the limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” and, “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer.” These limitations taken together are not supported by the disclosure as originally filed. The limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” is disclosed in at least FIGs. 20-24 which do not show the limitation, “a first metal layer [ ]; a second metal layer [ ]; and a third metal layer [ ]; wherein [ ] the set of first contacts are connected to the first metal layer, and the set of second contacts are directly connected to the second metal layer but disconnected from the first metal layer.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 16 recites the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” This limitation is not supported in combination with the limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” of claim 14 from which the claim depends. The limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” is disclosed in at least FIGs. 20-24 which do not show the limitation, “wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.” As best understood by Examiner, these two features are not disclosed in combination.
Claim 17 recites the limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator.” This limitation is not supported in combination with the limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” of claim 14 from which the claim depends. The limitation, “wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar,” is disclosed in at least FIGs. 20-24. The limitation, “wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator,” is disclosed in at least FIGs. 25 and 28. However, as best understood by Examiner, these two features are not disclosed in combination.
Claims 2, 3, 10-13, and 15 are rejected for merely containing the flaws of the parent claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation, “the first contact hole.” There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation, “a gate region.” It is unclear how this feature is differentiated from the previously-recited, “a first gate structure,” and, “a second gate structure.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US Patent Application Publication 2016/0240541, hereinafter Liaw ‘541) in view of Subbanna (US Patent 5,338,698, hereinafter Subbanna ‘698) and Esaki (US Patent Application Publication 2001/0050395, hereinafter Esaki ‘395), all three of record.
With respect to claim 1, Liaw ‘541 teaches (FIGs. 1, 2, and 5-7) a SRAM cell substantially as claimed, comprising:
a substrate (11) having a horizontal surface ([0031]);
a plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) within the substrate (11), each of the transistors includes a source region (“source and drain regions”), a drain region (“source and drain regions”) and a gate structure (“gate”) located between the source region and the drain region ([0022, 0031]);
a first shallow trench isolation (STI) region (17) disposed next to the source region of a first transistor of the plurality of transistors ([0032]);
a second STI region (17) disposed next to the drain region of the first transistor of the plurality of transistors ([0032]);
a set of contacts (gate and Contact-1) coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0034-0035]);
a word-line (WL) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0024]);
a bit-line (BL) and a bit line bar (BLB) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]);
a VDD contacting line (Vdd) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]); and
a VSS contacting line (Vss) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]).
Thus, Liaw ‘541 is shown to teach all the features of the claim with the exception of:
wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area disposed on one side of the heavily doped area and horizontally connected to the heavily doped area; and
wherein the first and second STI regions respectively have a top surface higher than a top surface of a gate conductive region of the gate structure of the first transistor.
However, Subbanna ‘698 teaches (FIG. 3) each of a drain region (33 and 34) and a source region (33 and 34) of a transistor (30) including a heavily doped area (34) and a metal area (33) disposed on one side of the heavily doped area and horizontally connected to the heavily doped area (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Further, Esaki ‘395 teaches (FIG. 1A) first and second STI regions (10) having a top surface higher than a top surface of a gate conductive region (3) of a gate structure (14) to fully isolate transistors in a process that allows for self-alignment of said STI regions ([0107]); and each of a drain region (5 and 12) and a source region (5 and 12) of a transistor including a lightly doped area (5) and a heavily doped area (12) adjacent to the lightly doped area ([0107]) to prevent short channel effect ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 including a heavily doped area and a metal area disposed on one side of the heavily doped area and horizontally connected to the heavily doped area as taught by Subbanna ‘698 to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced; to have formed the first and second STI regions respectively of Liaw ‘541 having a top surface higher than a top surface of a gate conductive region of the gate structure of the first transistor as taught by Esaki ‘395 to fully isolate transistors in a process that allows for self-alignment of said STI regions; and to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 and Subbanna ‘698 including a lightly doped area and a heavily doped area adjacent to the lightly doped area as taught by Esaki ‘395 to prevent short channel effect.
With respect to claim 4, Liaw ‘541 teaches (FIG. 6) wherein a gate region (G2) of one transistor (PU2) in the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) is connected to a source region or a drain region (55) of the one transistor directly through a first metal interconnection (WLC and 41) without another metal layer lower than the first metal interconnection ([0058]).
With respect to claim 6, Liaw ‘541, Subbanna ‘698, and Esaki ‘395 teach the device as described in claim 1 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitation wherein a first contact hole for one of the contacts is disposed between the first STI region and a side of the gate structure of the first transistor, and a second contact hole for another one of the contacts is disposed between the second STI region and an opposite side of the gate structure of the first transistor, wherein the first contact hole corresponds to the metal area of the source region and the second contact hole corresponds to the metal area of the drain region.
However, Esaki ‘395 teaches (FIG. 1A) a first contact hole (hole for left contact 13) for one of contacts (13) disposed between a first STI region (left STI 10) and a side of a gate structure (14) of a first transistor, and a second contact hole (hole for right contact 13) for another one of the contacts is disposed between a second STI region (right STI 10) and an opposite side of the gate structure of the first transistor to provide isolated electrical contact to the source and drain of the transistor ([0107]).
Further, Subbanna ‘698 teaches (FIG. 3) contacts (S and D) corresponding to metal areas (33) of the source and drain regions (33 and 34) (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, and Esaki ‘395 wherein a first contact hole for one of the contacts is disposed between the first STI region and a side of the gate structure of the first transistor, and a second contact hole for another one of the contacts is disposed between the second STI region and an opposite side of the gate structure of the first transistor as taught by Esaki ‘395 to provide isolated electrical contact to the source and drain of the transistor; and to have formed the first contact hole and the second contact hole of Liaw ‘541, Subbanna ‘698, and Esaki ‘395 corresponding to the metal area of the source region and to the metal area of the drain region respectively as taught by Subbanna ‘698 to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced.
With respect to claim 8, Liaw ‘541 teaches wherein the set of contacts (gate and Contact-1) comprise a set of first contacts (gate) and a set of second contacts (Contact-1), the set of first contacts are connected to a first metal layer (Gate_CO), and the set of second contacts are connected to a second metal layer (Contact-2) but disconnected from the first metal layer ([0036]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, and Esaki ‘395 as applied to claim 1 above, and further in view of Blatchford (US Patent Application Publication 2013/0069168, hereinafter Blatchford ‘168) of record.
With respect to claim 2, Liaw ‘541, Subbanna ‘698, and Esaki ‘395 teach the device as described in claim 1 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitation wherein as a minimum feature size (λ) of the SRAM cell gradually decreases from 28nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ2) is the same or substantially the same, when λ is decreased from 28nm to 5nm, the area size of the SRAM cell is between 84λ2~102λ2.
However, Liaw ‘541 teaches SRAM nodes below 28nm, including 22nm, 20nm, and 14nm using existing photolithographic tools with corresponding limits on lithography and feature sizes, thus produced at a lowered cost ([0061]). Process nodes between 5nm-28nm have been developed before the effective filing date of the claimed invention. Maintaining an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same is merely a matter of scalability and change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). One of ordinary skill in the art would be motivated to maintain an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same to develop denser memory allowing more storage on a smaller footprint.
Further, Blatchford ‘168 teaches (FIG. 1) an area size of an SRAM cell in terms of square of a minimum feature size (λ) of about 150λ2 for a feature size 20nm to provide a very significant area savings for integrated circuits with large SRAM memory arrays ([0032]). This falls within the disclosed dimensions of an area size of an SRAM cell in terms of square of a minimum feature size (λ) between 84λ2-672λ2 for feature sizes between 5nm-28nm. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Liaw ‘541, Subbanna ‘698, and Esaki ‘395 wherein as a minimum feature size (λ) of the SRAM cell gradually decreases from 28nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ2) is the same or substantially the same, when λ is decreased from 28nm to 5nm, the area size of the SRAM cell is between 84λ2~102λ2 as taught by Blatchford ‘168 because this is merely a matter of scalability and obvious change in size to develop denser memory allowing more storage on a smaller footprint, and to provide a very significant area savings for integrated circuits with large SRAM memory arrays.
Applicant is reminded that any features critical to achieving the claimed dimensions must be claimed.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Blatchford ‘168 as applied to claim 2 above, and further in view of Yoon et al. (US Patent Application Publication 2010/0289084, hereinafter Yoon ‘084) of record.
With respect to claim 3, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Blatchford ‘168 teach the device as described in claim 2 above with the exception of the additional limitation wherein a length of one transistor is between 3~4λ.
However, Yoon ‘084 teaches (FIG. 4A) a length of one transistor is between 3~4λ as art-recognized dimensions for transistors used in an SRAM. Further, this dimension represents a mere change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a length of one transistor of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Blatchford ‘168 between 3~4λ as taught by Yoon ‘084 because this represents art-recognized dimensions for transistors used in an SRAM, and because this is merely a matter of scalability and obvious change in size.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, and Esaki ‘395 as applied to claim 1 above, and further in view of Do et al. (US Patent Application Publication 2022/0059460, hereinafter Do ‘460) of record.
With respect to claim 5, Liaw ‘541, Subbanna ‘698, and Esaki ‘395 teach the device as described in claim 1 above with the exception of the additional limitation wherein the VDD contacting line or the VSS contacting line is distributed under the horizontal surface of the substrate from which the plurality of transistors are formed.
However, Do ‘460 teaches (FIGs. 10A and 11) a VDD contacting line or a VSS contacting line (BP) distributed under a horizontal surface of a substrate (101) from which a plurality of transistors are formed so wiring lines may be designed more freely, and a standard cell having the same number of tracks (a number of wiring lines or the like) may be implemented to have a relatively smaller cell height, or a relatively larger number of tracks may be guaranteed in a standard cell having the same cell height ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the VDD contacting line or the VSS contacting line of Liaw ‘541, Subbanna ‘698, and Esaki ‘395 distributed under the horizontal surface of the substrate from which the plurality of transistors are formed as taught by Do ‘460 so wiring lines may be designed more freely, and a standard cell having the same number of tracks (a number of wiring lines or the like) may be implemented to have a relatively smaller cell height, or a relatively larger number of tracks may be guaranteed in a standard cell having the same cell height.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541, Subbanna ‘698, and Esaki ‘395 as applied to claim 1 above, and further in view of Hamaguchi (US Patent Application Publication 2006/0131657, hereinafter Hamaguchi ‘657) of record and Yoon ‘084.
With respect to claim 7, Liaw ‘541, Subbanna ‘698, and Esaki ‘395 teach the device as described in claim 1 above with the exception of the additional limitation wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator, and a third STI region is between the NMOS transistor and the PMOS transistor, and an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ~4λ.
However, Hamaguchi ‘657 teaches (FIG. 1) a bottom surface of a n+ region (27) of a NMOS transistor (43) is fully isolated by a first insulator (17), and a bottom surface of a p+ region (27) of a PMOS transistor (44) is fully isolated by a second insulator (17) to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Further, Yoon ‘084 teaches (FIG. 1) a third STI region (11) between an NMOS transistor and a PMOS transistor to isolate said NMOS transistor from said PMOS transistor ([0029]).
Still further, Yoon ‘084 teaches (FIG. 4A) a length of one transistor is between 3~4λ as art-recognized dimensions for transistors used in an SRAM. Knowing this dimension for a length of one transistor, one of ordinary skill in the art could readily establish an edge distance between an n+ region of an NMOS transistor and a p+ region of a PMOS transistor between 2λ~4λ without undue experimentation. Further, this dimension represents a mere change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, and Esaki ‘395 wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region; to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 further comprising a third STI region is between the NMOS transistor and the PMOS transistor as taught by Yoon ‘084 to isolate said NMOS transistor from said PMOS transistor; and to have formed an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Hamaguchi ‘657 between 2λ~4λ as taught by Yoon ‘084 because this represents art-recognized dimensions for transistor components used in an SRAM, and because this is merely a matter of scalability and obvious change in size.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw ‘541 in view of Subbanna ‘698, Esaki ‘395, and Blatchford ‘168.
With respect to claim 9, Liaw ‘541 teaches (FIGs. 1, 2, and 5-7) a SRAM cell substantially as claimed, comprising:
a plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2), wherein a shallow trench isolation (STI) region (17) surrounds a first transistor of the plurality of transistors, and the first transistor includes a source region (“source and drain regions”), a drain region (“source and drain regions”) and a gate structure (“gate”) located between the source region and the drain region ([0022, 0031-0032]);
a set of contacts (gate and Contact-1) coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0034-0035]);
a word-line (WL) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0024]);
a bit-line (BL) and a bit line bar (BLB) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]);
a VDD contacting line (Vdd) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]); and
a VSS contacting line (Vss) electrically coupled to the plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) ([0022]).
Thus, Liaw ‘541 is shown to teach all the features of the claim with the exception of:
wherein each of the drain region and the source region of the first transistor includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area disposed on one side of the heavily doped area and horizontally connected to the heavily doped area;
wherein a top surface of the STI region is higher than a top surface of a gate conductive region of the gate structure of the first transistor; and
wherein, an area of the SRAM cell is not greater than 672λ2 when a minimum feature size (λ) is 5nm; or the area of the SRAM cell is not greater than 440λ2 when the minimum feature size is 7nm; or the area of the SRAM cell is not greater than 300λ2 when the minimum feature size is between 7nm to 10nm; or the area of the SRAM cell is not greater than 204λ2 when the minimum feature size (λ) is between 10nm to 16nm; or the area of the SRAM cell is not greater than 152λ2 when the minimum feature size (λ) is between 16nm to 22nm; or the area of the SRAM cell is not greater than 139λ2 when the minimum feature size (λ) is between 22nm to 28nm.
However, Subbanna ‘698 teaches (FIG. 3) each of a drain region (33 and 34) and a source region (33 and 34) of a transistor (30) including a heavily doped area (34) and a metal area (33) disposed on one side of the heavily doped area and horizontally connected to the heavily doped area (col. 5, ln. 7-64) to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Further, Esaki ‘395 teaches (FIG. 1A) a top surface of STI regions (10) higher than a top surface of a gate conductive region (3) of a gate structure (14) to fully isolate transistors in a process that allows for self-alignment of said STI regions ([0107]); and each of a drain region (5 and 12) and a source region (5 and 12) of a transistor including a lightly doped area (5) and a heavily doped area (12) adjacent to the lightly doped area ([0107]) to prevent short channel effect ([0041]).
Still further, Liaw ‘541 teaches SRAM nodes below 28nm, including 22nm, 20nm, and 14nm using existing photolithographic tools with corresponding limits on lithography and feature sizes, thus produced at a lowered cost ([0061]). Forming an area of the SRAM cell not greater than 672λ2 when a minimum feature size (λ) is 5nm; or the area of the SRAM cell not greater than 440λ2 when the minimum feature size is 7nm; or the area of the SRAM cell not greater than 300λ2 when the minimum feature size is between 7nm to 10nm; or the area of the SRAM cell not greater than 204λ2 when the minimum feature size (λ) is between 10nm to 16nm; or the area of the SRAM cell not greater than 152λ2 when the minimum feature size (λ) is between 16nm to 22nm; or the area of the SRAM cell not greater than 139λ2 when the minimum feature size (λ) is between 22nm to 28nm is merely a matter of scalability and change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). One of ordinary skill in the art would be motivated to form an SRAM cell at these dimensions to develop denser memory allowing more storage on a smaller footprint.
Still further, Blatchford ‘168 teaches (FIG. 1) an area size of an SRAM cell in terms of square of a minimum feature size (λ) of about 150λ2 for a feature size 20nm to provide a very significant area savings for integrated circuits with large SRAM memory arrays ([0032]). This falls within the disclosed dimensions of an area size of an SRAM cell in terms of square of a minimum feature size (λ) between 84λ2-672λ2 for feature sizes between 5nm-28nm. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 including a heavily doped area and a metal area disposed on one side of the heavily doped area and horizontally connected to the heavily doped area as taught by Subbanna ‘698 to provide an ultra-short channel FET structure in which both short channel effect and series resistance are reduced; to have formed a top surface of the STI region of Liaw ‘541 higher than a top surface of a gate conductive region of the gate structure of the first transistor as taught by Esaki ‘395 to fully isolate transistors in a process that allows for self-alignment of said STI regions; to have formed each of the drain region and the source region of the first transistor of Liaw ‘541 and Subbanna ‘698 including a lightly doped area and a heavily doped area adjacent to the lightly doped area as taught by Esaki ‘395 to prevent short channel effect; and to have formed the SRAM cell of Liaw ‘541 wherein, an area of the SRAM cell is not greater than 672λ2 when a minimum feature size (λ) is 5nm; or the area of the SRAM cell is not greater than 440λ2 when the minimum feature size is 7nm; or the area of the SRAM cell is not greater than 300λ2 when the minimum feature size is between 7nm to 10nm; or the area of the SRAM cell is not greater than 204λ2 when the minimum feature size (λ) is between 10nm to 16nm; or the area of the SRAM cell is not greater than 152λ2 when the minimum feature size (λ) is between 16nm to 22nm; or the area of the SRAM cell is not greater than 139λ2 when the minimum feature size (λ) is between 22nm to 28nm as taught by Blatchford ‘168 because this is merely a matter of scalability and obvious change in size to develop denser memory allowing more storage on a smaller footprint, and to provide a very significant area savings for integrated circuits with large SRAM memory arrays.
Applicant is reminded that any features critical to achieving the claimed dimensions must be claimed.
With respect to claims 10-13, Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Blatchford ‘168 teach the device as described in claim 9 above, but primary reference Liaw ‘541 does not explicitly teach the additional limitations wherein the area of the SRAM cell is within the range of 84λ2~672λ2 when the minimum feature size is 5nm; wherein the area of the SRAM cell is within the range of 84λ2~440λ2 when the minimum feature size is 7nm; wherein when the minimum feature size is between 10nm to 16nm, the area of the SRAM cell is within the range of 84λ2~204λ2; and wherein when λ is between 22nm to 28nm, the area of the SRAM cell is within the range of 84λ2~139λ2.
However, Liaw ‘541 teaches SRAM nodes below 28nm, including 22nm, 20nm, and 14nm using existing photolithographic tools with corresponding limits on lithography and feature sizes, thus produced at a lowered cost ([0061]). Process nodes between 5nm-28nm have been developed before the effective filing date of the claimed invention. Maintaining an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same is merely a matter of scalability and change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). One of ordinary skill in the art would be motivated to maintain an area size of an SRAM cell in terms of square of a minimum feature size (λ) the same or substantially the same to develop denser memory allowing more storage on a smaller footprint.
Further, Blatchford ‘168 teaches (FIG. 1) an area size of an SRAM cell in terms of square of a minimum feature size (λ) of about 150λ2 for a feature size 20nm to provide a very significant area savings for integrated circuits with large SRAM memory arrays ([0032]). This falls within the disclosed dimensions of an area size of an SRAM cell in terms of square of a minimum feature size (λ) between 84λ2-672λ2 for feature sizes between 5nm-28nm. In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); and In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Liaw ‘541, Subbanna ‘698, Esaki ‘395, and Blatchford ‘168 wherein the area of the SRAM cell is within the range of 84λ2~672λ2 when the minimum feature size is 5nm; wherein the area of the SRAM cell is within the range of 84λ2~440λ2 when the minimum feature size is 7nm; wherein when the minimum feature size is between 10nm to 16nm, the area of the SRAM cell is within the range of 84λ2~204λ2; and wherein when λ is between 22nm to 28nm, the area of the SRAM cell is within the range of 84λ2~139λ2 as taught by Blatchford ‘168 because this is merely a matter of scalability and obvious change in size to develop denser memory allowing more storage on a smaller footprint, and to provide a very significant area savings for integrated circuits with large SRAM memory arrays.
Applicant is reminded that any features critical to achieving the claimed dimensions must be claimed.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US Patent Application Publication 2015/0357282, hereinafter Lau ‘282) in view of Yamamoto et al. (Japanese Kokai Publication H10-27887, hereinafter Yamamoto ‘887), both of record.
With respect to claim 14, Lau ‘282 teaches (FIGs. 4-5C) a SRAM cell as substantially as claimed, comprising:
a plurality of transistors (defined within AC3 of logic cell 300) ([0105-0106]);
a plurality of contacts (AP1-AP5) coupled to the plurality of transistors ([0108]);
a first metal layer (M1) horizontally extended and disposed above and electrically coupled to the plurality of transistors ([0110]);
a second metal layer (M2) disposed above the first metal layer (M1) and electrically coupled to the plurality of transistors ([0101]); and
a third metal layer (M3) disposed above the second metal layer (M2) and electrically coupled to the plurality of transistors ([0112]);
wherein the plurality of contacts (AP1-AP5) comprise a set of first contacts (AP1 and AP2) and a set of second contacts (AP3-AP5), the set of first contacts are connected to the first metal layer (M1), and the set of second contacts are directly connected to the second metal layer (M2) but disconnected from the first metal layer ([0109]).
Thus, Lau ‘282 is shown to teach all the features of the claim with the exception of wherein the set of second contacts includes a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar, wherein a top of the second epitaxial semiconductor pillar is higher than an upper surface of the first metal layer.
However, Yamamoto ‘887 teaches (FIG. 7(b)) a second contact including a first epitaxial semiconductor pillar (711) and a second epitaxial semiconductor pillar (712) stacked on the first epitaxial semiconductor pillar, wherein a top of the second epitaxial semiconductor pillar is higher than an upper surface of a first metal layer (504) ([0009]) to prevent punch-through ([0013]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the set of second contacts of Lau ‘282 including a first epitaxial semiconductor pillar and a second epitaxial semiconductor pillar stacked on the first epitaxial semiconductor pillar, wherein a top of the second epitaxial semiconductor pillar is higher than an upper surface of the first metal layer as taught by Yamamoto ‘887 to prevent punch-through.
With respect to claim 15, Lau ‘282 teaches wherein a vertical length of the set of first contacts (AP1 and AP2) is shorter than that of the set of second contacts (AP3-AP5) ([0109]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lau ‘282 and Yamamoto ‘887 as applied to claim 14 above, and further in view of Liaw ‘541.
With respect to claim 16, Lau ‘282 and Yamamoto ‘887 teach the device as described in claim 14 above with the exception of the additional limitation wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.
However, Liaw ‘541 teaches (FIG. 6) a gate region (G2) of one transistor (PU2) in a plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) connected to a source region or a drain region (55) of the one transistor directly through a first metal interconnection (WLC and 41) without another metal layer lower than the first metal interconnection ([0058]) to provide an SRAM cell structure with improved connectivity and layout for advanced semiconductor processes ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the device of Lau ‘282 and Yamamoto ‘887 wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection as taught by Liaw ‘541 to provide an SRAM cell structure with improved connectivity and layout for advanced semiconductor processes.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lau ‘282 and Yamamoto ‘887 as applied to claim 14 above, and further in view of Hamaguchi ‘657 and Yoon ‘084.
With respect to claim 17, Lau ‘282 and Yamamoto ‘887 teach the device as described in claim 14 above with the exception of the additional limitation wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator, and wherein an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor is between 2λ~4λ.
However, Hamaguchi ‘657 teaches (FIG. 1) a bottom surface of a n+ region (27) of a NMOS transistor (43) is fully isolated by a first insulator (17), and a bottom surface of a p+ region (27) of a PMOS transistor (44) is fully isolated by a second insulator (17) to reduce the junction capacitance and the leak current of the source/drain region ([0032-0033]).
Further, Yoon ‘084 teaches (FIG. 4A) a length of one transistor is between 3~4λ as art-recognized dimensions for transistors used in an SRAM. Knowing this dimension for a length of one transistor, one of ordinary skill in the art could readily establish an edge distance between an n+ region of an NMOS transistor and a p+ region of a PMOS transistor between 2λ~4λ without undue experimentation. Further, this dimension represents a mere change in size. A change in size is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the SRAM cell of Lau ‘282 and Yamamoto ‘887 wherein a bottom surface of a n+ region of a NMOS transistor of the plurality of transistors is fully isolated by a first insulator, and a bottom surface of a p+ region of a PMOS transistor of the plurality of transistors is fully isolated by a second insulator as taught by Hamaguchi ‘657 to reduce the junction capacitance and the leak current of the source/drain region; and to have formed an edge distance between the n+ region of the NMOS transistor and the p+ region of the PMOS transistor of Lau ‘282, Yamamoto ‘887, and Hamaguchi ‘657 between 2λ~4λ as taught by Yoon ‘084 because this represents art-recognized dimensions for transistor components used in an SRAM, and because this is merely a matter of scalability and obvious change in size.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bohr et al. (US Patent Application Publication 2011/0156107, hereinafter Bohr ‘107) of record in view of Subbanna ‘698 and Esaki ‘395.
With respect to claim 18, Bohr ‘107 teaches (FIG. 2B) a SRAM cell substantially as claimed, comprising:
a plurality of transistors (101) including a first transistor (left 101) and a second transistor (right 101) ([0019, 0029-0030]), wherein the first transistor (left 101) comprises:
a first gate structure (102) with a length ([0019]);
a first channel region (regions of substrate 100 between diffusion regions 106 and below gate 102) ([0019]); and
a first conductive region (106) electrically coupled to the first channel region ([0019]);
wherein the second transistor (right 101) comprises:
a second gate structure (102) with the length ([0019]);
a second channel region (regions of substrate 100 between diffusion regions 106 and below gate 102) ([0019]); and
a second conductive region (106) electrically coupled to the second channel region ([0019]);
wherein an edge (any edge, but in particular the bottom edge) of the first conductive region (106) and an edge of the second conductive region (106) are substantially parallel and opposite to each other ([0019]).
Thus, Bohr ‘107 is shown to teach all the features of the claim with the exception of:
wherein the plurality of transistors include a NMOS transistor and a PMOS transistor, wherein the first transistor is the NMOS transistor and the second transistor is the PMOS transistor;
wherein the first conductive region includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area disposed on one side of the heavily doped area of the first conductive region and horizontally connected to the heavily doped area of the first conductive region; and
wherein the second conductive region includes a lightly doped area, a heavily doped area adjacent to the lightly doped area and a metal area disposed on one side of the heavily doped area of the second conductive region and horizontally connected to the heavily doped area of the second conductive region.
However, Subbanna ‘698 teaches (FIG. 3) CMOS transistors (CMOS integrated circuits) comprising NMOS (doped p-type) and PMOS (doped n-type) transistors (col. 6, ln. 21-37), wherein a first conductive region (33 and 34) includes a heavily doped area (34) and a metal area (33) disposed on one side of the heavily doped area of the first conductive region and horizontally connected to the heavily doped area of the first conductive region, and wherein a second conductive region (33 and 34) includes a heavily doped area (34) and a metal area (33) disposed on one side of the heavily doped area of the second conductive region and horizontally connected to the heavily doped area of the second conductive region (col. 5, ln. 7-64) to provide ultra-short channel CMOS FET structures in which both short channel effect and series resistance are reduced (col. 3, ln. 12-20).
Further, Esaki ‘395 teaches (FIG. 1A) first and second conductive regions (5 and 12) including a lightly doped area (5) and a heavily doped area (12) adjacent to the lightly doped area ([0107]) to prevent short channel effect ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of transistors of Bohr ‘107 including a NMOS transistor and a PMOS transistor, wherein the first transistor is the NMOS transistor and the second transistor is the PMOS transistor; wherein the first conductive region includes a heavily doped area and a metal area disposed on one side of the heavily doped area of the first conductive region and horizontally connected to the heavily doped area of the first conductive region; and wherein the second conductive region includes a heavily doped area and a metal area disposed on one side of the heavily doped area of the second conductive region and horizontally connected to the heavily doped area of the second conductive region as taught by Subbanna ‘698 to provide ultra-short channel CMOS FET structures in which both short channel effect and series resistance are reduced; and to have formed the first conductive region and the second conductive region of Bohr ‘107 and Subbanna ‘698 including a lightly doped area and a heavily doped area adjacent to the lightly doped area as taught by Esaki ‘395 to prevent short channel effect.
With respect to claim 19, Bohr ‘107 teaches wherein the first contact hole (hole housing contact 200) includes a periphery surrounded by a circumference of the first conductive region (106) ([0020]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bohr ‘107, Subbanna ‘698, and Esaki ‘395 as applied to claim 18 above, and further in view of Liaw ‘541.
With respect to claim 20, Bohr ‘107, Subbanna ‘698, and Esaki ‘395 teach the device as described in claim 18 above with the exception of the additional limitation wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection.
However, Liaw ‘541 teaches (FIG. 6) a gate region (G2) of one transistor (PU2) in a plurality of transistors (PG1, PG2, PU1, PU2, PD1, and PD2) connected to a source region or a drain region (55) of the one transistor directly through a first metal interconnection (WLC and 41) without another metal layer lower than the first metal interconnection ([0058]) to provide an SRAM cell structure with improved connectivity and layout for advanced semiconductor processes ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the device of Bohr ‘107, Subbanna ‘698, and Esaki ‘395 wherein a gate region of one transistor in the plurality of transistors is connected to a source region or a drain region of the one transistor directly through a first metal interconnection without another metal layer lower than the first metal interconnection as taught by Liaw ‘541 to provide an SRAM cell structure with improved connectivity and layout for advanced semiconductor processes.
Response to Arguments
Applicant’s amendments to claim 18 are sufficient to overcome the objection to claim 18 made in the non-final rejection filed 23 September 2025. The objection to claim 18 has been withdrawn.
Applicant’s arguments, see remarks, pp. 13-14, filed 23 December 2025, with respect to the 35 U.S.C. 112(b) rejections of claims 1-17 alleging that the claim language is unambiguous have been fully considered and are persuasive. The 35 U.S.C. 112(b) rejections of claims 1-17 have been withdrawn.
Applicant failed to supply arguments traversing the 35 U.S.C. 112(b) rejections of claims 19 and 20 made in the non-final rejection filed 23 December 2025. The outstanding 35 U.S.C. 112(b) rejections of claims 19 and 20 are maintained as set forth in the above rejection.
Applicant's arguments filed 23 December 2025 with respect to the 35 U.S.C. 112(a) rejections of claims 1-17 and the objections to the drawings and the specification have been fully considered but they are not persuasive.
Applicant argues (remarks, pp. 11-13) that the MPEP does not require that every claimed feature be described in the specification or shown in the same figure as part of a single embodiment; instead, the written description may be supported by the specification and the drawings taken as a whole. Examiner respectfully disagrees.
The outstanding 35 U.S.C. 112(a) rejections of claims 1-17 are raised not merely because the claimed features are not described in the specification or shown in the same figure as part of a single embodiment, but rather because there is no suggestion in the original disclosure that Applicant had in his or her possession the claimed subject matter in the combination of elements as claimed at the time the application was effectively filed. Although some of these claimed elements may be disclosed individually, there is insufficient disclosure to demonstrate that Applicant had in his or her possession each of the cited claimed elements in combination.
The corresponding objection to the specification for lacking antecedent basis for the claimed subject matter is supplied for similar reasons, namely that the specification fails to provide support for the claimed subject matter in the combination of elements as claimed.
The drawing[s] [ ] must show every feature of the invention specified in the claims. 37 C.F.R. 1.83(a). The outstanding objection to the drawings is maintained for failing to show the claimed subject matter in the combination of elements as claimed. Any structural detail that is of sufficient importance to be described should be shown in the drawing. Ex parte Good, 1911 C.D. 43, 164 OG 739 (Comm’r Pat. 1911).
Applicant's arguments filed 23 December 2025 with respect to the 35 U.S.C. 103 rejections of claims 1, 4, 9, 14, 16, and 18 have been fully considered but they are not persuasive.
Applicant argues (remarks, p. 16) that Esaki ‘395 fails to teach or suggest any metal area disposed on one side of the heavily doped source/drain regions (12/22) and horizontally connected to the heavily doped source/drain regions (12/22). Applicant further argues (remarks, p. 17) that Subbanna ‘698 fails to teach or suggest a heavily doped area disposed between the lightly doped area (34) and the metal area (33). Examiner respectfully disagrees.
One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Esaki ‘395 is not cited to teach the claimed metal area; rather, Subbanna ‘698 teaches this feature. Similarly, Subbanna ‘698 is not cited to teach the lightly doped area; rather, Esaki ‘395 teaches this feature.
Applicant argues (remarks, p. 17) a person of ordinary skill would understand that the STI fabrication flow of Esaki ‘395 cannot simply be applied to a device that requires metal areas in its source/drain regions as suggested by Subbanna ‘698 because the metal region disrupts the implantation, annealing, and self-alignment processes upon which Esaki '395 relies. Examiner respectfully disagrees.
Esaki ‘395 teaches (FIG. 1A) a drain region (5 and 12) and a source region (5 and 12) including a lightly doped area (5) and a heavily doped area (12) adjacent to the lightly doped area ([0107]) to prevent short channel effect ([0041]). The presence of the metal region (33) of Subbanna ‘698 would not prevent one of ordinary skill in the art from applying the lightly doped area of Esaki ‘395 to the transistor of Subbanna ‘698 with a reasonable expectation of success.
Applicant argues (remarks, pp. 18-19) that the contacts of Lau ‘282 are formed of metal rather than an epitaxial semiconductor material. Applicant further argues (remarks, pp. 19-21) that Yamamoto ‘887 teaches only a single epitaxial silicon layer, that the amorphous silicon layer (302) of Yamamoto ‘887 is not a second epitaxial semiconductor pillar, and that Yamamoto ‘887 does not disclose that a top of the second epitaxial pillar is higher than the upper surface of the first metal layer. Applicant maintains that there would be no motivation to modify Lau ‘282 to include stacked epitaxial semiconductor pillars. Examiner respectfully disagrees.
Lau ‘282 is not cited to teach the second epitaxial semiconductor pillar; rather, Yamamoto ‘887 is cited to teach address this feature. Without conceding to Applicant’s rebuttal, Examiner notes that the prior rejection relied on FIG. 4 of Yamamoto ‘887 to teach an epitaxial semiconductor pillar. In view of Applicant’s amendments, the rejection now relies on FIG. 7(b) of Yamamoto ‘887 which teaches the second epitaxial pillar (712) as claimed in an arrangement that prevents punch-through ([0013]).
Applicant argues (remarks, p. 23) that Liaw ‘541 never discloses that the gate (G2) of (PU2) is directly connected through only the word line contact (WLC) without any lower metal layers. Applicant maintains that the gate electrodes (G1 and G2) are connected to the first-level contacts (41 and 43) via butted contacts. Further, Applicant maintains that the elements (WLC) and (41) are two distinct layers of structures, and interpreting these elements as a single “first metal interconnection” is inconsistent with the actual layer hierarchy. Examiner respectfully disagrees.
Liaw ‘541 teaches a gate region (G2) of one transistor (PU2) connected to a source region or a drain region (55) of the one transistor directly through a first metal interconnection (WLC and 41) without another metal layer lower than the first metal interconnection ([0058]) as shown in FIG. 6. The claims do not exclude the first metal interconnection from comprising a plurality of metal layers. In this instance, the first metal interconnection may comprise both elements (WLC) and (41) along with any unnumbered butted contacts.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Sumi et al. (US Patent 5,597,739) teaches a source and drain regions comprising a metal area.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.R./Examiner, Art Unit 2893