Prosecution Insights
Last updated: May 29, 2026

Invention And Collaboration Laboratory Pte. Ltd.

8 pending office actions • 5 art units • 7 examiners • 0 of 8 (0%) have an AI response strategy ready • 9 patents granted in the last 365 days

Portfolio Summary

8
Total Pending OAs
7
Non-Final OAs
1
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 8 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

3
Overdue
1
Due this week
2
Due this month
1
Due in next 60 days
1
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 8 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (3)Due ≤ 7 days (1)Due ≤ 30 days (2)Due ≤ 60 days (1)Due later (1)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

0
Hard (0%)
8
Medium (100%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only6 (75%)
§102 only2 (25%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
8
Semiconductors
100% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

80 h
Manual time on pending OAs
16 h
Time saved (low, 20%)
28 h
Time saved (mid, 35%)
0.7 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
KOO, LAMONT B 2 80.5% +4.9%
TRAN, ANTHAN 1 82.9% +2.3%
RODELA, EDUARDO A 1 86.0% +5.6%
ANDERSON, WILLIAM H 1 85.7% +15.4%
SCHODDE, CHRISTOPHER A 1 52.9% +32.4%
PRIDEMORE, NATHAN ANDREW 1 73.8% +20.3%
ROLAND, CHRISTOPHER M 1 64.8% +21.4%

Quick Wins (5)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
18494783 SEMICONDUCTOR DEVICE STRUCTURE WITH VERTICAL TRANSISTOR OVER UNDERGROUND BIT LINE KOO, LAMONT B 50d overdue
18203688 PLANAR COMPLEMENTARY MOSFET STRUCTURE TO REDUCE LEAKAGES AND PLANAR AREAS RODELA, EDUARDO A 36d overdue
18770651 DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUIT TRAN, ANTHAN 32d overdue
18099677 INTEGRATED SCALING AND STRETCHING PLATFORM FOR SERVER PROCESSOR AND RACK SERVER UNIT ANDERSON, WILLIAM H 15d
18208388 TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME KOO, LAMONT B 61d

Interview Candidates (4)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.

App #TitleExaminerDue in
17395922 SRAM Cell Structures ROLAND, CHRISTOPHER M 5d
18099677 INTEGRATED SCALING AND STRETCHING PLATFORM FOR SERVER PROCESSOR AND RACK SERVER UNIT ANDERSON, WILLIAM H 15d
17875395 TRANSISTOR STRUCTURE SCHODDE, CHRISTOPHER A 23d
17528481 MANUFACTURE METHOD FOR INTERCONNECTION STRUCTURE PRIDEMORE, NATHAN ANDREW 33d

Top Art Units

Art UnitApps
2813 2
2893 2
2898 2
2825 1
2817 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
18770651 DYNAMIC MEMORY WITH SUSTAINABLE STORAGE ARCHITECTURE AND CLEAN UP CIRCUIT TRAN, ANTHAN 2825 §102 Non-Final OA 32d overdue Pending Jul 12, 2024
18494783 SEMICONDUCTOR DEVICE STRUCTURE WITH VERTICAL TRANSISTOR OVER UNDERGROUND BIT LINE KOO, LAMONT B 2813 §102 Non-Final OA 50d overdue Pending Oct 26, 2023
18208388 TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME KOO, LAMONT B 2813 §103 Non-Final OA 61d Pending Jun 12, 2023
18203688 PLANAR COMPLEMENTARY MOSFET STRUCTURE TO REDUCE LEAKAGES AND PLANAR AREAS RODELA, EDUARDO A 2893 §103 Non-Final OA 36d overdue Pending May 31, 2023
18099677 INTEGRATED SCALING AND STRETCHING PLATFORM FOR SERVER PROCESSOR AND RACK SERVER UNIT ANDERSON, WILLIAM H 2817 §103 Non-Final OA 15d Pending Jan 20, 2023
17875395 TRANSISTOR STRUCTURE SCHODDE, CHRISTOPHER A 2898 §103 Non-Final OA 23d Pending Jul 27, 2022
17528481 MANUFACTURE METHOD FOR INTERCONNECTION STRUCTURE PRIDEMORE, NATHAN ANDREW 2898 §103 Non-Final OA 33d Pending Nov 17, 2021
17395922 SRAM Cell Structures ROLAND, CHRISTOPHER M 2893 §103 Final Rejection 5d Pending Aug 06, 2021

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