DETAILED ACTION
This office action addresses Applicant’s response filed on 23 March 2026. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 8, and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fox (US 2009/0224408) in view of Balsdon (US 8,458,636) and Jung (US 2010/0133588).
Regarding claim 1, Fox discloses a method of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium (¶98), the method comprising: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction (Fig. 14A/B; ¶81); the routed patterns being functional in a representation of a circuit, the dummy patterns being non-functional in the representation of the circuit (¶81); and revising to form a revised layout diagram, the revising including: connecting first ends of the corresponding routed and dummy patterns; and connecting second ends of the corresponding routed and dummy patterns (¶¶81, 83);
wherein the identifying includes: selecting, as multiple candidate patterns, conductor patterns in the first conductance layer which overlaps, relative to a second direction that is perpendicular to the first direction, a portion of the routed pattern and setting, if the multiple candidate patterns are suitable for electrical coupling in parallel with the routed pattern, the multiple candidate patterns to be the dummy patterns (Figs. 14A/B; ¶¶81 (“one or more unused fill wires”), 83, 86); and
fabricating, based on the revised layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit (¶¶4, 49).
Fox does not appear to explicitly disclose that the selecting includes determining that all potential locations for the first and second jumper patterns are vacant in a second conductance layer. However, these limitations are strongly implied, if not inherent, in Fox. Fox discloses connecting the dummy pattern to the routed pattern using first and second jumper patterns on a second conductance layer and vias in an interconnection layer, and there are no conflicting/overlapping patterns (Fig. 14A/B; ¶¶73, 81, 83). Persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so. Balsdon also teaches selecting, as a candidate pattern, a conductor pattern in in the first conductance layer which overlaps, relative to a second direction that is perpendicular to the first direction, a portion of the routed pattern, that the selecting includes determining that all potential locations for the first and second jumper patterns are vacant in a second conductance layer; and setting, if the candidate pattern is suitable for electrical coupling in parallel with the routed pattern, the candidate pattern to be the dummy pattern (col. 14, lines 10-18).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox and Balsdon, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way to achieve the predictable results of connecting patterns in a valid way. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fox discloses routed patterns connected to selected dummy patterns. Persons having ordinary skill in the art would understand that such connections would only be selected if there was sufficient space, as taught by Balsdon. The teachings of Balsdon are directly applicable to Fox in the same way, so that Fox would select a dummy pattern to connect if the connection can be validly made.
If Fox is found to be unclear regarding multiple candidate/conductor patterns, Jung discloses the same (¶¶40, 43). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox, Balsdon, and Jung, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of connecting additional dummy patterns to further improve redundancy and/or capacitance. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fox discloses routed patterns connected to selected dummy patterns. Jung teaches connecting multiple dummy patterns, which persons having ordinary skill in the art would recognize is an obvious extension of Fox’s existing teachings. The teachings of Jung are directly applicable to Fox in the same way, so that Fox would similarly connect multiple dummy patterns to further improve redundancy and capacitance.
Regarding claims 3 and 14, Fox discloses that the selecting includes: determining that the multiple candidate patterns are non-functional conductor patterns (¶81), but does not appear to explicitly disclose determining that locations in an interconnection layer, which correspond to via patterns, are vacant. However, similarly to claim 1, these limitations are strongly implied, if not inherent, in Fox. Again, Fox discloses connecting the dummy pattern to the routed pattern using first and second jumper patterns on a second conductance layer and vias in an interconnection layer, and there are no conflicting/overlapping patterns (Fig. 14A/B; ¶¶73, 81, 83). Persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so, as taught by Balsdon (col. 14, lines 10-18). Motivation to combine remains consistent with claim 1.
Regarding claim 5, Fox discloses that the selecting includes determining that the at least one of the multiple candidate patterns is a functional conductor pattern and repeating the selecting for another candidate pattern (Figs. 12C, multiple functional conductors A1 connected together).
Regarding claim 8, Fox discloses that the first conductance layer represents a metallization layer (¶53).
Regarding claim 11, Fox discloses a system for revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium (¶98), the system comprising: at least one processor and at least one memory including computer program code for one or more programs (¶100); and wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute at least as follows:
identifying, as a routed pattern, a conductor pattern in a first conductance layer of the initial layout diagram which extends in a first direction and which is functional in a representation of a circuit (Fig. 14A/B; ¶¶81, 83);
selecting, as a candidate pattern, a conductor pattern in the first conductance layer that overlaps, relative to a second direction which is substantially perpendicular to the first direction, a portion of the routed pattern, the candidate pattern being non-functional in the representation of the circuit and setting, if the candidate pattern is suitable for electrical coupling in parallel with the routed pattern, the candidate pattern to be a dummy pattern (Fig. 14A/B; ¶¶81, 83); and
revising the initial layout diagram into a revised layout diagram, the revising including: connecting first ends of the corresponding routed and multiple dummy patterns with the first jumper pattern and connecting second ends of the corresponding routed and the multiple dummy patterns with the second jumper pattern (Figs. 12C, 13A, and 14A/B; ¶¶81 (“one or more unused fill wires”), 83, 86).
Fox does not appear to explicitly disclose that the selecting includes determining that all potential locations for the first and second jumper patterns are vacant in a second conductance layer. However, these limitations are strongly implied, if not inherent, in Fox. Fox discloses connecting the dummy pattern to the routed pattern using first and second jumper patterns on a second conductance layer and vias in an interconnection layer, and there are no conflicting/overlapping patterns (Fig. 14A/B; ¶¶73, 81, 83). Persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so. Balsdon also teaches selecting, as a candidate pattern, a conductor pattern in in the first conductance layer which overlaps, relative to a second direction that is perpendicular to the first direction, a portion of the routed pattern, that the selecting includes determining that all potential locations for the first and second jumper patterns are vacant in a second conductance layer; and setting, if the candidate pattern is suitable for electrical coupling in parallel with the routed pattern, the candidate pattern to be the dummy pattern (col. 14, lines 10-18). Motivation to combine remains consistent with claim 1.
If Fox is found to be unclear regarding multiple dummy patterns, Jung discloses the same (¶¶40, 43). Motivation to combine remains consistent with claim 1.
Regarding claim 12, Fox discloses at least one of: a masking facility configured to fabricate one or more semiconductor masks based on the revised layout diagram; or a fabricating facility configured to fabricate at least one component in a layer of a semiconductor integrated circuit based on the revised layout diagram (¶¶4, 49).
Regarding claim 13, Fox discloses that the masking facility is further configured, as an aspect included in fabrication of the one or more semiconductor masks, to perform one or more lithographic exposures based on the revised layout diagram; or the fabricating facility is further configured, as an aspect included in fabrication of the at least one component in a layer of the semiconductor integrated circuit, to perform one or more lithographic exposures based on the revised layout diagram (¶¶4, 5, 43, 49).
Claim(s) 2, 6, 7, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fox in view of Balsdon, Jung, and Leung (US 7,240,314).
Regarding claim 2, Fox does not appear to explicitly disclose that selecting the multiple candidate patterns comprises selecting the multiple candidate patterns based on prioritization. However, it is typical in the art of circuit design to prioritize or rank connection candidates according to known criteria, as taught by Leung (col. 17, lines 20-22). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox, Balsdon, Jung, and Leung, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar methods in the same way, to produce merely the predictable results of ranking connection candidates by known criteria in order to make preferred connections. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Fox discloses connecting unused dummy patterns and functional patterns, which persons having ordinary skill in the art would understand would involve checking if such connections can legally be made, as taught by Balsdon. Connection candidates are typically prioritized based on various criteria as taught by Leung. The teachings of Leung are directly applicable to Fox in the same way, so that Fox would prioritize the dummy patterns to connect to functional patterns based on known criteria, in order to make preferred connections.
Regarding claims 6, 7, and 15, Fox does not appear to explicitly disclose determining that one or more locations in a second conductance layer, which otherwise are to be used for the corresponding first and second jumper patterns, are not vacant; and repeating the selecting for another candidate pattern; and determining that one or more locations in an interconnection layer, which otherwise are to be used for one or more of via patterns, are not vacant; and repeating the selecting for another candidate pattern. As discussed above with regard to claims 1 and 3, persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so, as taught by Balsdon (col. 14, lines 10-18). Persons having ordinary skill in the art would further know that if the pattern cannot be routed, to repeat the selection with another candidate, as taught by Leung (col. 18, lines 1-3).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox, Balsdon, Jung, and Leung, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of finding a valid connection. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fox discloses routed patterns connected to selected dummy patterns. Persons having ordinary skill in the art would understand that such connections would only be selected if there were routing resources available to make the connection, as taught by Balsdon, and that a next candidate connection is selected if the connection cannot be made, as taught by Leung. The teachings of Balsdon and Leung are directly applicable to Fox in the same way, so that Fox would similarly find a candidate connection that can be validly made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fox in view of Balsdon, Jung, and Chao (US 5,790,417).
Regarding claim 4, Fox discloses that amongst not-yet-considered non-functional conductor patterns in the first conductance layer, and relative to the second direction, the multiple candidate patterns are not-yet-considered non- functional conductor patterns which are nearest to the routed pattern (Fig. 13A, 376 is the only non-functional conductor pattern near 361, and thus the nearest by definition). If Fox is found to be unclear regarding this limitation, Chao discloses the same (col. 2, lines 35-40). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox, Balsdon, Jung, and Chao, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of reducing necessary connection length. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Fox discloses connecting routed patterns to adjacent dummy patterns. Chao teaches that the adjacent dummy pattern is connected to the routed pattern, while other dummy patterns are not. The teachings of Chao are directly applicable to Fox in the same way, so that Fox would similarly connect routed patterns to adjacent dummy patterns, to reduced needed connection length.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fox in view of Balsdon, Jung, and He (US 2008/0237789).
Regarding claim 9, Fox does not appear to explicitly disclose that a functional conductor pattern represents a via pillar. However, via pillars are a well-known conductor structure, as taught by He (¶83). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox, Balsdon, Jung, and He, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of improving redundancy of conventional conductor types. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Fox discloses connecting a conductor to a dummy pattern to improve redundancy. Persons having ordinary skill in the art would know that a via pillar is a conventional conductor type, as taught by He. The teachings of He are directly applicable to Fox in the same way, so that Fox would similarly connect a conductor in a conventional via pillar to a dummy pattern to improve the redundancy of conventional via pillars.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fox in view of Balsdon, Jung, and Kosugi (US 2008/0104563).
Regarding claim 10, Fox does not appear to explicitly disclose performing a timing and ohmic loss analysis on the revised layout diagram. Kosugi discloses these limitations (¶5). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fox, Balsdon, Jung, and Kosugi, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of verifying correctness of the layout. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Fox discloses a revised layout. Persons having ordinary skill in the art would recognize that it is conventional to perform timing and ohmic loss analysis on the layout, as taught by Kosugi. The teachings of Kosugi are directly applicable to Fox in the same way, so that Fox would similarly perform timing and ohmic loss analysis on the revised layout, to verify correctness of the layout.
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shinomiya (US 2007/0272949) in view of Fox, Balsdon, and Jung.
Regarding claim 16, Shinomiya discloses a method of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium (¶107), the method comprising: identifying, in a first conductance layer of the initial layout diagram, first and second routed patterns and a dummy pattern, each of which extends in a first direction each of the first and second routed pattern being functional, and the dummy pattern being non-functional, in a representation of a circuit (¶42);
the initial layout diagram further including: first and second jumper patterns, in a second conductance layer, which extend in a second direction substantially perpendicular to the first direction and connecting the first and second jumper patterns and corresponding first and second ends correspondingly of the first routed patterns (¶¶115, 117); and
fabricating, based on the revised layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit (¶9).
Shinomiya does not appear to explicitly disclose revising the initial layout diagram into a revised layout diagram, the revising including: connecting first ends of the first and second jumper patterns and corresponding first ends and second ends of the dummy pattern; wherein the identifying includes: selecting, as a candidate pattern, a conductor pattern in in the first conductance layer which overlaps, relative to a second direction that is perpendicular to the first direction, a portion of the routed pattern and setting, if the candidate pattern is suitable for electrical coupling in parallel with the routed pattern, the candidate pattern to be the dummy pattern.
Fox discloses a method of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium (¶98), the method comprising: identifying, in a first conductance layer of the layout diagram, first and second routed patterns and a dummy pattern, each of which extends in a first direction (Figs. 13A/B and 14A/B; ); each of the first and second routed pattern being functional, and the dummy pattern being non-functional, in a representation of a circuit (¶81);
revising the layout diagram into a revised layout diagram, the revising including: connecting first ends of the first and second jumper patterns and corresponding first ends and second ends of the dummy pattern (¶¶80, 81, 83);
wherein the identifying includes: selecting, as a candidate pattern, a conductor pattern in in the first conductance layer which overlaps, relative to a second direction that is perpendicular to the first direction, a portion of the routed pattern and setting, if the candidate pattern is suitable for electrical coupling in parallel with the routed pattern, the candidate pattern to be the dummy pattern (Figs. 14A/B; ¶¶81, 83); and
fabricating, based on the revised layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit (¶¶4, 49).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shinomiya and Fox, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way to achieve the predictable results of revising layouts to improve redundancy and capacitance. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Shinomiya discloses a layout having functional and dummy patterns. Fox teaches revising the layout to connect the functional and dummy patterns to improve redundancy and capacitance. The teachings of Fox are directly applicable to Shinomiya in the same way, so that Shinomiya would similarly connect the functional and dummy patterns to improve redundancy and capacitance.
Shinomiya and Fox do not appear to explicitly disclose that the selecting includes determining that all potential locations for the first and second jumper patterns are vacant in a second conductance layer. However, these limitations are strongly implied, if not inherent, in Fox. Fox discloses connecting the dummy pattern to the routed pattern using first and second jumper patterns on a second conductance layer and vias in an interconnection layer, and there are no conflicting/overlapping patterns (Fig. 14A/B; ¶¶73, 81, 83). Persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so. Balsdon also teaches selecting, as a candidate pattern, a conductor pattern in in the first conductance layer which overlaps, relative to a second direction that is perpendicular to the first direction, a portion of the routed pattern, that the selecting includes determining that all potential locations for the first and second jumper patterns are vacant in a second conductance layer; and setting, if the candidate pattern is suitable for electrical coupling in parallel with the routed pattern, the candidate pattern to be the dummy pattern (col. 14, lines 10-18).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shinomiya, Fox, and Balsdon, because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way to achieve the predictable results of connecting patterns in a valid way. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Shinomiya discloses a layout having functional and dummy patterns, which Fox teaches are connected in order to improve redundancy and capacitance. Persons having ordinary skill in the art would understand that such connections would only be selected if there was sufficient space, as taught by Balsdon. The teachings of Balsdon are directly applicable to Shinomiya and Fox in the same way, so that Shinomiya and Fox would select a dummy pattern to connect if the connection can be validly made.
Shinomiya does not appear to explicitly disclose a plurality of dummy patterns. Fox (Figs. 14A/B; ¶¶81 (“one or more unused fill wires”), 83, 86) and Jung (¶¶40, 43) disclose these limitations. It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shinomiya, Balsdon, Fox, and Jung because doing so would have involved merely the routine use of a known technique to improve similar methods in the same way to achieve the predictable results of connecting additional dummy patterns to further improve redundancy and/or capacitance. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Shinomiya discloses a layout having functional and dummy patterns, which Fox teaches are connected in order to improve redundancy and capacitance. Jung teaches connecting multiple dummy patterns, which persons having ordinary skill in the art would recognize is an obvious extension of Fox’s existing teachings. The teachings of Fox and Jung are directly applicable to Shinomiya in the same way, so that Shinomiya would similarly connect multiple dummy patterns to functional patterns to further improve redundancy and capacitance.
Regarding claim 20, Shinomiya does not appear to explicitly disclose that the first and second routed pattern is between a first dummy pattern of the plurality of dummy patterns and a second dummy pattern of the plurality of dummy patterns. Fox (Figs. 14A/B) and Jung (¶¶40, 43) disclose these limitations. Motivation to combine remains consistent with claim 16.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shinomiya in view of Fox, Balsdon, Jung, and Leung.
Regarding claim 17, Shinomiya does not appear to explicitly disclose that selecting the candidate pattern comprises selecting the candidate pattern based on prioritization. However, it is typical in the art of circuit design to prioritize or rank connection candidates according to known criteria, as taught by Leung (col. 17, lines 20-22).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shinomiya, Fox, Balsdon, Jung, and Leung, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar methods in the same way, to produce merely the predictable results of ranking connection candidates by known criteria in order to make preferred connections. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Shinomiya discloses a layout having functional and dummy patterns. Fox discloses connecting unused dummy patterns and functional patterns, which persons having ordinary skill in the art would understand would involve checking if such connections can legally be made, as taught by Balsdon. Connection candidates are typically prioritized based on various criteria as taught by Leung. The teachings of Leung are directly applicable to Shinomiya and Fox in the same way, so that Shinomiya and Fox would prioritize the dummy patterns to connect to functional patterns based on known criteria, in order to make preferred connections.
Regarding claim 18, Shinomiya does not appear to explicitly disclose that the selecting includes: determining that the candidate pattern is a non-functional conductor pattern; Fox discloses these limitations (¶81). Shinomiya also does not appear to explicitly disclose determining that locations in an interconnection layer, which correspond to via patterns, are vacant. However, similarly to claim 16, these limitations are strongly implied, if not inherent, in Fox. Again, Fox discloses connecting the dummy pattern to the routed pattern using first and second jumper patterns on a second conductance layer and vias in an interconnection layer, and there are no conflicting/overlapping patterns (Fig. 14A/B; ¶¶73, 81, 83). Persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so, as taught by Balsdon (col. 14, lines 10-18). Motivation to combine remains consistent with claim 16 and 17.
Regarding claim 19, Shinomiya does not appear to explicitly disclose that the selecting includes one or more as follows: (A) including: determining that the candidate pattern is a functional conductor pattern; and repeating the selecting and determining for another candidate pattern; (B) including: determining that one or more locations in the second conductance layer, which otherwise are to be used for correspondingly extending the first and second jumper patterns, are not vacant; and repeating the selecting and determining for another candidate pattern; or (C) including: determining that one or more locations in an interconnection layer, which otherwise are to be used for one or more via patterns, are not vacant; and repeating the selecting for another candidate pattern. Fox discloses determining that the candidate pattern is a functional conductor pattern, and repeating the selecting and determining for another conductor pattern (Figs. 12C, multiple functional conductors A1 connected together). Furthermore, as discussed above with regard to claim 3, persons having ordinary skill in the art, reading Fox, would understand that successfully routing a pattern in a layout implies the availability of the space to do so, as taught by and Balsdon (col. 14, lines 10-18). Persons having ordinary skill in the art would further understand that if the pattern cannot be routed, repeating the selection with another candidate, as taught by Leung (col. 18, lines 1-3).
It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Shinomiya, Fox, Balsdon, Jung, and Leung, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of improving redundancy by finding a valid connection. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Shinomiya discloses a layout having functional and dummy patterns. Fox discloses connecting candidate functional and dummy patterns to improve redundancy. Persons having ordinary skill in the art would understand that such connections would only be selected if there were routing resources available to make the connections, as taught by Balsdon, and that a next candidate connection is selected if a connection cannot be made, as taught by Leung. The teachings of Fox, Balsdon, and Leung are directly applicable to Shinomiya in the same way, so that Shinomiya would similarly find a candidate connection that can be validly made.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection. Applicant asserts that the prior art fails to teach newly-added limitations, which are addressed above using newly-cited prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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18 August 2026
/ARIC LIN/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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