DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 26, 2025 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on November 26, 2025. Claims 13, 16, 23, 27 and 30 have been amended. New claims 35-39 have been added. Claims 1-12, 17-21, 31 and 33 have been canceled. Currently, claims 13-16, 22-30, 32 and 34-39 are pending.
Response to Arguments
Applicant has acknowledged that US 20210305178 A1 is commonly owned. Pursuant to 35 U.S.C. § 102(b)(2)(C), this reference is disqualified as prior art against the present claims because it was owned by the same person or subject to an obligation to the same person at the time the current invention was filed.
Election/Restrictions
Newly submitted claims 35 and 39 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: The applicant had originally elected species wherein the isolation break 152 had the sub-layer 142 completely recessed while a portion of the second sub-layer 144 extended continuously across the isolation break 152. However, the new claims are directed to another species for example, shown in Figure 1C, wherein both the sub-layers 142 and 144 are recessed in the isolation break 152. Note that the claims do not recite the sub-layer 144 to be partially recessed.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 35 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15, 22-29, 32, 34 and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over West et al. (US 2018/0286802 A1; hereafter West 802’) in view of in view of Bonifield et al (US 2019/0206812 A1; hereafter Bonifield).
Regarding claim 13, West 802’ teaches a method of forming a microelectronic device (see e.g., electronic device 100A, a high voltage capacitor, Figure 1A), comprising:
forming a first plate of a capacitor (see e.g., high voltage capacitor 104 includes a bottom plate 130, Paras [0020], [0023], Figure 1A) over a semiconductor substrate (see e.g., substrate 102 such as silicon wafer, Para [0020], Figure 1A):
forming one or more first dielectric layers above the first plate, the one or more first dielectric layers having a first dielectric constant (see e.g., intra-metal dielectric (IMD) layers 122 e.g., dielectric materials or compositions comprised of silicon dioxide-based materials and the like formed over the bottom plate 130, Para [0022], Figure 1A);
forming a second dielectric layer (see e.g., lower bandgap dielectric layer 140 including a sub-layer 142 of SiON and a sub-layer 144 of SiN, Para [0024], Figure 1A) on the one or more first dielectric layers (see e.g., lower-bandgap dielectric layer 140 formed on the IMD layers 122), the second dielectric layer having a second dielectric constant greater than the first dielectric constant of the one or more first dielectric layers (see e.g., lower bandgap dielectric layer 140 formed of SiON and SiN, which are known to be of a higher dielectric constant than that of silicon oxide forming the IMD layers 122, Para [0024]);
forming a second plate of the capacitor (see e.g., top plate 132 of the high voltage capacitor 104, Para [0023], Figure 1A) on the second dielectric layer (see e.g., top plate 132 formed on the lower- bandgap dielectric layer 140), the second plate having a lower corner contacting the second dielectric layer (see e.g., lower corner of top plate 132 contacts the sub-layer 144, Figure 1A);
forming an electric field abatement structure encircling the second plate by removing a portion of the second dielectric layer in an isolation break of the electric field abatement structure; (see e.g., a lateral isolation break 150 in the lower-bandgap dielectric layer 140 contacting the top plate 132 such that the isolation break 150 may at least partially circumscribe the top plate 132. The lateral isolation break 150 may therefore be located between the top plate 132 and any low voltage element of the microelectronic device 100A, so that the lower-bandgap dielectric layer 140 contacting the top plate 132 does not contact any low voltage element, Para [0024], Figure 1A);
forming a first faraday cage adjacent to the capacitor (see e.g., the inner faraday cage, Para [0020], Figure 1A),
the first faraday cage laterally surrounding the first (see e.g., as shown in Figure 1A the inner faraday cage surrounds the bottom plate 130);
forming a second faraday cage (see e.g., outer faraday cage, Para [0020], Figure 1A) adjacent to the first faraday cage, the second faraday cage laterally surrounding the first faraday cage, wherein the first faraday cage is located between the second faraday cage and the capacitor (see e.g., the outer faraday cage laterally surrounds the inner faraday cage wherein the inner faraday cage is located between the outer faraday cage and the high voltage capacitor 104, Figure 1A); and
forming a protective overcoat (PO) layer (see e.g., upper IMD layer 156, Para [0027], Figure 1A) on the second dielectric layer (see e.g., formed on the lower-bandgap dielectric layer 140, Figure 1A),
West 802’ does not explicitly teach
“the first faraday cage laterally surrounding the first and second plates”
A change in size or proportion is held to be an obvious matter of design choice. See In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See MPEP 2144.04.
In a similar field of endeavor Bonifield teaches a high voltage capacitor where the multiple columns of metal levels (e.g., Mn to Mn-4) connected by vias laterally surround the bottom plate 129 and the top plate 128 as shown in for example, the cross-sectional view of Figure 2E.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bonifield’s teachings of metal interconnects surrounding the first and the second plate in the method of West 802’ so that the metal layers and via stacks provide improved integrated shielding.
West 802’ does not explicitly teach
“the PO layer overlapping partway onto the second plate”
A rearrangement or parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Bonifield teaches
the PO layer overlapping partway onto the second plate (see e.g., dielectric layer 225, dielectric layer 161 and dielectric layer 162 which serve as protective layers overlap the top plate 128, Para [0044], Figure 2E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bonifield teachings of the PO layer overlapping partway onto the second plate in the method of West 802’ as a mere arrangement of parts for protection purposes.
Regarding claim 14, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ further teaches
wherein the second dielectric layer (see e.g., lower-bandgap dielectric layer 140, Para [0024], Figure 1A) includes a first sublayer (see e.g., sub-layer 144 that includes SiN, Para [0024]) having a third dielectric constant (see e.g., dielectric constant of SiN) and a second sublayer (see e.g., sub-layer 142 that includes SiON, Para [0024]) having a fourth dielectric constant (see e.g., dielectric constant of SiON) less than the third dielectric constant (see e.g., SiON has a dielectric constant less than the dielectric constant of SiN, Para [0024]).
Regarding claim 15, West 802’, as modified by Bonifield teaches the limitations of claim 14 as mentioned above. West 802’ further teaches
wherein the first sublayer includes silicon nitride (see e.g., sub-layer 144 is SiN, Para [0024]) and the second sublayer includes silicon oxynitride (see e.g., sub-layer 142 is SiON, Para [0024]).
Regarding claim 22, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ further teaches
forming a second PO layer (see e.g., layer 160, Para [0027], Figure 1A) on the PO layer (see e.g., layer 160 formed on the upper IMD layer 156, Para [0027], Figure 1A), the second PO layer having a curved sidewall profile over the second plate (see e.g., layer 160 may overlap edges of top plate 132 and has a curved sidewall profile that is, a slope of approximately 20°, Para [0027], Figure 1A).
West 802’ does not explicitly teach
“the second PO layer overlapping partway over the second plate”
A rearrangement or parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Bonifield teaches
the second PO layer overlapping partway over the second plate (see e.g., dielectric layer 225, dielectric layer 161 and dielectric layer 162 which serve as protective layers overlap the top plate 128, Para [0044], Figure 2E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bonifield teachings of the second PO layer overlapping partway onto the second plate in the method of West 802’ as a mere arrangement of parts for protection purposes.
Regarding claim 23, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ further teaches
wherein the second dielectric layer between the isolation break and the lower corner provides a shelf of the electric field abatement structure (see e.g., extension 151 of the lower-bandgap dielectric layer 140 between the lower corner of the top plate 132 and the isolation break 150 provides a shelf of the electric field abatement structure as shown in Figure 1A).
Regarding claim 24, West 802’, as modified by Bonifield teaches the limitations of claim 14 as mentioned above. West 802’ further teaches
wherein the fourth dielectric constant (see e.g., dielectric constant of SiON layer 142, Para [0024]) is greater than the first dielectric constant (see e.g., SiON known to be of a higher dielectric constant than that of silicon oxide forming the IMD layers 122, Para [0024]).
Regarding claim 25, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ further teaches
wherein: the …. second faraday cages extend from the semiconductor substrate through the second dielectric layer (see e.g., the outer faraday cage extends from the semiconductor substrate 102 through the lower-bandgap dielectric layer 140 as shown in Figure 1A).
West 802’ does not explicitly teach
“wherein: the first …faraday cages extend from the semiconductor substrate through the second dielectric layer”
A change in size or proportion is held to be an obvious matter of design choice. See In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See MPEP 2144.04.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to extend the first faraday cage through the second dielectric layer in order to provide improved shielding.
Regarding claim 26, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ does not explicitly teach
“wherein the first and second faraday cages have a same height from the semiconductor substrate”.
A change in size or proportion is held to be an obvious matter of design choice. See In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See MPEP 2144.04.
In a similar field of endeavor Bonifield teaches a high voltage capacitor where multiple columns of similar heights from the substrate 210 including metal levels (e.g., Mn to Mn-4) connected by vias laterally surround the bottom plate 129 and the top plate 128 as shown in for example, the cross-sectional view of Figure 2E.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bonifield’s teachings of metal columns including metal layers and via stacks of similar heights from the substrate in the method of West 802’ so that they may provide integrated shielding.
Regarding claim 27, West 802’ teaches a method of forming a microelectronic device (see e.g., electronic device 100A, a high voltage capacitor, Figure 1A), comprising:
forming a bottom capacitor plate (see e.g., high voltage capacitor 104 includes a bottom plate 130, Paras [0020], [0023], Figure 1A) over a substrate, the substrate including a semiconductor material (see e.g., substrate 102 such as silicon wafer, Para [0020], Figure 1A);
forming one or more first dielectric layers above the bottom capacitor plate (see e.g., intra-metal dielectric (IMD) layers 122 e.g., dielectric materials or compositions comprised of silicon dioxide-based materials and the like formed over the bottom plate 130, Para [0022], Figure 1A);
forming a second dielectric layer on the one or more first dielectric layers (see e.g., lower bandgap dielectric layer 140 including a sub-layer 142 of SiON and a sub-layer 144 of SiN, Para [0024], Figure 1A), the second dielectric layer including at least a first sublayer (see e.g., lower-bandgap dielectric layer 140 includes a sub-layer 144 made of SiN, Para [0024], Figure 1A) having a first dielectric constant (see e.g., dielectric constant of SiN) greater than one or more dielectric constants of the one or more first dielectric layers (see e.g., known that the dielectric constant of SiN is greater than the dielectric constant of SiO2);
forming a top capacitor plate (see e.g., top plate 132 of the high voltage capacitor 104, Para [0023], Figure 1A) on the second dielectric layer (see e.g., top plate 132 formed on the lower bandgap dielectric layer 140), the top capacitor plate having a lower corner contacting the second dielectric layer (see e.g., lower corner of top plate 132 contacts the sub-layer 144, Figure 1A);
forming an electric field abatement structure encircling the second plate by removing a portion of the first sublayer in an isolation break of the electric field abatement structure (see e.g., a lateral isolation break 150 in the sub-layer 144, such that the isolation break 150 may at least partially circumscribe the top plate 132. The isolation break 150 may therefore be located between the top plate 132 and any low voltage element of the microelectronic device 100A, so that the lower-bandgap dielectric layer 140 contacting the top plate 132 does not contact any low voltage element, Para [0024], Figure 1A);
forming a first faraday cage adjacent to and laterally surrounding the top and bottom
capacitor plates (see e.g., the inner faraday cage surrounding the bottom plate 130, Para [0020], Figure 1A), the first faraday cage extending from the substrate through the second dielectric layer; and
forming a second faraday cage (see e.g., outer faraday cage, Para [0020], Figure 1A) laterally surrounding the first faraday cage, wherein the first faraday cage is located between the second faraday cage and the top and bottom capacitor plates (see e.g., the outer faraday cage laterally surrounds the inner faraday cage wherein the inner faraday cage is located between the outer faraday cage and the top and bottom plates 130 and 132 respectively, of the high voltage capacitor 104, Figure 1A).
West 802’ does not explicitly teach
“forming a first faraday cage adjacent to and laterally surrounding the top and bottom
capacitor plates,
the first faraday cage extending from the substrate through the second dielectric layer; and
the first and second faraday cages having a same height from the substrate”,
A change in size or proportion is held to be an obvious matter of design choice. See In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See MPEP 2144.04.
In a similar field of endeavor Bonifield teaches a high voltage capacitor where multiple columns of similar heights from the substrate 210 including metal levels (e.g., Mn to Mn-4) connected by vias laterally surround the bottom plate 129 and the top plate 128 as shown in for example, the cross-sectional view of Figure 2E.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bonifield’s teachings of metal columns including metal layers and via stacks of similar heights from the substrate and surrounding the top and bottom plates in the method of West 802’ so that they may provide improved integrated shielding.
Regarding claim 28, West 802’, as modified by Bonifield teaches the limitations of claim 27 as mentioned above. West 802’ further teaches
wherein the second faraday cage extends from the substrate through the second dielectric layer (see e.g., the outer faraday cage extends from the semiconductor substrate 102 through the lower-bandgap dielectric layer 140 as shown in Figure 1A).
Regarding claim 29, West 802’, as modified by Bonifield teaches the limitations of claim 27 as mentioned above. West 802’ further teaches
wherein forming the second dielectric layer (see e.g., lower-bandgap dielectric layer 140, Para [0024], Figure 1A) includes, before forming the first sublayer (see e.g., sub-layer 144 that includes SiN, Para [0024]), forming a second sublayer (see e.g., sub-layer 142 that includes SiON, Para [0024]) on the one or more first dielectric layers (see e.g., sub-layer 142 formed on the IMD layer 122), the second sublayer having a second dielectric constant less than the first dielectric constant (see e.g., SiON has a dielectric constant which is known to be less than the dielectric constant of SiN).
Regarding claim 32, West 802’, as modified by Bonifield teaches the limitations of claim 29 as mentioned above. West 802’ further teaches
wherein the second dielectric constant (see e.g., dielectric constant of the SiON sub-layer 142, Para [0024]) is greater than the one or more dielectric constants of the one or more first dielectric layers (see e.g., dielectric constant of SiO2 IMD layers 122. Dielectric constant of SiO2 is less than the dielectric constant of SiON).
Regarding claim 34, West 802’, as modified by Bonifield teaches the limitations of claim 27 as mentioned above. West 802’ further teaches
forming a first protective overcoat (PO) layer (see e.g., upper IMD layer 156, Para [0027], Figure 1A) on the second dielectric layer (see e.g., formed on the lower-bandgap dielectric layer 140, Figure 1A),
forming a second PO layer (see e.g., layer 160, Para [0027], Figure 1A) on the first PO layer (see e.g., layer 160 formed on the upper IMD layer 156, Para [0027], Figure 1A), the second PO layer having a curved sidewall profile over the second plate (see e.g., layer 160 may overlap edges of top plate 132 and has a curved sidewall profile that is, a slope of approximately 20°, Para [0027], Figure 1A).
West 802’ does not explicitly teach
“the first PO layer overlapping partway onto the top capacitor plate;
the second PO layer overlapping partway over the top capacitor plate”
A rearrangement or parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Bonifield teaches
the first PO layer overlapping partway onto the top capacitor plate;
the second PO layer overlapping partway over the top capacitor plate (see e.g., dielectric layer 225, dielectric layer 161 and dielectric layer 162 which serve as protective layers overlap the top plate 128, Para [0044], Figure 2E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bonifield teachings of the first PO layer overlapping partway onto the top capacitor plate; the second PO layer overlapping partway over the top capacitor plate in the method of West 802’ as a mere arrangement of parts for protection purposes.
Regarding claim 36, West 802’, as modified by Bonifield teaches the limitations of claim 27 as mentioned above. West 802’ further teaches
wherein the first faraday cage is closer to the electric field abatement structure than the lower corner of the top capacitor plate (see e.g., the inner faraday cage is closer to the lateral isolation break 150 than the lower corner of the top plate 132, which is separated from the lateral isolation break 150 by a distance 146 as shown in Figure 1A).
Regarding claim 37, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ further teaches
wherein:
forming the electric field abatement structure includes forming a recess in the second dielectric layer (see e.g., lateral isolation break 150 includes a recess formed in the lower-bandgap dielectric layer 140, Para [0024], Figure 1A);
the recess includes a first sidewall and an opposing second sidewall, the first sidewall being closer to the lower corner of the second plate than the second sidewall, and the second sidewall being closer to the first faraday cage than the first sidewall; and (see e.g., as shown in Figure 1A the recess forming the lateral isolation break 150 has a sidewall closer to the top plate 132 and another opposite sidewall closer to the inner faraday cage)
the first faraday cage is positioned closer to the second sidewall of the recess than the lower corner of the second plate is positioned to the first sidewall of the recess (see e.g., the inner faraday cage is closer to the recess forming the lateral isolation break 150 than the lower corner of the top plate 132, which is separated from the lateral isolation break 150 by a distance 146 as shown in Figure 1A).
Regarding claim 38, West 802’, as modified by Bonifield teaches the limitations of claim 13 as mentioned above. West 802’ further teaches
wherein:
forming the electric field abatement structure includes forming a recess in the second dielectric layer (see e.g., lateral isolation break 150 includes a recess formed in the lower-bandgap dielectric layer 140, Para [0024], Figure 1A);
the recess includes a first sidewall and an opposing second sidewall, the first sidewall being closer to the lower corner of the second plate than the second sidewall, and the second sidewall being closer to the first faraday cage than the first sidewall; and (see e.g., as shown in Figure 1A the recess forming the lateral isolation break 150 has a sidewall closer to the top plate 132 and another opposite sidewall closer to the inner faraday cage)
the first sidewall of the recess is separated from the lower corner of the second plate by at least 14 microns (see e.g., the sidewall of the recess is separated from the lower corner of the top plate by a lateral distance 146 which is at least twice a thickness 148 of the lower-bandgap dielectric layer 140. The thickness 148 is around 1.2 microns (thickness of each first sub-layer 142 and second sub-layer 144 being around 0.6 microns); hence lateral distance 146 is at least 2.4 microns. Accordingly, the distance maybe equal to 2.4 microns or any value greater than 2.4 microns, Para [0024], Figure 1A).
Claims 16 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over West et al. (US 2018/0286802 A1; hereafter West 802’) in view of in view of Bonifield et al (US 2019/0206812 A1; hereafter Bonifield) and further in view of West et al. (US 2017/0263696 A1; hereafter West 696’).
Regarding claim 16, West 802’, as modified by Bonifield teaches the limitations of claim 14 as mentioned above. West 802’ does not explicitly teach
“wherein removing the portion of the second dielectric layer in the isolation break leaves at least a portion of the second sublayer extending across the isolation break”.
In a similar field of endeavor West 696’ teaches
wherein removing the portion of the second dielectric layer in the isolation break leaves at least a portion of the second sublayer extending across the isolation break (see e.g., The isolation break 150 may protrude partially into the first sub-layer 142 but without completely separating the first sub-layer 142 into two separate portions. Thus, the first sub-layer 142 extends under the isolation break 140 and contiguously coextends with the first (main) dielectric layer 136 thereunder. As such, the first sub-layer 142 covers a wider area than the first portion 151 of the second sub-layer 144. Landing the isolation break 150 slightly into the first sub-layer 142 provides several advantages over fully extending the isolation break 150 into and through the first sub-layer 142, Paras [0015]- [0016], [0018], [0020], Figures 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement West 696’s teachings of wherein removing the portion of the second dielectric layer in the isolation break leaves at least a portion of the second sublayer extending across the isolation break in the method of West 802’ since the contiguous first sub-layer may advantageously enhance the surge protection provided by the isolated first portion of the second sub-layer without incurring any design penalty. Second, by not substantially extending into the first sub-layer, the isolation break can be fabricated with a lower-cost process as well. Third, by landing within the first sub-layer, the isolation break enhances the overall breakdown strength and surge performance of the high voltage component.
Regarding claim 30, West 802’, as modified by Bonifield teaches the limitations of claim 29 as mentioned above. West 802’ further teaches
“wherein removing the first sublayer in the isolation break leaves at least a portion of the second sublayer extending across the isolation break”.
In a similar field of endeavor West 696’ teaches
wherein removing the first sublayer in the isolation break leaves at least a portion of the second sublayer extending across the isolation break (see e.g., The isolation break 150 may protrude partially into the first sub-layer 142 but without completely separating the first sub-layer 142 into two separate portions. Thus, the first sub-layer 142 extends under the isolation break 140 and contiguously coextends with the first (main) dielectric layer 136 thereunder. As such, the first sub-layer 142 covers a wider area than the first portion 151 of the second sub-layer 144. Landing the isolation break 150 slightly into the first sub-layer 142 provides several advantages over fully extending the isolation break 150 into and through the first sub-layer 142, Paras [0015]- [0016], [0018], [0020], Figures 1).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement West 696’s teachings of wherein removing the first sublayer in the isolation break leaves at least a portion of the second sublayer extending across the isolation break in the method of West since the contiguous first sub-layer may advantageously enhance the surge protection provided by the isolated first portion of the second sub-layer without incurring any design penalty. Second, by not substantially extending into the first sub-layer, the isolation break can be fabricated with a lower-cost process as well. Third, by landing within the first sub-layer, the isolation break enhances the overall breakdown strength and surge performance of the high voltage component.
Conclusion
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893